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1 /* |
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2 * i386 virtual CPU header |
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3 * |
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4 * Copyright (c) 2003 Fabrice Bellard |
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5 * |
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6 * This library is free software; you can redistribute it and/or |
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7 * modify it under the terms of the GNU Lesser General Public |
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8 * License as published by the Free Software Foundation; either |
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9 * version 2 of the License, or (at your option) any later version. |
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10 * |
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11 * This library is distributed in the hope that it will be useful, |
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12 * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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14 * Lesser General Public License for more details. |
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15 * |
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16 * You should have received a copy of the GNU Lesser General Public |
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17 * License along with this library; if not, write to the Free Software |
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18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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19 */ |
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20 #ifndef CPU_I386_H |
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21 #define CPU_I386_H |
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22 |
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23 #include "config.h" |
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24 |
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25 #ifdef TARGET_X86_64 |
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26 #define TARGET_LONG_BITS 64 |
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27 #else |
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28 #define TARGET_LONG_BITS 32 |
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29 #endif |
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30 |
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31 /* target supports implicit self modifying code */ |
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32 #define TARGET_HAS_SMC |
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33 /* support for self modifying code even if the modified instruction is |
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34 close to the modifying instruction */ |
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35 #define TARGET_HAS_PRECISE_SMC |
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36 |
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37 #define TARGET_HAS_ICE 1 |
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38 |
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39 #ifdef TARGET_X86_64 |
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40 #define ELF_MACHINE EM_X86_64 |
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41 #else |
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42 #define ELF_MACHINE EM_386 |
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43 #endif |
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44 |
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45 #include "cpu-defs.h" |
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46 |
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47 #include "softfloat.h" |
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48 |
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49 #define R_EAX 0 |
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50 #define R_ECX 1 |
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51 #define R_EDX 2 |
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52 #define R_EBX 3 |
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53 #define R_ESP 4 |
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54 #define R_EBP 5 |
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55 #define R_ESI 6 |
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56 #define R_EDI 7 |
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57 |
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58 #define R_AL 0 |
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59 #define R_CL 1 |
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60 #define R_DL 2 |
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61 #define R_BL 3 |
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62 #define R_AH 4 |
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63 #define R_CH 5 |
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64 #define R_DH 6 |
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65 #define R_BH 7 |
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66 |
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67 #define R_ES 0 |
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68 #define R_CS 1 |
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69 #define R_SS 2 |
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70 #define R_DS 3 |
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71 #define R_FS 4 |
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72 #define R_GS 5 |
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73 |
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74 /* segment descriptor fields */ |
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75 #define DESC_G_MASK (1 << 23) |
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76 #define DESC_B_SHIFT 22 |
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77 #define DESC_B_MASK (1 << DESC_B_SHIFT) |
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78 #define DESC_L_SHIFT 21 /* x86_64 only : 64 bit code segment */ |
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79 #define DESC_L_MASK (1 << DESC_L_SHIFT) |
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80 #define DESC_AVL_MASK (1 << 20) |
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81 #define DESC_P_MASK (1 << 15) |
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82 #define DESC_DPL_SHIFT 13 |
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83 #define DESC_DPL_MASK (1 << DESC_DPL_SHIFT) |
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84 #define DESC_S_MASK (1 << 12) |
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85 #define DESC_TYPE_SHIFT 8 |
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86 #define DESC_A_MASK (1 << 8) |
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87 |
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88 #define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */ |
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89 #define DESC_C_MASK (1 << 10) /* code: conforming */ |
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90 #define DESC_R_MASK (1 << 9) /* code: readable */ |
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91 |
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92 #define DESC_E_MASK (1 << 10) /* data: expansion direction */ |
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93 #define DESC_W_MASK (1 << 9) /* data: writable */ |
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94 |
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95 #define DESC_TSS_BUSY_MASK (1 << 9) |
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96 |
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97 /* eflags masks */ |
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98 #define CC_C 0x0001 |
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99 #define CC_P 0x0004 |
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100 #define CC_A 0x0010 |
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101 #define CC_Z 0x0040 |
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102 #define CC_S 0x0080 |
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103 #define CC_O 0x0800 |
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104 |
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105 #define TF_SHIFT 8 |
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106 #define IOPL_SHIFT 12 |
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107 #define VM_SHIFT 17 |
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108 |
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109 #define TF_MASK 0x00000100 |
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110 #define IF_MASK 0x00000200 |
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111 #define DF_MASK 0x00000400 |
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112 #define IOPL_MASK 0x00003000 |
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113 #define NT_MASK 0x00004000 |
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114 #define RF_MASK 0x00010000 |
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115 #define VM_MASK 0x00020000 |
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116 #define AC_MASK 0x00040000 |
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117 #define VIF_MASK 0x00080000 |
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118 #define VIP_MASK 0x00100000 |
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119 #define ID_MASK 0x00200000 |
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120 |
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121 /* hidden flags - used internally by qemu to represent additional cpu |
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122 states. Only the CPL, INHIBIT_IRQ, SMM and SVMI are not |
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123 redundant. We avoid using the IOPL_MASK, TF_MASK and VM_MASK bit |
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124 position to ease oring with eflags. */ |
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125 /* current cpl */ |
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126 #define HF_CPL_SHIFT 0 |
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127 /* true if soft mmu is being used */ |
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128 #define HF_SOFTMMU_SHIFT 2 |
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129 /* true if hardware interrupts must be disabled for next instruction */ |
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130 #define HF_INHIBIT_IRQ_SHIFT 3 |
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131 /* 16 or 32 segments */ |
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132 #define HF_CS32_SHIFT 4 |
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133 #define HF_SS32_SHIFT 5 |
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134 /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */ |
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135 #define HF_ADDSEG_SHIFT 6 |
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136 /* copy of CR0.PE (protected mode) */ |
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137 #define HF_PE_SHIFT 7 |
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138 #define HF_TF_SHIFT 8 /* must be same as eflags */ |
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139 #define HF_MP_SHIFT 9 /* the order must be MP, EM, TS */ |
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140 #define HF_EM_SHIFT 10 |
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141 #define HF_TS_SHIFT 11 |
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142 #define HF_IOPL_SHIFT 12 /* must be same as eflags */ |
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143 #define HF_LMA_SHIFT 14 /* only used on x86_64: long mode active */ |
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144 #define HF_CS64_SHIFT 15 /* only used on x86_64: 64 bit code segment */ |
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145 #define HF_OSFXSR_SHIFT 16 /* CR4.OSFXSR */ |
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146 #define HF_VM_SHIFT 17 /* must be same as eflags */ |
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147 #define HF_SMM_SHIFT 19 /* CPU in SMM mode */ |
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148 #define HF_SVME_SHIFT 20 /* SVME enabled (copy of EFER.SVME) */ |
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149 #define HF_SVMI_SHIFT 21 /* SVM intercepts are active */ |
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150 |
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151 #define HF_CPL_MASK (3 << HF_CPL_SHIFT) |
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152 #define HF_SOFTMMU_MASK (1 << HF_SOFTMMU_SHIFT) |
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153 #define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT) |
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154 #define HF_CS32_MASK (1 << HF_CS32_SHIFT) |
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155 #define HF_SS32_MASK (1 << HF_SS32_SHIFT) |
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156 #define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT) |
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157 #define HF_PE_MASK (1 << HF_PE_SHIFT) |
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158 #define HF_TF_MASK (1 << HF_TF_SHIFT) |
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159 #define HF_MP_MASK (1 << HF_MP_SHIFT) |
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160 #define HF_EM_MASK (1 << HF_EM_SHIFT) |
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161 #define HF_TS_MASK (1 << HF_TS_SHIFT) |
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162 #define HF_IOPL_MASK (3 << HF_IOPL_SHIFT) |
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163 #define HF_LMA_MASK (1 << HF_LMA_SHIFT) |
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164 #define HF_CS64_MASK (1 << HF_CS64_SHIFT) |
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165 #define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT) |
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166 #define HF_VM_MASK (1 << HF_VM_SHIFT) |
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167 #define HF_SMM_MASK (1 << HF_SMM_SHIFT) |
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168 #define HF_SVME_MASK (1 << HF_SVME_SHIFT) |
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169 #define HF_SVMI_MASK (1 << HF_SVMI_SHIFT) |
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170 |
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171 /* hflags2 */ |
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172 |
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173 #define HF2_GIF_SHIFT 0 /* if set CPU takes interrupts */ |
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174 #define HF2_HIF_SHIFT 1 /* value of IF_MASK when entering SVM */ |
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175 #define HF2_NMI_SHIFT 2 /* CPU serving NMI */ |
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176 #define HF2_VINTR_SHIFT 3 /* value of V_INTR_MASKING bit */ |
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177 |
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178 #define HF2_GIF_MASK (1 << HF2_GIF_SHIFT) |
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179 #define HF2_HIF_MASK (1 << HF2_HIF_SHIFT) |
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180 #define HF2_NMI_MASK (1 << HF2_NMI_SHIFT) |
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181 #define HF2_VINTR_MASK (1 << HF2_VINTR_SHIFT) |
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182 |
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183 #define CR0_PE_SHIFT 0 |
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184 #define CR0_MP_SHIFT 1 |
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185 |
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186 #define CR0_PE_MASK (1 << 0) |
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187 #define CR0_MP_MASK (1 << 1) |
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188 #define CR0_EM_MASK (1 << 2) |
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189 #define CR0_TS_MASK (1 << 3) |
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190 #define CR0_ET_MASK (1 << 4) |
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191 #define CR0_NE_MASK (1 << 5) |
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192 #define CR0_WP_MASK (1 << 16) |
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193 #define CR0_AM_MASK (1 << 18) |
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194 #define CR0_PG_MASK (1 << 31) |
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195 |
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196 #define CR4_VME_MASK (1 << 0) |
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197 #define CR4_PVI_MASK (1 << 1) |
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198 #define CR4_TSD_MASK (1 << 2) |
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199 #define CR4_DE_MASK (1 << 3) |
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200 #define CR4_PSE_MASK (1 << 4) |
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201 #define CR4_PAE_MASK (1 << 5) |
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202 #define CR4_PGE_MASK (1 << 7) |
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203 #define CR4_PCE_MASK (1 << 8) |
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204 #define CR4_OSFXSR_SHIFT 9 |
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205 #define CR4_OSFXSR_MASK (1 << CR4_OSFXSR_SHIFT) |
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206 #define CR4_OSXMMEXCPT_MASK (1 << 10) |
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207 |
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208 #define DR6_BD (1 << 13) |
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209 #define DR6_BS (1 << 14) |
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210 #define DR6_BT (1 << 15) |
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211 #define DR6_FIXED_1 0xffff0ff0 |
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212 |
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213 #define DR7_GD (1 << 13) |
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214 #define DR7_TYPE_SHIFT 16 |
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215 #define DR7_LEN_SHIFT 18 |
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216 #define DR7_FIXED_1 0x00000400 |
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217 |
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218 #define PG_PRESENT_BIT 0 |
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219 #define PG_RW_BIT 1 |
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220 #define PG_USER_BIT 2 |
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221 #define PG_PWT_BIT 3 |
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222 #define PG_PCD_BIT 4 |
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223 #define PG_ACCESSED_BIT 5 |
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224 #define PG_DIRTY_BIT 6 |
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225 #define PG_PSE_BIT 7 |
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226 #define PG_GLOBAL_BIT 8 |
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227 #define PG_NX_BIT 63 |
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228 |
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229 #define PG_PRESENT_MASK (1 << PG_PRESENT_BIT) |
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230 #define PG_RW_MASK (1 << PG_RW_BIT) |
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231 #define PG_USER_MASK (1 << PG_USER_BIT) |
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232 #define PG_PWT_MASK (1 << PG_PWT_BIT) |
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233 #define PG_PCD_MASK (1 << PG_PCD_BIT) |
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234 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT) |
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235 #define PG_DIRTY_MASK (1 << PG_DIRTY_BIT) |
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236 #define PG_PSE_MASK (1 << PG_PSE_BIT) |
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237 #define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT) |
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238 #define PG_NX_MASK (1LL << PG_NX_BIT) |
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239 |
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240 #define PG_ERROR_W_BIT 1 |
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241 |
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242 #define PG_ERROR_P_MASK 0x01 |
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243 #define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT) |
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244 #define PG_ERROR_U_MASK 0x04 |
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245 #define PG_ERROR_RSVD_MASK 0x08 |
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246 #define PG_ERROR_I_D_MASK 0x10 |
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247 |
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248 #define MSR_IA32_TSC 0x10 |
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249 #define MSR_IA32_APICBASE 0x1b |
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250 #define MSR_IA32_APICBASE_BSP (1<<8) |
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251 #define MSR_IA32_APICBASE_ENABLE (1<<11) |
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252 #define MSR_IA32_APICBASE_BASE (0xfffff<<12) |
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253 |
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254 #define MSR_IA32_SYSENTER_CS 0x174 |
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255 #define MSR_IA32_SYSENTER_ESP 0x175 |
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256 #define MSR_IA32_SYSENTER_EIP 0x176 |
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257 |
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258 #define MSR_MCG_CAP 0x179 |
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259 #define MSR_MCG_STATUS 0x17a |
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260 #define MSR_MCG_CTL 0x17b |
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261 |
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262 #define MSR_IA32_PERF_STATUS 0x198 |
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263 |
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264 #define MSR_PAT 0x277 |
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265 |
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266 #define MSR_EFER 0xc0000080 |
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267 |
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268 #define MSR_EFER_SCE (1 << 0) |
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269 #define MSR_EFER_LME (1 << 8) |
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270 #define MSR_EFER_LMA (1 << 10) |
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271 #define MSR_EFER_NXE (1 << 11) |
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272 #define MSR_EFER_SVME (1 << 12) |
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273 #define MSR_EFER_FFXSR (1 << 14) |
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274 |
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275 #define MSR_STAR 0xc0000081 |
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276 #define MSR_LSTAR 0xc0000082 |
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277 #define MSR_CSTAR 0xc0000083 |
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278 #define MSR_FMASK 0xc0000084 |
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279 #define MSR_FSBASE 0xc0000100 |
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280 #define MSR_GSBASE 0xc0000101 |
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281 #define MSR_KERNELGSBASE 0xc0000102 |
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282 |
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283 #define MSR_VM_HSAVE_PA 0xc0010117 |
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284 |
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285 /* cpuid_features bits */ |
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286 #define CPUID_FP87 (1 << 0) |
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287 #define CPUID_VME (1 << 1) |
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288 #define CPUID_DE (1 << 2) |
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289 #define CPUID_PSE (1 << 3) |
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290 #define CPUID_TSC (1 << 4) |
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291 #define CPUID_MSR (1 << 5) |
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292 #define CPUID_PAE (1 << 6) |
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293 #define CPUID_MCE (1 << 7) |
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294 #define CPUID_CX8 (1 << 8) |
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295 #define CPUID_APIC (1 << 9) |
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296 #define CPUID_SEP (1 << 11) /* sysenter/sysexit */ |
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297 #define CPUID_MTRR (1 << 12) |
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298 #define CPUID_PGE (1 << 13) |
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299 #define CPUID_MCA (1 << 14) |
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300 #define CPUID_CMOV (1 << 15) |
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301 #define CPUID_PAT (1 << 16) |
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302 #define CPUID_PSE36 (1 << 17) |
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303 #define CPUID_PN (1 << 18) |
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304 #define CPUID_CLFLUSH (1 << 19) |
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305 #define CPUID_DTS (1 << 21) |
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306 #define CPUID_ACPI (1 << 22) |
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307 #define CPUID_MMX (1 << 23) |
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308 #define CPUID_FXSR (1 << 24) |
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309 #define CPUID_SSE (1 << 25) |
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310 #define CPUID_SSE2 (1 << 26) |
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311 #define CPUID_SS (1 << 27) |
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312 #define CPUID_HT (1 << 28) |
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313 #define CPUID_TM (1 << 29) |
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314 #define CPUID_IA64 (1 << 30) |
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315 #define CPUID_PBE (1 << 31) |
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316 |
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317 #define CPUID_EXT_SSE3 (1 << 0) |
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318 #define CPUID_EXT_DTES64 (1 << 2) |
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319 #define CPUID_EXT_MONITOR (1 << 3) |
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320 #define CPUID_EXT_DSCPL (1 << 4) |
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321 #define CPUID_EXT_VMX (1 << 5) |
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322 #define CPUID_EXT_SMX (1 << 6) |
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323 #define CPUID_EXT_EST (1 << 7) |
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324 #define CPUID_EXT_TM2 (1 << 8) |
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325 #define CPUID_EXT_SSSE3 (1 << 9) |
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326 #define CPUID_EXT_CID (1 << 10) |
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327 #define CPUID_EXT_CX16 (1 << 13) |
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328 #define CPUID_EXT_XTPR (1 << 14) |
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329 #define CPUID_EXT_PDCM (1 << 15) |
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330 #define CPUID_EXT_DCA (1 << 18) |
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331 #define CPUID_EXT_SSE41 (1 << 19) |
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332 #define CPUID_EXT_SSE42 (1 << 20) |
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333 #define CPUID_EXT_X2APIC (1 << 21) |
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334 #define CPUID_EXT_MOVBE (1 << 22) |
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335 #define CPUID_EXT_POPCNT (1 << 23) |
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336 #define CPUID_EXT_XSAVE (1 << 26) |
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337 #define CPUID_EXT_OSXSAVE (1 << 27) |
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338 |
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339 #define CPUID_EXT2_SYSCALL (1 << 11) |
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340 #define CPUID_EXT2_MP (1 << 19) |
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341 #define CPUID_EXT2_NX (1 << 20) |
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342 #define CPUID_EXT2_MMXEXT (1 << 22) |
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343 #define CPUID_EXT2_FFXSR (1 << 25) |
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344 #define CPUID_EXT2_PDPE1GB (1 << 26) |
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345 #define CPUID_EXT2_RDTSCP (1 << 27) |
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346 #define CPUID_EXT2_LM (1 << 29) |
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347 #define CPUID_EXT2_3DNOWEXT (1 << 30) |
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348 #define CPUID_EXT2_3DNOW (1 << 31) |
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349 |
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350 #define CPUID_EXT3_LAHF_LM (1 << 0) |
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351 #define CPUID_EXT3_CMP_LEG (1 << 1) |
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352 #define CPUID_EXT3_SVM (1 << 2) |
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353 #define CPUID_EXT3_EXTAPIC (1 << 3) |
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354 #define CPUID_EXT3_CR8LEG (1 << 4) |
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355 #define CPUID_EXT3_ABM (1 << 5) |
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356 #define CPUID_EXT3_SSE4A (1 << 6) |
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357 #define CPUID_EXT3_MISALIGNSSE (1 << 7) |
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358 #define CPUID_EXT3_3DNOWPREFETCH (1 << 8) |
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359 #define CPUID_EXT3_OSVW (1 << 9) |
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360 #define CPUID_EXT3_IBS (1 << 10) |
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361 #define CPUID_EXT3_SKINIT (1 << 12) |
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362 |
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363 #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */ |
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364 #define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */ |
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365 #define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */ |
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366 |
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367 #define CPUID_VENDOR_AMD_1 0x68747541 /* "Auth" */ |
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368 #define CPUID_VENDOR_AMD_2 0x69746e65 /* "enti" */ |
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369 #define CPUID_VENDOR_AMD_3 0x444d4163 /* "cAMD" */ |
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370 |
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371 #define CPUID_MWAIT_IBE (1 << 1) /* Interrupts can exit capability */ |
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372 #define CPUID_MWAIT_EMX (1 << 0) /* enumeration supported */ |
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373 |
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374 #define EXCP00_DIVZ 0 |
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375 #define EXCP01_DB 1 |
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376 #define EXCP02_NMI 2 |
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377 #define EXCP03_INT3 3 |
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378 #define EXCP04_INTO 4 |
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379 #define EXCP05_BOUND 5 |
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380 #define EXCP06_ILLOP 6 |
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381 #define EXCP07_PREX 7 |
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382 #define EXCP08_DBLE 8 |
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383 #define EXCP09_XERR 9 |
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384 #define EXCP0A_TSS 10 |
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385 #define EXCP0B_NOSEG 11 |
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386 #define EXCP0C_STACK 12 |
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387 #define EXCP0D_GPF 13 |
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388 #define EXCP0E_PAGE 14 |
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389 #define EXCP10_COPR 16 |
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390 #define EXCP11_ALGN 17 |
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391 #define EXCP12_MCHK 18 |
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392 |
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393 #define EXCP_SYSCALL 0x100 /* only happens in user only emulation |
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394 for syscall instruction */ |
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395 |
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396 enum { |
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397 CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */ |
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398 CC_OP_EFLAGS, /* all cc are explicitly computed, CC_SRC = flags */ |
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399 |
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400 CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */ |
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401 CC_OP_MULW, |
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402 CC_OP_MULL, |
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403 CC_OP_MULQ, |
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404 |
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405 CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ |
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406 CC_OP_ADDW, |
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407 CC_OP_ADDL, |
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408 CC_OP_ADDQ, |
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409 |
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410 CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ |
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411 CC_OP_ADCW, |
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412 CC_OP_ADCL, |
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413 CC_OP_ADCQ, |
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414 |
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415 CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ |
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416 CC_OP_SUBW, |
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417 CC_OP_SUBL, |
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418 CC_OP_SUBQ, |
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419 |
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420 CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ |
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421 CC_OP_SBBW, |
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422 CC_OP_SBBL, |
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423 CC_OP_SBBQ, |
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424 |
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425 CC_OP_LOGICB, /* modify all flags, CC_DST = res */ |
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426 CC_OP_LOGICW, |
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427 CC_OP_LOGICL, |
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428 CC_OP_LOGICQ, |
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429 |
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430 CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */ |
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431 CC_OP_INCW, |
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432 CC_OP_INCL, |
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433 CC_OP_INCQ, |
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434 |
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435 CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */ |
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436 CC_OP_DECW, |
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437 CC_OP_DECL, |
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438 CC_OP_DECQ, |
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439 |
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440 CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */ |
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441 CC_OP_SHLW, |
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442 CC_OP_SHLL, |
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443 CC_OP_SHLQ, |
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444 |
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445 CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */ |
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446 CC_OP_SARW, |
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447 CC_OP_SARL, |
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448 CC_OP_SARQ, |
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449 |
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450 CC_OP_NB, |
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451 }; |
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452 |
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453 #ifdef FLOATX80 |
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454 #define USE_X86LDOUBLE |
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455 #endif |
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456 |
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457 #ifdef USE_X86LDOUBLE |
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458 typedef floatx80 CPU86_LDouble; |
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459 #else |
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460 typedef float64 CPU86_LDouble; |
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461 #endif |
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462 |
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463 typedef struct SegmentCache { |
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464 uint32_t selector; |
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465 target_ulong base; |
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466 uint32_t limit; |
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467 uint32_t flags; |
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468 } SegmentCache; |
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469 |
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470 typedef union { |
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471 uint8_t _b[16]; |
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472 uint16_t _w[8]; |
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473 uint32_t _l[4]; |
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474 uint64_t _q[2]; |
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475 float32 _s[4]; |
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476 float64 _d[2]; |
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477 } XMMReg; |
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478 |
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479 typedef union { |
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480 uint8_t _b[8]; |
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481 uint16_t _w[4]; |
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482 uint32_t _l[2]; |
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483 float32 _s[2]; |
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484 uint64_t q; |
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485 } MMXReg; |
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486 |
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487 #ifdef WORDS_BIGENDIAN |
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488 #define XMM_B(n) _b[15 - (n)] |
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489 #define XMM_W(n) _w[7 - (n)] |
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490 #define XMM_L(n) _l[3 - (n)] |
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491 #define XMM_S(n) _s[3 - (n)] |
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492 #define XMM_Q(n) _q[1 - (n)] |
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493 #define XMM_D(n) _d[1 - (n)] |
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494 |
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495 #define MMX_B(n) _b[7 - (n)] |
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496 #define MMX_W(n) _w[3 - (n)] |
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497 #define MMX_L(n) _l[1 - (n)] |
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498 #define MMX_S(n) _s[1 - (n)] |
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499 #else |
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500 #define XMM_B(n) _b[n] |
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501 #define XMM_W(n) _w[n] |
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502 #define XMM_L(n) _l[n] |
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503 #define XMM_S(n) _s[n] |
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504 #define XMM_Q(n) _q[n] |
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505 #define XMM_D(n) _d[n] |
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506 |
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507 #define MMX_B(n) _b[n] |
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508 #define MMX_W(n) _w[n] |
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509 #define MMX_L(n) _l[n] |
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510 #define MMX_S(n) _s[n] |
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511 #endif |
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512 #define MMX_Q(n) q |
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513 |
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514 #ifdef TARGET_X86_64 |
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515 #define CPU_NB_REGS 16 |
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516 #else |
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517 #define CPU_NB_REGS 8 |
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518 #endif |
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519 |
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520 #define NB_MMU_MODES 2 |
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521 |
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522 typedef struct CPUX86State { |
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523 /* standard registers */ |
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524 target_ulong regs[CPU_NB_REGS]; |
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525 target_ulong eip; |
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526 target_ulong eflags; /* eflags register. During CPU emulation, CC |
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527 flags and DF are set to zero because they are |
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528 stored elsewhere */ |
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529 |
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530 /* emulator internal eflags handling */ |
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531 target_ulong cc_src; |
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532 target_ulong cc_dst; |
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533 uint32_t cc_op; |
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534 int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */ |
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535 uint32_t hflags; /* TB flags, see HF_xxx constants. These flags |
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536 are known at translation time. */ |
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537 uint32_t hflags2; /* various other flags, see HF2_xxx constants. */ |
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538 |
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539 /* segments */ |
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540 SegmentCache segs[6]; /* selector values */ |
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541 SegmentCache ldt; |
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542 SegmentCache tr; |
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543 SegmentCache gdt; /* only base and limit are used */ |
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544 SegmentCache idt; /* only base and limit are used */ |
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545 |
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546 target_ulong cr[5]; /* NOTE: cr1 is unused */ |
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547 uint64_t a20_mask; |
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548 |
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549 /* FPU state */ |
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550 unsigned int fpstt; /* top of stack index */ |
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551 unsigned int fpus; |
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552 unsigned int fpuc; |
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553 uint8_t fptags[8]; /* 0 = valid, 1 = empty */ |
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554 union { |
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555 #ifdef USE_X86LDOUBLE |
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556 CPU86_LDouble d __attribute__((aligned(16))); |
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557 #else |
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558 CPU86_LDouble d; |
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559 #endif |
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560 MMXReg mmx; |
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561 } fpregs[8]; |
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562 |
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563 /* emulator internal variables */ |
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564 float_status fp_status; |
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565 CPU86_LDouble ft0; |
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566 |
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567 float_status mmx_status; /* for 3DNow! float ops */ |
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568 float_status sse_status; |
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569 uint32_t mxcsr; |
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570 XMMReg xmm_regs[CPU_NB_REGS]; |
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571 XMMReg xmm_t0; |
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572 MMXReg mmx_t0; |
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573 target_ulong cc_tmp; /* temporary for rcr/rcl */ |
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574 |
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575 /* sysenter registers */ |
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576 uint32_t sysenter_cs; |
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577 target_ulong sysenter_esp; |
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578 target_ulong sysenter_eip; |
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579 uint64_t efer; |
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580 uint64_t star; |
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581 |
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582 uint64_t vm_hsave; |
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583 uint64_t vm_vmcb; |
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584 uint64_t tsc_offset; |
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585 uint64_t intercept; |
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586 uint16_t intercept_cr_read; |
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587 uint16_t intercept_cr_write; |
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588 uint16_t intercept_dr_read; |
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589 uint16_t intercept_dr_write; |
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590 uint32_t intercept_exceptions; |
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591 uint8_t v_tpr; |
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592 |
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593 #ifdef TARGET_X86_64 |
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594 target_ulong lstar; |
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595 target_ulong cstar; |
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596 target_ulong fmask; |
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597 target_ulong kernelgsbase; |
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598 #endif |
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599 |
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600 uint64_t tsc; |
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601 |
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602 uint64_t pat; |
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603 |
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604 /* exception/interrupt handling */ |
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605 int error_code; |
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606 int exception_is_int; |
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607 target_ulong exception_next_eip; |
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608 target_ulong dr[8]; /* debug registers */ |
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609 union { |
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610 CPUBreakpoint *cpu_breakpoint[4]; |
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611 CPUWatchpoint *cpu_watchpoint[4]; |
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612 }; /* break/watchpoints for dr[0..3] */ |
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613 uint32_t smbase; |
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614 int old_exception; /* exception in flight */ |
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615 |
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616 CPU_COMMON |
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617 |
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618 /* processor features (e.g. for CPUID insn) */ |
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619 uint32_t cpuid_level; |
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620 uint32_t cpuid_vendor1; |
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621 uint32_t cpuid_vendor2; |
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622 uint32_t cpuid_vendor3; |
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623 uint32_t cpuid_version; |
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624 uint32_t cpuid_features; |
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625 uint32_t cpuid_ext_features; |
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626 uint32_t cpuid_xlevel; |
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627 uint32_t cpuid_model[12]; |
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628 uint32_t cpuid_ext2_features; |
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629 uint32_t cpuid_ext3_features; |
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630 uint32_t cpuid_apic_id; |
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631 |
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632 #ifdef USE_KQEMU |
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633 int kqemu_enabled; |
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634 int last_io_time; |
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635 #endif |
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636 |
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637 /* For KVM */ |
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638 uint64_t interrupt_bitmap[256 / 64]; |
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639 |
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640 /* in order to simplify APIC support, we leave this pointer to the |
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641 user */ |
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642 struct APICState *apic_state; |
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643 } CPUX86State; |
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644 |
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645 CPUX86State *cpu_x86_init(const char *cpu_model); |
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646 int cpu_x86_exec(CPUX86State *s); |
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647 void cpu_x86_close(CPUX86State *s); |
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648 void x86_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, |
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649 ...)); |
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650 int cpu_get_pic_interrupt(CPUX86State *s); |
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651 /* MSDOS compatibility mode FPU exception support */ |
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652 void cpu_set_ferr(CPUX86State *s); |
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653 |
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654 /* this function must always be used to load data in the segment |
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655 cache: it synchronizes the hflags with the segment cache values */ |
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656 static inline void cpu_x86_load_seg_cache(CPUX86State *env, |
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657 int seg_reg, unsigned int selector, |
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658 target_ulong base, |
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659 unsigned int limit, |
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660 unsigned int flags) |
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661 { |
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662 SegmentCache *sc; |
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663 unsigned int new_hflags; |
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664 |
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665 sc = &env->segs[seg_reg]; |
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666 sc->selector = selector; |
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667 sc->base = base; |
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668 sc->limit = limit; |
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669 sc->flags = flags; |
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670 |
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671 /* update the hidden flags */ |
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672 { |
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673 if (seg_reg == R_CS) { |
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674 #ifdef TARGET_X86_64 |
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675 if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) { |
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676 /* long mode */ |
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677 env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; |
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678 env->hflags &= ~(HF_ADDSEG_MASK); |
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679 } else |
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680 #endif |
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681 { |
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682 /* legacy / compatibility case */ |
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683 new_hflags = (env->segs[R_CS].flags & DESC_B_MASK) |
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684 >> (DESC_B_SHIFT - HF_CS32_SHIFT); |
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685 env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) | |
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686 new_hflags; |
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687 } |
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688 } |
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689 new_hflags = (env->segs[R_SS].flags & DESC_B_MASK) |
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690 >> (DESC_B_SHIFT - HF_SS32_SHIFT); |
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691 if (env->hflags & HF_CS64_MASK) { |
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692 /* zero base assumed for DS, ES and SS in long mode */ |
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693 } else if (!(env->cr[0] & CR0_PE_MASK) || |
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694 (env->eflags & VM_MASK) || |
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695 !(env->hflags & HF_CS32_MASK)) { |
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696 /* XXX: try to avoid this test. The problem comes from the |
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697 fact that is real mode or vm86 mode we only modify the |
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698 'base' and 'selector' fields of the segment cache to go |
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699 faster. A solution may be to force addseg to one in |
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700 translate-i386.c. */ |
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701 new_hflags |= HF_ADDSEG_MASK; |
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702 } else { |
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703 new_hflags |= ((env->segs[R_DS].base | |
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704 env->segs[R_ES].base | |
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705 env->segs[R_SS].base) != 0) << |
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706 HF_ADDSEG_SHIFT; |
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707 } |
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708 env->hflags = (env->hflags & |
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709 ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags; |
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710 } |
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711 } |
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712 |
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713 /* wrapper, just in case memory mappings must be changed */ |
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714 static inline void cpu_x86_set_cpl(CPUX86State *s, int cpl) |
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715 { |
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716 #if HF_CPL_MASK == 3 |
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717 s->hflags = (s->hflags & ~HF_CPL_MASK) | cpl; |
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718 #else |
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719 #error HF_CPL_MASK is hardcoded |
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720 #endif |
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721 } |
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722 |
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723 /* op_helper.c */ |
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724 /* used for debug or cpu save/restore */ |
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725 void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, CPU86_LDouble f); |
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726 CPU86_LDouble cpu_set_fp80(uint64_t mant, uint16_t upper); |
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727 |
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728 /* cpu-exec.c */ |
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729 /* the following helpers are only usable in user mode simulation as |
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730 they can trigger unexpected exceptions */ |
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731 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector); |
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732 void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32); |
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733 void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32); |
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734 |
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735 /* you can call this signal handler from your SIGBUS and SIGSEGV |
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736 signal handlers to inform the virtual CPU of exceptions. non zero |
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737 is returned if the signal was handled by the virtual CPU. */ |
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738 int cpu_x86_signal_handler(int host_signum, void *pinfo, |
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739 void *puc); |
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740 |
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741 /* helper.c */ |
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742 int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr, |
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743 int is_write, int mmu_idx, int is_softmmu); |
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744 void cpu_x86_set_a20(CPUX86State *env, int a20_state); |
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745 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, |
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746 uint32_t *eax, uint32_t *ebx, |
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747 uint32_t *ecx, uint32_t *edx); |
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748 |
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749 static inline int hw_breakpoint_enabled(unsigned long dr7, int index) |
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750 { |
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751 return (dr7 >> (index * 2)) & 3; |
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752 } |
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753 |
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754 static inline int hw_breakpoint_type(unsigned long dr7, int index) |
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755 { |
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756 return (dr7 >> (DR7_TYPE_SHIFT + (index * 2))) & 3; |
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757 } |
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758 |
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759 static inline int hw_breakpoint_len(unsigned long dr7, int index) |
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760 { |
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761 int len = ((dr7 >> (DR7_LEN_SHIFT + (index * 2))) & 3); |
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762 return (len == 2) ? 8 : len + 1; |
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763 } |
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764 |
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765 void hw_breakpoint_insert(CPUX86State *env, int index); |
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766 void hw_breakpoint_remove(CPUX86State *env, int index); |
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767 int check_hw_breakpoints(CPUX86State *env, int force_dr6_update); |
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768 |
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769 /* will be suppressed */ |
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770 void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0); |
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771 void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3); |
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772 void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4); |
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773 |
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774 /* hw/apic.c */ |
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775 void cpu_set_apic_base(CPUX86State *env, uint64_t val); |
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776 uint64_t cpu_get_apic_base(CPUX86State *env); |
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777 void cpu_set_apic_tpr(CPUX86State *env, uint8_t val); |
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778 #ifndef NO_CPU_IO_DEFS |
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779 uint8_t cpu_get_apic_tpr(CPUX86State *env); |
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780 #endif |
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781 |
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782 /* hw/pc.c */ |
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783 void cpu_smm_update(CPUX86State *env); |
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784 uint64_t cpu_get_tsc(CPUX86State *env); |
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785 |
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786 /* used to debug */ |
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787 #define X86_DUMP_FPU 0x0001 /* dump FPU state too */ |
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788 #define X86_DUMP_CCOP 0x0002 /* dump qemu flag cache */ |
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789 |
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790 #ifdef USE_KQEMU |
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791 static inline int cpu_get_time_fast(void) |
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792 { |
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793 int low, high; |
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794 asm volatile("rdtsc" : "=a" (low), "=d" (high)); |
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795 return low; |
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796 } |
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797 #endif |
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798 |
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799 #define TARGET_PAGE_BITS 12 |
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800 |
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801 #define CPUState CPUX86State |
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802 #define cpu_init cpu_x86_init |
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803 #define cpu_exec cpu_x86_exec |
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804 #define cpu_gen_code cpu_x86_gen_code |
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805 #define cpu_signal_handler cpu_x86_signal_handler |
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806 #define cpu_list x86_cpu_list |
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807 |
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808 #define CPU_SAVE_VERSION 7 |
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809 |
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810 /* MMU modes definitions */ |
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811 #define MMU_MODE0_SUFFIX _kernel |
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812 #define MMU_MODE1_SUFFIX _user |
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813 #define MMU_USER_IDX 1 |
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814 static inline int cpu_mmu_index (CPUState *env) |
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815 { |
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816 return (env->hflags & HF_CPL_MASK) == 3 ? 1 : 0; |
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817 } |
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818 |
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819 /* translate.c */ |
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820 void optimize_flags_init(void); |
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821 |
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822 typedef struct CCTable { |
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823 int (*compute_all)(void); /* return all the flags */ |
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824 int (*compute_c)(void); /* return the C flag */ |
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825 } CCTable; |
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826 |
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827 #if defined(CONFIG_USER_ONLY) |
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828 static inline void cpu_clone_regs(CPUState *env, target_ulong newsp) |
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829 { |
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830 if (newsp) |
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831 env->regs[R_ESP] = newsp; |
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832 env->regs[R_EAX] = 0; |
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833 } |
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834 #endif |
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835 |
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836 #include "cpu-all.h" |
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837 #include "exec-all.h" |
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838 |
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839 #include "svm.h" |
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840 |
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841 static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb) |
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842 { |
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843 env->eip = tb->pc - tb->cs_base; |
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844 } |
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845 |
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846 static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, |
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847 target_ulong *cs_base, int *flags) |
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848 { |
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849 *cs_base = env->segs[R_CS].base; |
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850 *pc = *cs_base + env->eip; |
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851 *flags = env->hflags | (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK)); |
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852 } |
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853 |
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854 #endif /* CPU_I386_H */ |