1 /*

     2  *  m68k translation

     3  *

     4  *  Copyright (c) 2005-2007 CodeSourcery

     5  *  Written by Paul Brook

     6  *

     7  * This library is free software; you can redistribute it and/or

     8  * modify it under the terms of the GNU Lesser General Public

     9  * License as published by the Free Software Foundation; either

    10  * version 2 of the License, or (at your option) any later version.

    11  *

    12  * This library is distributed in the hope that it will be useful,

    13  * but WITHOUT ANY WARRANTY; without even the implied warranty of

    14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

    15  * General Public License for more details.

    16  *

    17  * You should have received a copy of the GNU Lesser General Public

    18  * License along with this library; if not, write to the Free Software

    19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA

    20  */

    21 #include <stdarg.h>

    22 #include <stdlib.h>

    23 #include <stdio.h>

    24 #include <string.h>

    25 #include <inttypes.h>

    26 #include <assert.h>

    27 

    28 #include "config.h"

    29 #include "cpu.h"

    30 #include "exec-all.h"

    31 #include "disas.h"

    32 #include "tcg-op.h"

    33 #include "qemu-log.h"

    34 

    35 #include "helpers.h"

    36 #define GEN_HELPER 1

    37 #include "helpers.h"

    38 

    39 //#define DEBUG_DISPATCH 1

    40 

    41 /* Fake floating point.  */

    42 #define tcg_gen_mov_f64 tcg_gen_mov_i64

    43 #define tcg_gen_qemu_ldf64 tcg_gen_qemu_ld64

    44 #define tcg_gen_qemu_stf64 tcg_gen_qemu_st64

    45 

    46 #define DEFO32(name, offset) static TCGv QREG_##name;

    47 #define DEFO64(name, offset) static TCGv_i64 QREG_##name;

    48 #define DEFF64(name, offset) static TCGv_i64 QREG_##name;

    49 #include "qregs.def"

    50 #undef DEFO32

    51 #undef DEFO64

    52 #undef DEFF64

    53 

    54 static TCGv_ptr cpu_env;

    55 

    56 static char cpu_reg_names[3*8*3 + 5*4];

    57 static TCGv cpu_dregs[8];

    58 static TCGv cpu_aregs[8];

    59 static TCGv_i64 cpu_fregs[8];

    60 static TCGv_i64 cpu_macc[4];

    61 

    62 #define DREG(insn, pos) cpu_dregs[((insn) >> (pos)) & 7]

    63 #define AREG(insn, pos) cpu_aregs[((insn) >> (pos)) & 7]

    64 #define FREG(insn, pos) cpu_fregs[((insn) >> (pos)) & 7]

    65 #define MACREG(acc) cpu_macc[acc]

    66 #define QREG_SP cpu_aregs[7]

    67 

    68 static TCGv NULL_QREG;

    69 #define IS_NULL_QREG(t) (TCGV_EQUAL(t, NULL_QREG))

    70 /* Used to distinguish stores from bad addressing modes.  */

    71 static TCGv store_dummy;

    72 

    73 #include "gen-icount.h"

    74 

    75 void m68k_tcg_init(void)

    76 {

    77     char *p;

    78     int i;

    79 

    80 #define DEFO32(name,  offset) QREG_##name = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUState, offset), #name);

    81 #define DEFO64(name,  offset) QREG_##name = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUState, offset), #name);

    82 #define DEFF64(name,  offset) DEFO64(name, offset)

    83 #include "qregs.def"

    84 #undef DEFO32

    85 #undef DEFO64

    86 #undef DEFF64

    87 

    88     cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");

    89 

    90     p = cpu_reg_names;

    91     for (i = 0; i < 8; i++) {

    92         sprintf(p, "D%d", i);

    93         cpu_dregs[i] = tcg_global_mem_new(TCG_AREG0,

    94                                           offsetof(CPUM68KState, dregs[i]), p);

    95         p += 3;

    96         sprintf(p, "A%d", i);

    97         cpu_aregs[i] = tcg_global_mem_new(TCG_AREG0,

    98                                           offsetof(CPUM68KState, aregs[i]), p);

    99         p += 3;

   100         sprintf(p, "F%d", i);

   101         cpu_fregs[i] = tcg_global_mem_new_i64(TCG_AREG0,

   102                                           offsetof(CPUM68KState, fregs[i]), p);

   103         p += 3;

   104     }

   105     for (i = 0; i < 4; i++) {

   106         sprintf(p, "ACC%d", i);

   107         cpu_macc[i] = tcg_global_mem_new_i64(TCG_AREG0,

   108                                          offsetof(CPUM68KState, macc[i]), p);

   109         p += 5;

   110     }

   111 

   112     NULL_QREG = tcg_global_mem_new(TCG_AREG0, -4, "NULL");

   113     store_dummy = tcg_global_mem_new(TCG_AREG0, -8, "NULL");

   114 

   115 #define GEN_HELPER 2

   116 #include "helpers.h"

   117 }

   118 

   119 static inline void qemu_assert(int cond, const char *msg)

   120 {

   121     if (!cond) {

   122         fprintf (stderr, "badness: %s\n", msg);

   123         abort();

   124     }

   125 }

   126 

   127 /* internal defines */

   128 typedef struct DisasContext {

   129     CPUM68KState *env;

   130     target_ulong insn_pc; /* Start of the current instruction.  */

   131     target_ulong pc;

   132     int is_jmp;

   133     int cc_op;

   134     int user;

   135     uint32_t fpcr;

   136     struct TranslationBlock *tb;

   137     int singlestep_enabled;

   138     int is_mem;

   139     TCGv_i64 mactmp;

   140     int done_mac;

   141 } DisasContext;

   142 

   143 #define DISAS_JUMP_NEXT 4

   144 

   145 #if defined(CONFIG_USER_ONLY)

   146 #define IS_USER(s) 1

   147 #else

   148 #define IS_USER(s) s->user

   149 #endif

   150 

   151 /* XXX: move that elsewhere */

   152 /* ??? Fix exceptions.  */

   153 static void *gen_throws_exception;

   154 #define gen_last_qop NULL

   155 

   156 #define OS_BYTE 0

   157 #define OS_WORD 1

   158 #define OS_LONG 2

   159 #define OS_SINGLE 4

   160 #define OS_DOUBLE 5

   161 

   162 typedef void (*disas_proc)(DisasContext *, uint16_t);

   163 

   164 #ifdef DEBUG_DISPATCH

   165 #define DISAS_INSN(name) \

   166   static void real_disas_##name (DisasContext *s, uint16_t insn); \

   167   static void disas_##name (DisasContext *s, uint16_t insn) { \

   168     if (logfile) fprintf(logfile, "Dispatch " #name "\n"); \

   169     real_disas_##name(s, insn); } \

   170   static void real_disas_##name (DisasContext *s, uint16_t insn)

   171 #else

   172 #define DISAS_INSN(name) \

   173   static void disas_##name (DisasContext *s, uint16_t insn)

   174 #endif

   175 

   176 /* FIXME: Remove this.  */

   177 #define gen_im32(val) tcg_const_i32(val)

   178 

   179 /* Generate a load from the specified address.  Narrow values are

   180    sign extended to full register width.  */

   181 static inline TCGv gen_load(DisasContext * s, int opsize, TCGv addr, int sign)

   182 {

   183     TCGv tmp;

   184     int index = IS_USER(s);

   185     s->is_mem = 1;

   186     tmp = tcg_temp_new_i32();

   187     switch(opsize) {

   188     case OS_BYTE:

   189         if (sign)

   190             tcg_gen_qemu_ld8s(tmp, addr, index);

   191         else

   192             tcg_gen_qemu_ld8u(tmp, addr, index);

   193         break;

   194     case OS_WORD:

   195         if (sign)

   196             tcg_gen_qemu_ld16s(tmp, addr, index);

   197         else

   198             tcg_gen_qemu_ld16u(tmp, addr, index);

   199         break;

   200     case OS_LONG:

   201     case OS_SINGLE:

   202         tcg_gen_qemu_ld32u(tmp, addr, index);

   203         break;

   204     default:

   205         qemu_assert(0, "bad load size");

   206     }

   207     gen_throws_exception = gen_last_qop;

   208     return tmp;

   209 }

   210 

   211 static inline TCGv_i64 gen_load64(DisasContext * s, TCGv addr)

   212 {

   213     TCGv_i64 tmp;

   214     int index = IS_USER(s);

   215     s->is_mem = 1;

   216     tmp = tcg_temp_new_i64();

   217     tcg_gen_qemu_ldf64(tmp, addr, index);

   218     gen_throws_exception = gen_last_qop;

   219     return tmp;

   220 }

   221 

   222 /* Generate a store.  */

   223 static inline void gen_store(DisasContext *s, int opsize, TCGv addr, TCGv val)

   224 {

   225     int index = IS_USER(s);

   226     s->is_mem = 1;

   227     switch(opsize) {

   228     case OS_BYTE:

   229         tcg_gen_qemu_st8(val, addr, index);

   230         break;

   231     case OS_WORD:

   232         tcg_gen_qemu_st16(val, addr, index);

   233         break;

   234     case OS_LONG:

   235     case OS_SINGLE:

   236         tcg_gen_qemu_st32(val, addr, index);

   237         break;

   238     default:

   239         qemu_assert(0, "bad store size");

   240     }

   241     gen_throws_exception = gen_last_qop;

   242 }

   243 

   244 static inline void gen_store64(DisasContext *s, TCGv addr, TCGv_i64 val)

   245 {

   246     int index = IS_USER(s);

   247     s->is_mem = 1;

   248     tcg_gen_qemu_stf64(val, addr, index);

   249     gen_throws_exception = gen_last_qop;

   250 }

   251 

   252 typedef enum {

   253     EA_STORE,

   254     EA_LOADU,

   255     EA_LOADS

   256 } ea_what;

   257 

   258 /* Generate an unsigned load if VAL is 0 a signed load if val is -1,

   259    otherwise generate a store.  */

   260 static TCGv gen_ldst(DisasContext *s, int opsize, TCGv addr, TCGv val,

   261                      ea_what what)

   262 {

   263     if (what == EA_STORE) {

   264         gen_store(s, opsize, addr, val);

   265         return store_dummy;

   266     } else {

   267         return gen_load(s, opsize, addr, what == EA_LOADS);

   268     }

   269 }

   270 

   271 /* Read a 32-bit immediate constant.  */

   272 static inline uint32_t read_im32(DisasContext *s)

   273 {

   274     uint32_t im;

   275     im = ((uint32_t)lduw_code(s->pc)) << 16;

   276     s->pc += 2;

   277     im |= lduw_code(s->pc);

   278     s->pc += 2;

   279     return im;

   280 }

   281 

   282 /* Calculate and address index.  */

   283 static TCGv gen_addr_index(uint16_t ext, TCGv tmp)

   284 {

   285     TCGv add;

   286     int scale;

   287 

   288     add = (ext & 0x8000) ? AREG(ext, 12) : DREG(ext, 12);

   289     if ((ext & 0x800) == 0) {

   290         tcg_gen_ext16s_i32(tmp, add);

   291         add = tmp;

   292     }

   293     scale = (ext >> 9) & 3;

   294     if (scale != 0) {

   295         tcg_gen_shli_i32(tmp, add, scale);

   296         add = tmp;

   297     }

   298     return add;

   299 }

   300 

   301 /* Handle a base + index + displacement effective addresss.

   302    A NULL_QREG base means pc-relative.  */

   303 static TCGv gen_lea_indexed(DisasContext *s, int opsize, TCGv base)

   304 {

   305     uint32_t offset;

   306     uint16_t ext;

   307     TCGv add;

   308     TCGv tmp;

   309     uint32_t bd, od;

   310 

   311     offset = s->pc;

   312     ext = lduw_code(s->pc);

   313     s->pc += 2;

   314 

   315     if ((ext & 0x800) == 0 && !m68k_feature(s->env, M68K_FEATURE_WORD_INDEX))

   316         return NULL_QREG;

   317 

   318     if (ext & 0x100) {

   319         /* full extension word format */

   320         if (!m68k_feature(s->env, M68K_FEATURE_EXT_FULL))

   321             return NULL_QREG;

   322 

   323         if ((ext & 0x30) > 0x10) {

   324             /* base displacement */

   325             if ((ext & 0x30) == 0x20) {

   326                 bd = (int16_t)lduw_code(s->pc);

   327                 s->pc += 2;

   328             } else {

   329                 bd = read_im32(s);

   330             }

   331         } else {

   332             bd = 0;

   333         }

   334         tmp = tcg_temp_new();

   335         if ((ext & 0x44) == 0) {

   336             /* pre-index */

   337             add = gen_addr_index(ext, tmp);

   338         } else {

   339             add = NULL_QREG;

   340         }

   341         if ((ext & 0x80) == 0) {

   342             /* base not suppressed */

   343             if (IS_NULL_QREG(base)) {

   344                 base = gen_im32(offset + bd);

   345                 bd = 0;

   346             }

   347             if (!IS_NULL_QREG(add)) {

   348                 tcg_gen_add_i32(tmp, add, base);

   349                 add = tmp;

   350             } else {

   351                 add = base;

   352             }

   353         }

   354         if (!IS_NULL_QREG(add)) {

   355             if (bd != 0) {

   356                 tcg_gen_addi_i32(tmp, add, bd);

   357                 add = tmp;

   358             }

   359         } else {

   360             add = gen_im32(bd);

   361         }

   362         if ((ext & 3) != 0) {

   363             /* memory indirect */

   364             base = gen_load(s, OS_LONG, add, 0);

   365             if ((ext & 0x44) == 4) {

   366                 add = gen_addr_index(ext, tmp);

   367                 tcg_gen_add_i32(tmp, add, base);

   368                 add = tmp;

   369             } else {

   370                 add = base;

   371             }

   372             if ((ext & 3) > 1) {

   373                 /* outer displacement */

   374                 if ((ext & 3) == 2) {

   375                     od = (int16_t)lduw_code(s->pc);

   376                     s->pc += 2;

   377                 } else {

   378                     od = read_im32(s);

   379                 }

   380             } else {

   381                 od = 0;

   382             }

   383             if (od != 0) {

   384                 tcg_gen_addi_i32(tmp, add, od);

   385                 add = tmp;

   386             }

   387         }

   388     } else {

   389         /* brief extension word format */

   390         tmp = tcg_temp_new();

   391         add = gen_addr_index(ext, tmp);

   392         if (!IS_NULL_QREG(base)) {

   393             tcg_gen_add_i32(tmp, add, base);

   394             if ((int8_t)ext)

   395                 tcg_gen_addi_i32(tmp, tmp, (int8_t)ext);

   396         } else {

   397             tcg_gen_addi_i32(tmp, add, offset + (int8_t)ext);

   398         }

   399         add = tmp;

   400     }

   401     return add;

   402 }

   403 

   404 /* Update the CPU env CC_OP state.  */

   405 static inline void gen_flush_cc_op(DisasContext *s)

   406 {

   407     if (s->cc_op != CC_OP_DYNAMIC)

   408         tcg_gen_movi_i32(QREG_CC_OP, s->cc_op);

   409 }

   410 

   411 /* Evaluate all the CC flags.  */

   412 static inline void gen_flush_flags(DisasContext *s)

   413 {

   414     if (s->cc_op == CC_OP_FLAGS)

   415         return;

   416     gen_flush_cc_op(s);

   417     gen_helper_flush_flags(cpu_env, QREG_CC_OP);

   418     s->cc_op = CC_OP_FLAGS;

   419 }

   420 

   421 static void gen_logic_cc(DisasContext *s, TCGv val)

   422 {

   423     tcg_gen_mov_i32(QREG_CC_DEST, val);

   424     s->cc_op = CC_OP_LOGIC;

   425 }

   426 

   427 static void gen_update_cc_add(TCGv dest, TCGv src)

   428 {

   429     tcg_gen_mov_i32(QREG_CC_DEST, dest);

   430     tcg_gen_mov_i32(QREG_CC_SRC, src);

   431 }

   432 

   433 static inline int opsize_bytes(int opsize)

   434 {

   435     switch (opsize) {

   436     case OS_BYTE: return 1;

   437     case OS_WORD: return 2;

   438     case OS_LONG: return 4;

   439     case OS_SINGLE: return 4;

   440     case OS_DOUBLE: return 8;

   441     default:

   442         qemu_assert(0, "bad operand size");

   443         return 0;

   444     }

   445 }

   446 

   447 /* Assign value to a register.  If the width is less than the register width

   448    only the low part of the register is set.  */

   449 static void gen_partset_reg(int opsize, TCGv reg, TCGv val)

   450 {

   451     TCGv tmp;

   452     switch (opsize) {

   453     case OS_BYTE:

   454         tcg_gen_andi_i32(reg, reg, 0xffffff00);

   455         tmp = tcg_temp_new();

   456         tcg_gen_ext8u_i32(tmp, val);

   457         tcg_gen_or_i32(reg, reg, tmp);

   458         break;

   459     case OS_WORD:

   460         tcg_gen_andi_i32(reg, reg, 0xffff0000);

   461         tmp = tcg_temp_new();

   462         tcg_gen_ext16u_i32(tmp, val);

   463         tcg_gen_or_i32(reg, reg, tmp);

   464         break;

   465     case OS_LONG:

   466     case OS_SINGLE:

   467         tcg_gen_mov_i32(reg, val);

   468         break;

   469     default:

   470         qemu_assert(0, "Bad operand size");

   471         break;

   472     }

   473 }

   474 

   475 /* Sign or zero extend a value.  */

   476 static inline TCGv gen_extend(TCGv val, int opsize, int sign)

   477 {

   478     TCGv tmp;

   479 

   480     switch (opsize) {

   481     case OS_BYTE:

   482         tmp = tcg_temp_new();

   483         if (sign)

   484             tcg_gen_ext8s_i32(tmp, val);

   485         else

   486             tcg_gen_ext8u_i32(tmp, val);

   487         break;

   488     case OS_WORD:

   489         tmp = tcg_temp_new();

   490         if (sign)

   491             tcg_gen_ext16s_i32(tmp, val);

   492         else

   493             tcg_gen_ext16u_i32(tmp, val);

   494         break;

   495     case OS_LONG:

   496     case OS_SINGLE:

   497         tmp = val;

   498         break;

   499     default:

   500         qemu_assert(0, "Bad operand size");

   501     }

   502     return tmp;

   503 }

   504 

   505 /* Generate code for an "effective address".  Does not adjust the base

   506    register for autoincrement addressing modes.  */

   507 static TCGv gen_lea(DisasContext *s, uint16_t insn, int opsize)

   508 {

   509     TCGv reg;

   510     TCGv tmp;

   511     uint16_t ext;

   512     uint32_t offset;

   513 

   514     switch ((insn >> 3) & 7) {

   515     case 0: /* Data register direct.  */

   516     case 1: /* Address register direct.  */

   517         return NULL_QREG;

   518     case 2: /* Indirect register */

   519     case 3: /* Indirect postincrement.  */

   520         return AREG(insn, 0);

   521     case 4: /* Indirect predecrememnt.  */

   522         reg = AREG(insn, 0);

   523         tmp = tcg_temp_new();

   524         tcg_gen_subi_i32(tmp, reg, opsize_bytes(opsize));

   525         return tmp;

   526     case 5: /* Indirect displacement.  */

   527         reg = AREG(insn, 0);

   528         tmp = tcg_temp_new();

   529         ext = lduw_code(s->pc);

   530         s->pc += 2;

   531         tcg_gen_addi_i32(tmp, reg, (int16_t)ext);

   532         return tmp;

   533     case 6: /* Indirect index + displacement.  */

   534         reg = AREG(insn, 0);

   535         return gen_lea_indexed(s, opsize, reg);

   536     case 7: /* Other */

   537         switch (insn & 7) {

   538         case 0: /* Absolute short.  */

   539             offset = ldsw_code(s->pc);

   540             s->pc += 2;

   541             return gen_im32(offset);

   542         case 1: /* Absolute long.  */

   543             offset = read_im32(s);

   544             return gen_im32(offset);

   545         case 2: /* pc displacement  */

   546             tmp = tcg_temp_new();

   547             offset = s->pc;

   548             offset += ldsw_code(s->pc);

   549             s->pc += 2;

   550             return gen_im32(offset);

   551         case 3: /* pc index+displacement.  */

   552             return gen_lea_indexed(s, opsize, NULL_QREG);

   553         case 4: /* Immediate.  */

   554         default:

   555             return NULL_QREG;

   556         }

   557     }

   558     /* Should never happen.  */

   559     return NULL_QREG;

   560 }

   561 

   562 /* Helper function for gen_ea. Reuse the computed address between the

   563    for read/write operands.  */

   564 static inline TCGv gen_ea_once(DisasContext *s, uint16_t insn, int opsize,

   565                               TCGv val, TCGv *addrp, ea_what what)

   566 {

   567     TCGv tmp;

   568 

   569     if (addrp && what == EA_STORE) {

   570         tmp = *addrp;

   571     } else {

   572         tmp = gen_lea(s, insn, opsize);

   573         if (IS_NULL_QREG(tmp))

   574             return tmp;

   575         if (addrp)

   576             *addrp = tmp;

   577     }

   578     return gen_ldst(s, opsize, tmp, val, what);

   579 }

   580 

   581 /* Generate code to load/store a value ito/from an EA.  If VAL > 0 this is

   582    a write otherwise it is a read (0 == sign extend, -1 == zero extend).

   583    ADDRP is non-null for readwrite operands.  */

   584 static TCGv gen_ea(DisasContext *s, uint16_t insn, int opsize, TCGv val,

   585                    TCGv *addrp, ea_what what)

   586 {

   587     TCGv reg;

   588     TCGv result;

   589     uint32_t offset;

   590 

   591     switch ((insn >> 3) & 7) {

   592     case 0: /* Data register direct.  */

   593         reg = DREG(insn, 0);

   594         if (what == EA_STORE) {

   595             gen_partset_reg(opsize, reg, val);

   596             return store_dummy;

   597         } else {

   598             return gen_extend(reg, opsize, what == EA_LOADS);

   599         }

   600     case 1: /* Address register direct.  */

   601         reg = AREG(insn, 0);

   602         if (what == EA_STORE) {

   603             tcg_gen_mov_i32(reg, val);

   604             return store_dummy;

   605         } else {

   606             return gen_extend(reg, opsize, what == EA_LOADS);

   607         }

   608     case 2: /* Indirect register */

   609         reg = AREG(insn, 0);

   610         return gen_ldst(s, opsize, reg, val, what);

   611     case 3: /* Indirect postincrement.  */

   612         reg = AREG(insn, 0);

   613         result = gen_ldst(s, opsize, reg, val, what);

   614         /* ??? This is not exception safe.  The instruction may still

   615            fault after this point.  */

   616         if (what == EA_STORE || !addrp)

   617             tcg_gen_addi_i32(reg, reg, opsize_bytes(opsize));

   618         return result;

   619     case 4: /* Indirect predecrememnt.  */

   620         {

   621             TCGv tmp;

   622             if (addrp && what == EA_STORE) {

   623                 tmp = *addrp;

   624             } else {

   625                 tmp = gen_lea(s, insn, opsize);

   626                 if (IS_NULL_QREG(tmp))

   627                     return tmp;

   628                 if (addrp)

   629                     *addrp = tmp;

   630             }

   631             result = gen_ldst(s, opsize, tmp, val, what);

   632             /* ??? This is not exception safe.  The instruction may still

   633                fault after this point.  */

   634             if (what == EA_STORE || !addrp) {

   635                 reg = AREG(insn, 0);

   636                 tcg_gen_mov_i32(reg, tmp);

   637             }

   638         }

   639         return result;

   640     case 5: /* Indirect displacement.  */

   641     case 6: /* Indirect index + displacement.  */

   642         return gen_ea_once(s, insn, opsize, val, addrp, what);

   643     case 7: /* Other */

   644         switch (insn & 7) {

   645         case 0: /* Absolute short.  */

   646         case 1: /* Absolute long.  */

   647         case 2: /* pc displacement  */

   648         case 3: /* pc index+displacement.  */

   649             return gen_ea_once(s, insn, opsize, val, addrp, what);

   650         case 4: /* Immediate.  */

   651             /* Sign extend values for consistency.  */

   652             switch (opsize) {

   653             case OS_BYTE:

   654                 if (what == EA_LOADS)

   655                     offset = ldsb_code(s->pc + 1);

   656                 else

   657                     offset = ldub_code(s->pc + 1);

   658                 s->pc += 2;

   659                 break;

   660             case OS_WORD:

   661                 if (what == EA_LOADS)

   662                     offset = ldsw_code(s->pc);

   663                 else

   664                     offset = lduw_code(s->pc);

   665                 s->pc += 2;

   666                 break;

   667             case OS_LONG:

   668                 offset = read_im32(s);

   669                 break;

   670             default:

   671                 qemu_assert(0, "Bad immediate operand");

   672             }

   673             return tcg_const_i32(offset);

   674         default:

   675             return NULL_QREG;

   676         }

   677     }

   678     /* Should never happen.  */

   679     return NULL_QREG;

   680 }

   681 

   682 /* This generates a conditional branch, clobbering all temporaries.  */

   683 static void gen_jmpcc(DisasContext *s, int cond, int l1)

   684 {

   685     TCGv tmp;

   686 

   687     /* TODO: Optimize compare/branch pairs rather than always flushing

   688        flag state to CC_OP_FLAGS.  */

   689     gen_flush_flags(s);

   690     switch (cond) {

   691     case 0: /* T */

   692         tcg_gen_br(l1);

   693         break;

   694     case 1: /* F */

   695         break;

   696     case 2: /* HI (!C && !Z) */

   697         tmp = tcg_temp_new();

   698         tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_C | CCF_Z);

   699         tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1);

   700         break;

   701     case 3: /* LS (C || Z) */

   702         tmp = tcg_temp_new();

   703         tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_C | CCF_Z);

   704         tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1);

   705         break;

   706     case 4: /* CC (!C) */

   707         tmp = tcg_temp_new();

   708         tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_C);

   709         tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1);

   710         break;

   711     case 5: /* CS (C) */

   712         tmp = tcg_temp_new();

   713         tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_C);

   714         tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1);

   715         break;

   716     case 6: /* NE (!Z) */

   717         tmp = tcg_temp_new();

   718         tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_Z);

   719         tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1);

   720         break;

   721     case 7: /* EQ (Z) */

   722         tmp = tcg_temp_new();

   723         tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_Z);

   724         tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1);

   725         break;

   726     case 8: /* VC (!V) */

   727         tmp = tcg_temp_new();

   728         tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_V);

   729         tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1);

   730         break;

   731     case 9: /* VS (V) */

   732         tmp = tcg_temp_new();

   733         tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_V);

   734         tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1);

   735         break;

   736     case 10: /* PL (!N) */

   737         tmp = tcg_temp_new();

   738         tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_N);

   739         tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1);

   740         break;

   741     case 11: /* MI (N) */

   742         tmp = tcg_temp_new();

   743         tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_N);

   744         tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1);

   745         break;

   746     case 12: /* GE (!(N ^ V)) */

   747         tmp = tcg_temp_new();

   748         assert(CCF_V == (CCF_N >> 2));

   749         tcg_gen_shri_i32(tmp, QREG_CC_DEST, 2);

   750         tcg_gen_xor_i32(tmp, tmp, QREG_CC_DEST);

   751         tcg_gen_andi_i32(tmp, tmp, CCF_V);

   752         tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1);

   753         break;

   754     case 13: /* LT (N ^ V) */

   755         tmp = tcg_temp_new();

   756         assert(CCF_V == (CCF_N >> 2));

   757         tcg_gen_shri_i32(tmp, QREG_CC_DEST, 2);

   758         tcg_gen_xor_i32(tmp, tmp, QREG_CC_DEST);

   759         tcg_gen_andi_i32(tmp, tmp, CCF_V);

   760         tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1);

   761         break;

   762     case 14: /* GT (!(Z || (N ^ V))) */

   763         tmp = tcg_temp_new();

   764         assert(CCF_V == (CCF_N >> 2));

   765         tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_N);

   766         tcg_gen_shri_i32(tmp, tmp, 2);

   767         tcg_gen_xor_i32(tmp, tmp, QREG_CC_DEST);

   768         tcg_gen_andi_i32(tmp, tmp, CCF_V | CCF_Z);

   769         tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1);

   770         break;

   771     case 15: /* LE (Z || (N ^ V)) */

   772         tmp = tcg_temp_new();

   773         assert(CCF_V == (CCF_N >> 2));

   774         tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_N);

   775         tcg_gen_shri_i32(tmp, tmp, 2);

   776         tcg_gen_xor_i32(tmp, tmp, QREG_CC_DEST);

   777         tcg_gen_andi_i32(tmp, tmp, CCF_V | CCF_Z);

   778         tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1);

   779         break;

   780     default:

   781         /* Should ever happen.  */

   782         abort();

   783     }

   784 }

   785 

   786 DISAS_INSN(scc)

   787 {

   788     int l1;

   789     int cond;

   790     TCGv reg;

   791 

   792     l1 = gen_new_label();

   793     cond = (insn >> 8) & 0xf;

   794     reg = DREG(insn, 0);

   795     tcg_gen_andi_i32(reg, reg, 0xffffff00);

   796     /* This is safe because we modify the reg directly, with no other values

   797        live.  */

   798     gen_jmpcc(s, cond ^ 1, l1);

   799     tcg_gen_ori_i32(reg, reg, 0xff);

   800     gen_set_label(l1);

   801 }

   802 

   803 /* Force a TB lookup after an instruction that changes the CPU state.  */

   804 static void gen_lookup_tb(DisasContext *s)

   805 {

   806     gen_flush_cc_op(s);

   807     tcg_gen_movi_i32(QREG_PC, s->pc);

   808     s->is_jmp = DISAS_UPDATE;

   809 }

   810 

   811 /* Generate a jump to an immediate address.  */

   812 static void gen_jmp_im(DisasContext *s, uint32_t dest)

   813 {

   814     gen_flush_cc_op(s);

   815     tcg_gen_movi_i32(QREG_PC, dest);

   816     s->is_jmp = DISAS_JUMP;

   817 }

   818 

   819 /* Generate a jump to the address in qreg DEST.  */

   820 static void gen_jmp(DisasContext *s, TCGv dest)

   821 {

   822     gen_flush_cc_op(s);

   823     tcg_gen_mov_i32(QREG_PC, dest);

   824     s->is_jmp = DISAS_JUMP;

   825 }

   826 

   827 static void gen_exception(DisasContext *s, uint32_t where, int nr)

   828 {

   829     gen_flush_cc_op(s);

   830     gen_jmp_im(s, where);

   831     gen_helper_raise_exception(tcg_const_i32(nr));

   832 }

   833 

   834 static inline void gen_addr_fault(DisasContext *s)

   835 {

   836     gen_exception(s, s->insn_pc, EXCP_ADDRESS);

   837 }

   838 

   839 #define SRC_EA(result, opsize, op_sign, addrp) do { \

   840     result = gen_ea(s, insn, opsize, NULL_QREG, addrp, op_sign ? EA_LOADS : EA_LOADU); \

   841     if (IS_NULL_QREG(result)) { \

   842         gen_addr_fault(s); \

   843         return; \

   844     } \

   845     } while (0)

   846 

   847 #define DEST_EA(insn, opsize, val, addrp) do { \

   848     TCGv ea_result = gen_ea(s, insn, opsize, val, addrp, EA_STORE); \

   849     if (IS_NULL_QREG(ea_result)) { \

   850         gen_addr_fault(s); \

   851         return; \

   852     } \

   853     } while (0)

   854 

   855 /* Generate a jump to an immediate address.  */

   856 static void gen_jmp_tb(DisasContext *s, int n, uint32_t dest)

   857 {

   858     TranslationBlock *tb;

   859 

   860     tb = s->tb;

   861     if (unlikely(s->singlestep_enabled)) {

   862         gen_exception(s, dest, EXCP_DEBUG);

   863     } else if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) ||

   864                (s->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {

   865         tcg_gen_goto_tb(n);

   866         tcg_gen_movi_i32(QREG_PC, dest);

   867         tcg_gen_exit_tb((long)tb + n);

   868     } else {

   869         gen_jmp_im(s, dest);

   870         tcg_gen_exit_tb(0);

   871     }

   872     s->is_jmp = DISAS_TB_JUMP;

   873 }

   874 

   875 DISAS_INSN(undef_mac)

   876 {

   877     gen_exception(s, s->pc - 2, EXCP_LINEA);

   878 }

   879 

   880 DISAS_INSN(undef_fpu)

   881 {

   882     gen_exception(s, s->pc - 2, EXCP_LINEF);

   883 }

   884 

   885 DISAS_INSN(undef)

   886 {

   887     gen_exception(s, s->pc - 2, EXCP_UNSUPPORTED);

   888     cpu_abort(cpu_single_env, "Illegal instruction: %04x @ %08x",

   889               insn, s->pc - 2);

   890 }

   891 

   892 DISAS_INSN(mulw)

   893 {

   894     TCGv reg;

   895     TCGv tmp;

   896     TCGv src;

   897     int sign;

   898 

   899     sign = (insn & 0x100) != 0;

   900     reg = DREG(insn, 9);

   901     tmp = tcg_temp_new();

   902     if (sign)

   903         tcg_gen_ext16s_i32(tmp, reg);

   904     else

   905         tcg_gen_ext16u_i32(tmp, reg);

   906     SRC_EA(src, OS_WORD, sign, NULL);

   907     tcg_gen_mul_i32(tmp, tmp, src);

   908     tcg_gen_mov_i32(reg, tmp);

   909     /* Unlike m68k, coldfire always clears the overflow bit.  */

   910     gen_logic_cc(s, tmp);

   911 }

   912 

   913 DISAS_INSN(divw)

   914 {

   915     TCGv reg;

   916     TCGv tmp;

   917     TCGv src;

   918     int sign;

   919 

   920     sign = (insn & 0x100) != 0;

   921     reg = DREG(insn, 9);

   922     if (sign) {

   923         tcg_gen_ext16s_i32(QREG_DIV1, reg);

   924     } else {

   925         tcg_gen_ext16u_i32(QREG_DIV1, reg);

   926     }

   927     SRC_EA(src, OS_WORD, sign, NULL);

   928     tcg_gen_mov_i32(QREG_DIV2, src);

   929     if (sign) {

   930         gen_helper_divs(cpu_env, tcg_const_i32(1));

   931     } else {

   932         gen_helper_divu(cpu_env, tcg_const_i32(1));

   933     }

   934 

   935     tmp = tcg_temp_new();

   936     src = tcg_temp_new();

   937     tcg_gen_ext16u_i32(tmp, QREG_DIV1);

   938     tcg_gen_shli_i32(src, QREG_DIV2, 16);

   939     tcg_gen_or_i32(reg, tmp, src);

   940     s->cc_op = CC_OP_FLAGS;

   941 }

   942 

   943 DISAS_INSN(divl)

   944 {

   945     TCGv num;

   946     TCGv den;

   947     TCGv reg;

   948     uint16_t ext;

   949 

   950     ext = lduw_code(s->pc);

   951     s->pc += 2;

   952     if (ext & 0x87f8) {

   953         gen_exception(s, s->pc - 4, EXCP_UNSUPPORTED);

   954         return;

   955     }

   956     num = DREG(ext, 12);

   957     reg = DREG(ext, 0);

   958     tcg_gen_mov_i32(QREG_DIV1, num);

   959     SRC_EA(den, OS_LONG, 0, NULL);

   960     tcg_gen_mov_i32(QREG_DIV2, den);

   961     if (ext & 0x0800) {

   962         gen_helper_divs(cpu_env, tcg_const_i32(0));

   963     } else {

   964         gen_helper_divu(cpu_env, tcg_const_i32(0));

   965     }

   966     if ((ext & 7) == ((ext >> 12) & 7)) {

   967         /* div */

   968         tcg_gen_mov_i32 (reg, QREG_DIV1);

   969     } else {

   970         /* rem */

   971         tcg_gen_mov_i32 (reg, QREG_DIV2);

   972     }

   973     s->cc_op = CC_OP_FLAGS;

   974 }

   975 

   976 DISAS_INSN(addsub)

   977 {

   978     TCGv reg;

   979     TCGv dest;

   980     TCGv src;

   981     TCGv tmp;

   982     TCGv addr;

   983     int add;

   984 

   985     add = (insn & 0x4000) != 0;

   986     reg = DREG(insn, 9);

   987     dest = tcg_temp_new();

   988     if (insn & 0x100) {

   989         SRC_EA(tmp, OS_LONG, 0, &addr);

   990         src = reg;

   991     } else {

   992         tmp = reg;

   993         SRC_EA(src, OS_LONG, 0, NULL);

   994     }

   995     if (add) {

   996         tcg_gen_add_i32(dest, tmp, src);

   997         gen_helper_xflag_lt(QREG_CC_X, dest, src);

   998         s->cc_op = CC_OP_ADD;

   999     } else {

  1000         gen_helper_xflag_lt(QREG_CC_X, tmp, src);

  1001         tcg_gen_sub_i32(dest, tmp, src);

  1002         s->cc_op = CC_OP_SUB;

  1003     }

  1004     gen_update_cc_add(dest, src);

  1005     if (insn & 0x100) {

  1006         DEST_EA(insn, OS_LONG, dest, &addr);

  1007     } else {

  1008         tcg_gen_mov_i32(reg, dest);

  1009     }

  1010 }

  1011 

  1012 

  1013 /* Reverse the order of the bits in REG.  */

  1014 DISAS_INSN(bitrev)

  1015 {

  1016     TCGv reg;

  1017     reg = DREG(insn, 0);

  1018     gen_helper_bitrev(reg, reg);

  1019 }

  1020 

  1021 DISAS_INSN(bitop_reg)

  1022 {

  1023     int opsize;

  1024     int op;

  1025     TCGv src1;

  1026     TCGv src2;

  1027     TCGv tmp;

  1028     TCGv addr;

  1029     TCGv dest;

  1030 

  1031     if ((insn & 0x38) != 0)

  1032         opsize = OS_BYTE;

  1033     else

  1034         opsize = OS_LONG;

  1035     op = (insn >> 6) & 3;

  1036     SRC_EA(src1, opsize, 0, op ? &addr: NULL);

  1037     src2 = DREG(insn, 9);

  1038     dest = tcg_temp_new();

  1039 

  1040     gen_flush_flags(s);

  1041     tmp = tcg_temp_new();

  1042     if (opsize == OS_BYTE)

  1043         tcg_gen_andi_i32(tmp, src2, 7);

  1044     else

  1045         tcg_gen_andi_i32(tmp, src2, 31);

  1046     src2 = tmp;

  1047     tmp = tcg_temp_new();

  1048     tcg_gen_shr_i32(tmp, src1, src2);

  1049     tcg_gen_andi_i32(tmp, tmp, 1);

  1050     tcg_gen_shli_i32(tmp, tmp, 2);

  1051     /* Clear CCF_Z if bit set.  */

  1052     tcg_gen_ori_i32(QREG_CC_DEST, QREG_CC_DEST, CCF_Z);

  1053     tcg_gen_xor_i32(QREG_CC_DEST, QREG_CC_DEST, tmp);

  1054 

  1055     tcg_gen_shl_i32(tmp, tcg_const_i32(1), src2);

  1056     switch (op) {

  1057     case 1: /* bchg */

  1058         tcg_gen_xor_i32(dest, src1, tmp);

  1059         break;

  1060     case 2: /* bclr */

  1061         tcg_gen_not_i32(tmp, tmp);

  1062         tcg_gen_and_i32(dest, src1, tmp);

  1063         break;

  1064     case 3: /* bset */

  1065         tcg_gen_or_i32(dest, src1, tmp);

  1066         break;

  1067     default: /* btst */

  1068         break;

  1069     }

  1070     if (op)

  1071         DEST_EA(insn, opsize, dest, &addr);

  1072 }

  1073 

  1074 DISAS_INSN(sats)

  1075 {

  1076     TCGv reg;

  1077     reg = DREG(insn, 0);

  1078     gen_flush_flags(s);

  1079     gen_helper_sats(reg, reg, QREG_CC_DEST);

  1080     gen_logic_cc(s, reg);

  1081 }

  1082 

  1083 static void gen_push(DisasContext *s, TCGv val)

  1084 {

  1085     TCGv tmp;

  1086 

  1087     tmp = tcg_temp_new();

  1088     tcg_gen_subi_i32(tmp, QREG_SP, 4);

  1089     gen_store(s, OS_LONG, tmp, val);

  1090     tcg_gen_mov_i32(QREG_SP, tmp);

  1091 }

  1092 

  1093 DISAS_INSN(movem)

  1094 {

  1095     TCGv addr;

  1096     int i;

  1097     uint16_t mask;

  1098     TCGv reg;

  1099     TCGv tmp;

  1100     int is_load;

  1101 

  1102     mask = lduw_code(s->pc);

  1103     s->pc += 2;

  1104     tmp = gen_lea(s, insn, OS_LONG);

  1105     if (IS_NULL_QREG(tmp)) {

  1106         gen_addr_fault(s);

  1107         return;

  1108     }

  1109     addr = tcg_temp_new();

  1110     tcg_gen_mov_i32(addr, tmp);

  1111     is_load = ((insn & 0x0400) != 0);

  1112     for (i = 0; i < 16; i++, mask >>= 1) {

  1113         if (mask & 1) {

  1114             if (i < 8)

  1115                 reg = DREG(i, 0);

  1116             else

  1117                 reg = AREG(i, 0);

  1118             if (is_load) {

  1119                 tmp = gen_load(s, OS_LONG, addr, 0);

  1120                 tcg_gen_mov_i32(reg, tmp);

  1121             } else {

  1122                 gen_store(s, OS_LONG, addr, reg);

  1123             }

  1124             if (mask != 1)

  1125                 tcg_gen_addi_i32(addr, addr, 4);

  1126         }

  1127     }

  1128 }

  1129 

  1130 DISAS_INSN(bitop_im)

  1131 {

  1132     int opsize;

  1133     int op;

  1134     TCGv src1;

  1135     uint32_t mask;