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1 #if !defined(__QEMU_MIPS_EXEC_H__) |
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2 #define __QEMU_MIPS_EXEC_H__ |
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3 |
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4 //#define DEBUG_OP |
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5 |
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6 #include "config.h" |
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7 #include "mips-defs.h" |
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8 #include "dyngen-exec.h" |
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9 #include "cpu-defs.h" |
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10 |
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11 register struct CPUMIPSState *env asm(AREG0); |
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12 |
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13 #include "cpu.h" |
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14 #include "exec-all.h" |
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15 |
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16 #if !defined(CONFIG_USER_ONLY) |
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17 #include "softmmu_exec.h" |
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18 #endif /* !defined(CONFIG_USER_ONLY) */ |
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19 |
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20 void do_mtc0_status_debug(uint32_t old, uint32_t val); |
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21 void do_mtc0_status_irqraise_debug(void); |
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22 void dump_fpu(CPUState *env); |
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23 void fpu_dump_state(CPUState *env, FILE *f, |
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24 int (*fpu_fprintf)(FILE *f, const char *fmt, ...), |
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25 int flags); |
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26 |
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27 void cpu_mips_clock_init (CPUState *env); |
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28 void cpu_mips_tlb_flush (CPUState *env, int flush_global); |
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29 |
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30 static inline void env_to_regs(void) |
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31 { |
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32 } |
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33 |
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34 static inline void regs_to_env(void) |
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35 { |
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36 } |
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37 |
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38 static inline int cpu_halted(CPUState *env) |
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39 { |
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40 if (!env->halted) |
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41 return 0; |
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42 if (env->interrupt_request & |
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43 (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER)) { |
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44 env->halted = 0; |
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45 return 0; |
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46 } |
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47 return EXCP_HALTED; |
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48 } |
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49 |
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50 static inline void compute_hflags(CPUState *env) |
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51 { |
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52 env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 | |
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53 MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU | |
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54 MIPS_HFLAG_UX); |
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55 if (!(env->CP0_Status & (1 << CP0St_EXL)) && |
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56 !(env->CP0_Status & (1 << CP0St_ERL)) && |
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57 !(env->hflags & MIPS_HFLAG_DM)) { |
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58 env->hflags |= (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU; |
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59 } |
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60 #if defined(TARGET_MIPS64) |
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61 if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) || |
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62 (env->CP0_Status & (1 << CP0St_PX)) || |
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63 (env->CP0_Status & (1 << CP0St_UX))) |
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64 env->hflags |= MIPS_HFLAG_64; |
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65 if (env->CP0_Status & (1 << CP0St_UX)) |
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66 env->hflags |= MIPS_HFLAG_UX; |
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67 #endif |
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68 if ((env->CP0_Status & (1 << CP0St_CU0)) || |
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69 !(env->hflags & MIPS_HFLAG_KSU)) |
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70 env->hflags |= MIPS_HFLAG_CP0; |
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71 if (env->CP0_Status & (1 << CP0St_CU1)) |
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72 env->hflags |= MIPS_HFLAG_FPU; |
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73 if (env->CP0_Status & (1 << CP0St_FR)) |
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74 env->hflags |= MIPS_HFLAG_F64; |
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75 if (env->insn_flags & ISA_MIPS32R2) { |
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76 if (env->active_fpu.fcr0 & (1 << FCR0_F64)) |
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77 env->hflags |= MIPS_HFLAG_COP1X; |
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78 } else if (env->insn_flags & ISA_MIPS32) { |
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79 if (env->hflags & MIPS_HFLAG_64) |
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80 env->hflags |= MIPS_HFLAG_COP1X; |
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81 } else if (env->insn_flags & ISA_MIPS4) { |
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82 /* All supported MIPS IV CPUs use the XX (CU3) to enable |
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83 and disable the MIPS IV extensions to the MIPS III ISA. |
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84 Some other MIPS IV CPUs ignore the bit, so the check here |
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85 would be too restrictive for them. */ |
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86 if (env->CP0_Status & (1 << CP0St_CU3)) |
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87 env->hflags |= MIPS_HFLAG_COP1X; |
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88 } |
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89 } |
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90 |
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91 #endif /* !defined(__QEMU_MIPS_EXEC_H__) */ |