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1 /* |
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2 * MIPS emulation for qemu: CPU initialisation routines. |
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3 * |
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4 * Copyright (c) 2004-2005 Jocelyn Mayer |
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5 * Copyright (c) 2007 Herve Poussineau |
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6 * |
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7 * This library is free software; you can redistribute it and/or |
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8 * modify it under the terms of the GNU Lesser General Public |
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9 * License as published by the Free Software Foundation; either |
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10 * version 2 of the License, or (at your option) any later version. |
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11 * |
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12 * This library is distributed in the hope that it will be useful, |
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13 * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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15 * Lesser General Public License for more details. |
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16 * |
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17 * You should have received a copy of the GNU Lesser General Public |
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18 * License along with this library; if not, write to the Free Software |
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19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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20 */ |
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21 |
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22 /* CPU / CPU family specific config register values. */ |
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23 |
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24 /* Have config1, uncached coherency */ |
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25 #define MIPS_CONFIG0 \ |
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26 ((1 << CP0C0_M) | (0x2 << CP0C0_K0)) |
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27 |
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28 /* Have config2, no coprocessor2 attached, no MDMX support attached, |
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29 no performance counters, watch registers present, |
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30 no code compression, EJTAG present, no FPU */ |
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31 #define MIPS_CONFIG1 \ |
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32 ((1 << CP0C1_M) | \ |
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33 (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \ |
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34 (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \ |
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35 (0 << CP0C1_FP)) |
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36 |
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37 /* Have config3, no tertiary/secondary caches implemented */ |
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38 #define MIPS_CONFIG2 \ |
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39 ((1 << CP0C2_M)) |
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40 |
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41 /* No config4, no DSP ASE, no large physaddr (PABITS), |
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42 no external interrupt controller, no vectored interupts, |
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43 no 1kb pages, no SmartMIPS ASE, no trace logic */ |
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44 #define MIPS_CONFIG3 \ |
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45 ((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \ |
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46 (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \ |
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47 (0 << CP0C3_SM) | (0 << CP0C3_TL)) |
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48 |
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49 /* Define a implementation number of 1. |
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50 Define a major version 1, minor version 0. */ |
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51 #define MIPS_FCR0 ((0 << FCR0_S) | (0x1 << FCR0_PRID) | (0x10 << FCR0_REV)) |
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52 |
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53 /* MMU types, the first four entries have the same layout as the |
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54 CP0C0_MT field. */ |
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55 enum mips_mmu_types { |
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56 MMU_TYPE_NONE, |
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57 MMU_TYPE_R4000, |
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58 MMU_TYPE_RESERVED, |
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59 MMU_TYPE_FMT, |
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60 MMU_TYPE_R3000, |
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61 MMU_TYPE_R6000, |
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62 MMU_TYPE_R8000 |
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63 }; |
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64 |
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65 struct mips_def_t { |
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66 const char *name; |
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67 int32_t CP0_PRid; |
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68 int32_t CP0_Config0; |
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69 int32_t CP0_Config1; |
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70 int32_t CP0_Config2; |
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71 int32_t CP0_Config3; |
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72 int32_t CP0_Config6; |
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73 int32_t CP0_Config7; |
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74 int32_t SYNCI_Step; |
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75 int32_t CCRes; |
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76 int32_t CP0_Status_rw_bitmask; |
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77 int32_t CP0_TCStatus_rw_bitmask; |
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78 int32_t CP0_SRSCtl; |
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79 int32_t CP1_fcr0; |
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80 int32_t SEGBITS; |
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81 int32_t PABITS; |
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82 int32_t CP0_SRSConf0_rw_bitmask; |
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83 int32_t CP0_SRSConf0; |
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84 int32_t CP0_SRSConf1_rw_bitmask; |
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85 int32_t CP0_SRSConf1; |
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86 int32_t CP0_SRSConf2_rw_bitmask; |
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87 int32_t CP0_SRSConf2; |
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88 int32_t CP0_SRSConf3_rw_bitmask; |
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89 int32_t CP0_SRSConf3; |
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90 int32_t CP0_SRSConf4_rw_bitmask; |
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91 int32_t CP0_SRSConf4; |
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92 int insn_flags; |
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93 enum mips_mmu_types mmu_type; |
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94 }; |
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95 |
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96 /*****************************************************************************/ |
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97 /* MIPS CPU definitions */ |
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98 static const mips_def_t mips_defs[] = |
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99 { |
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100 { |
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101 .name = "4Kc", |
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102 .CP0_PRid = 0x00018000, |
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103 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT), |
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104 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | |
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105 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
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106 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), |
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107 .CP0_Config2 = MIPS_CONFIG2, |
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108 .CP0_Config3 = MIPS_CONFIG3, |
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109 .SYNCI_Step = 32, |
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110 .CCRes = 2, |
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111 .CP0_Status_rw_bitmask = 0x1278FF17, |
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112 .SEGBITS = 32, |
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113 .PABITS = 32, |
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114 .insn_flags = CPU_MIPS32 | ASE_MIPS16, |
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115 .mmu_type = MMU_TYPE_R4000, |
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116 }, |
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117 { |
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118 .name = "4Km", |
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119 .CP0_PRid = 0x00018300, |
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120 /* Config1 implemented, fixed mapping MMU, |
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121 no virtual icache, uncached coherency. */ |
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122 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT), |
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123 .CP0_Config1 = MIPS_CONFIG1 | |
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124 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
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125 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), |
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126 .CP0_Config2 = MIPS_CONFIG2, |
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127 .CP0_Config3 = MIPS_CONFIG3, |
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128 .SYNCI_Step = 32, |
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129 .CCRes = 2, |
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130 .CP0_Status_rw_bitmask = 0x1258FF17, |
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131 .SEGBITS = 32, |
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132 .PABITS = 32, |
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133 .insn_flags = CPU_MIPS32 | ASE_MIPS16, |
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134 .mmu_type = MMU_TYPE_FMT, |
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135 }, |
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136 { |
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137 .name = "4KEcR1", |
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138 .CP0_PRid = 0x00018400, |
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139 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT), |
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140 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | |
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141 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
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142 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), |
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143 .CP0_Config2 = MIPS_CONFIG2, |
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144 .CP0_Config3 = MIPS_CONFIG3, |
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145 .SYNCI_Step = 32, |
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146 .CCRes = 2, |
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147 .CP0_Status_rw_bitmask = 0x1278FF17, |
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148 .SEGBITS = 32, |
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149 .PABITS = 32, |
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150 .insn_flags = CPU_MIPS32 | ASE_MIPS16, |
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151 .mmu_type = MMU_TYPE_R4000, |
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152 }, |
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153 { |
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154 .name = "4KEmR1", |
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155 .CP0_PRid = 0x00018500, |
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156 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT), |
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157 .CP0_Config1 = MIPS_CONFIG1 | |
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158 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
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159 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), |
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160 .CP0_Config2 = MIPS_CONFIG2, |
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161 .CP0_Config3 = MIPS_CONFIG3, |
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162 .SYNCI_Step = 32, |
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163 .CCRes = 2, |
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164 .CP0_Status_rw_bitmask = 0x1258FF17, |
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165 .SEGBITS = 32, |
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166 .PABITS = 32, |
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167 .insn_flags = CPU_MIPS32 | ASE_MIPS16, |
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168 .mmu_type = MMU_TYPE_FMT, |
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169 }, |
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170 { |
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171 .name = "4KEc", |
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172 .CP0_PRid = 0x00019000, |
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173 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | |
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174 (MMU_TYPE_R4000 << CP0C0_MT), |
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175 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | |
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176 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
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177 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), |
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178 .CP0_Config2 = MIPS_CONFIG2, |
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179 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt), |
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180 .SYNCI_Step = 32, |
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181 .CCRes = 2, |
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182 .CP0_Status_rw_bitmask = 0x1278FF17, |
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183 .SEGBITS = 32, |
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184 .PABITS = 32, |
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185 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16, |
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186 .mmu_type = MMU_TYPE_R4000, |
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187 }, |
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188 { |
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189 .name = "4KEm", |
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190 .CP0_PRid = 0x00019100, |
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191 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | |
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192 (MMU_TYPE_FMT << CP0C0_MT), |
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193 .CP0_Config1 = MIPS_CONFIG1 | |
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194 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
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195 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), |
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196 .CP0_Config2 = MIPS_CONFIG2, |
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197 .CP0_Config3 = MIPS_CONFIG3, |
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198 .SYNCI_Step = 32, |
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199 .CCRes = 2, |
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200 .CP0_Status_rw_bitmask = 0x1258FF17, |
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201 .SEGBITS = 32, |
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202 .PABITS = 32, |
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203 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16, |
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204 .mmu_type = MMU_TYPE_FMT, |
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205 }, |
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206 { |
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207 .name = "24Kc", |
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208 .CP0_PRid = 0x00019300, |
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209 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | |
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210 (MMU_TYPE_R4000 << CP0C0_MT), |
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211 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | |
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212 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
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213 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), |
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214 .CP0_Config2 = MIPS_CONFIG2, |
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215 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt), |
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216 .SYNCI_Step = 32, |
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217 .CCRes = 2, |
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218 /* No DSP implemented. */ |
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219 .CP0_Status_rw_bitmask = 0x1278FF1F, |
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220 .SEGBITS = 32, |
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221 .PABITS = 32, |
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222 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16, |
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223 .mmu_type = MMU_TYPE_R4000, |
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224 }, |
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225 { |
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226 .name = "24Kf", |
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227 .CP0_PRid = 0x00019300, |
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228 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | |
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229 (MMU_TYPE_R4000 << CP0C0_MT), |
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230 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) | |
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231 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
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232 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), |
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233 .CP0_Config2 = MIPS_CONFIG2, |
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234 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt), |
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235 .SYNCI_Step = 32, |
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236 .CCRes = 2, |
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237 /* No DSP implemented. */ |
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238 .CP0_Status_rw_bitmask = 0x3678FF1F, |
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239 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | |
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240 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID), |
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241 .SEGBITS = 32, |
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242 .PABITS = 32, |
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243 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16, |
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244 .mmu_type = MMU_TYPE_R4000, |
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245 }, |
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246 { |
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247 .name = "34Kf", |
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248 .CP0_PRid = 0x00019500, |
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249 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | |
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250 (MMU_TYPE_R4000 << CP0C0_MT), |
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251 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) | |
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252 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
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253 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), |
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254 .CP0_Config2 = MIPS_CONFIG2, |
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255 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt) | (1 << CP0C3_MT), |
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256 .SYNCI_Step = 32, |
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257 .CCRes = 2, |
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258 /* No DSP implemented. */ |
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259 .CP0_Status_rw_bitmask = 0x3678FF1F, |
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260 /* No DSP implemented. */ |
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261 .CP0_TCStatus_rw_bitmask = (0 << CP0TCSt_TCU3) | (0 << CP0TCSt_TCU2) | |
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262 (1 << CP0TCSt_TCU1) | (1 << CP0TCSt_TCU0) | |
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263 (0 << CP0TCSt_TMX) | (1 << CP0TCSt_DT) | |
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264 (1 << CP0TCSt_DA) | (1 << CP0TCSt_A) | |
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265 (0x3 << CP0TCSt_TKSU) | (1 << CP0TCSt_IXMT) | |
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266 (0xff << CP0TCSt_TASID), |
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267 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | |
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268 (1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID), |
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269 .CP0_SRSCtl = (0xf << CP0SRSCtl_HSS), |
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270 .CP0_SRSConf0_rw_bitmask = 0x3fffffff, |
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271 .CP0_SRSConf0 = (1 << CP0SRSC0_M) | (0x3fe << CP0SRSC0_SRS3) | |
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272 (0x3fe << CP0SRSC0_SRS2) | (0x3fe << CP0SRSC0_SRS1), |
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273 .CP0_SRSConf1_rw_bitmask = 0x3fffffff, |
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274 .CP0_SRSConf1 = (1 << CP0SRSC1_M) | (0x3fe << CP0SRSC1_SRS6) | |
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275 (0x3fe << CP0SRSC1_SRS5) | (0x3fe << CP0SRSC1_SRS4), |
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276 .CP0_SRSConf2_rw_bitmask = 0x3fffffff, |
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277 .CP0_SRSConf2 = (1 << CP0SRSC2_M) | (0x3fe << CP0SRSC2_SRS9) | |
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278 (0x3fe << CP0SRSC2_SRS8) | (0x3fe << CP0SRSC2_SRS7), |
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279 .CP0_SRSConf3_rw_bitmask = 0x3fffffff, |
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280 .CP0_SRSConf3 = (1 << CP0SRSC3_M) | (0x3fe << CP0SRSC3_SRS12) | |
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281 (0x3fe << CP0SRSC3_SRS11) | (0x3fe << CP0SRSC3_SRS10), |
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282 .CP0_SRSConf4_rw_bitmask = 0x3fffffff, |
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283 .CP0_SRSConf4 = (0x3fe << CP0SRSC4_SRS15) | |
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284 (0x3fe << CP0SRSC4_SRS14) | (0x3fe << CP0SRSC4_SRS13), |
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285 .SEGBITS = 32, |
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286 .PABITS = 32, |
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287 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT, |
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288 .mmu_type = MMU_TYPE_R4000, |
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289 }, |
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290 #if defined(TARGET_MIPS64) |
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291 { |
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292 .name = "R4000", |
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293 .CP0_PRid = 0x00000400, |
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294 /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */ |
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295 .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0), |
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296 /* Note: Config1 is only used internally, the R4000 has only Config0. */ |
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297 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU), |
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298 .SYNCI_Step = 16, |
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299 .CCRes = 2, |
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300 .CP0_Status_rw_bitmask = 0x3678FFFF, |
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301 /* The R4000 has a full 64bit FPU but doesn't use the fcr0 bits. */ |
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302 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV), |
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303 .SEGBITS = 40, |
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304 .PABITS = 36, |
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305 .insn_flags = CPU_MIPS3, |
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306 .mmu_type = MMU_TYPE_R4000, |
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307 }, |
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308 { |
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309 .name = "VR5432", |
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310 .CP0_PRid = 0x00005400, |
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311 /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */ |
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312 .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0), |
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313 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU), |
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314 .SYNCI_Step = 16, |
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315 .CCRes = 2, |
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316 .CP0_Status_rw_bitmask = 0x3678FFFF, |
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317 /* The VR5432 has a full 64bit FPU but doesn't use the fcr0 bits. */ |
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318 .CP1_fcr0 = (0x54 << FCR0_PRID) | (0x0 << FCR0_REV), |
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319 .SEGBITS = 40, |
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320 .PABITS = 32, |
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321 .insn_flags = CPU_VR54XX, |
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322 .mmu_type = MMU_TYPE_R4000, |
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323 }, |
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324 { |
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325 .name = "5Kc", |
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326 .CP0_PRid = 0x00018100, |
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327 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) | |
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328 (MMU_TYPE_R4000 << CP0C0_MT), |
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329 .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) | |
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330 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) | |
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331 (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) | |
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332 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), |
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333 .CP0_Config2 = MIPS_CONFIG2, |
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334 .CP0_Config3 = MIPS_CONFIG3, |
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335 .SYNCI_Step = 32, |
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336 .CCRes = 2, |
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337 .CP0_Status_rw_bitmask = 0x32F8FFFF, |
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338 .SEGBITS = 42, |
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339 .PABITS = 36, |
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340 .insn_flags = CPU_MIPS64, |
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341 .mmu_type = MMU_TYPE_R4000, |
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342 }, |
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343 { |
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344 .name = "5Kf", |
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345 .CP0_PRid = 0x00018100, |
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346 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) | |
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347 (MMU_TYPE_R4000 << CP0C0_MT), |
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348 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) | |
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349 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) | |
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350 (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) | |
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351 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), |
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352 .CP0_Config2 = MIPS_CONFIG2, |
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353 .CP0_Config3 = MIPS_CONFIG3, |
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354 .SYNCI_Step = 32, |
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355 .CCRes = 2, |
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356 .CP0_Status_rw_bitmask = 0x36F8FFFF, |
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357 /* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */ |
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358 .CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) | |
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359 (0x81 << FCR0_PRID) | (0x0 << FCR0_REV), |
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360 .SEGBITS = 42, |
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361 .PABITS = 36, |
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362 .insn_flags = CPU_MIPS64, |
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363 .mmu_type = MMU_TYPE_R4000, |
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364 }, |
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365 { |
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366 .name = "20Kc", |
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367 /* We emulate a later version of the 20Kc, earlier ones had a broken |
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368 WAIT instruction. */ |
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369 .CP0_PRid = 0x000182a0, |
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370 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) | |
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371 (MMU_TYPE_R4000 << CP0C0_MT) | (1 << CP0C0_VI), |
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372 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU) | |
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373 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) | |
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374 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | |
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375 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), |
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376 .CP0_Config2 = MIPS_CONFIG2, |
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377 .CP0_Config3 = MIPS_CONFIG3, |
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378 .SYNCI_Step = 32, |
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379 .CCRes = 1, |
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380 .CP0_Status_rw_bitmask = 0x36FBFFFF, |
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381 /* The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */ |
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382 .CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) | |
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383 (1 << FCR0_D) | (1 << FCR0_S) | |
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384 (0x82 << FCR0_PRID) | (0x0 << FCR0_REV), |
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385 .SEGBITS = 40, |
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386 .PABITS = 36, |
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387 .insn_flags = CPU_MIPS64 | ASE_MIPS3D, |
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388 .mmu_type = MMU_TYPE_R4000, |
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389 }, |
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390 { |
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391 /* A generic CPU providing MIPS64 Release 2 features. |
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392 FIXME: Eventually this should be replaced by a real CPU model. */ |
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393 .name = "MIPS64R2-generic", |
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394 .CP0_PRid = 0x00010000, |
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395 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | |
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396 (MMU_TYPE_R4000 << CP0C0_MT), |
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397 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) | |
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398 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) | |
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399 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | |
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400 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), |
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401 .CP0_Config2 = MIPS_CONFIG2, |
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402 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA), |
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403 .SYNCI_Step = 32, |
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404 .CCRes = 2, |
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405 .CP0_Status_rw_bitmask = 0x36FBFFFF, |
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406 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) | |
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407 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | |
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408 (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV), |
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409 .SEGBITS = 42, |
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410 /* The architectural limit is 59, but we have hardcoded 36 bit |
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411 in some places... |
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412 .PABITS = 59, */ /* the architectural limit */ |
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413 .PABITS = 36, |
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414 .insn_flags = CPU_MIPS64R2 | ASE_MIPS3D, |
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415 .mmu_type = MMU_TYPE_R4000, |
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416 }, |
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417 #endif |
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418 }; |
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419 |
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420 static const mips_def_t *cpu_mips_find_by_name (const char *name) |
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421 { |
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422 int i; |
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423 |
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424 for (i = 0; i < ARRAY_SIZE(mips_defs); i++) { |
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425 if (strcasecmp(name, mips_defs[i].name) == 0) { |
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426 return &mips_defs[i]; |
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427 } |
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428 } |
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429 return NULL; |
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430 } |
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431 |
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432 void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)) |
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433 { |
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434 int i; |
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435 |
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436 for (i = 0; i < ARRAY_SIZE(mips_defs); i++) { |
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437 (*cpu_fprintf)(f, "MIPS '%s'\n", |
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438 mips_defs[i].name); |
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439 } |
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440 } |
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441 |
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442 #ifndef CONFIG_USER_ONLY |
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443 static void no_mmu_init (CPUMIPSState *env, const mips_def_t *def) |
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444 { |
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445 env->tlb->nb_tlb = 1; |
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446 env->tlb->map_address = &no_mmu_map_address; |
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447 } |
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448 |
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449 static void fixed_mmu_init (CPUMIPSState *env, const mips_def_t *def) |
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450 { |
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451 env->tlb->nb_tlb = 1; |
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452 env->tlb->map_address = &fixed_mmu_map_address; |
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453 } |
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454 |
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455 static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def) |
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456 { |
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457 env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63); |
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458 env->tlb->map_address = &r4k_map_address; |
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459 env->tlb->do_tlbwi = r4k_do_tlbwi; |
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460 env->tlb->do_tlbwr = r4k_do_tlbwr; |
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461 env->tlb->do_tlbp = r4k_do_tlbp; |
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462 env->tlb->do_tlbr = r4k_do_tlbr; |
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463 } |
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464 |
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465 static void mmu_init (CPUMIPSState *env, const mips_def_t *def) |
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466 { |
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467 env->tlb = qemu_mallocz(sizeof(CPUMIPSTLBContext)); |
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468 |
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469 switch (def->mmu_type) { |
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470 case MMU_TYPE_NONE: |
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471 no_mmu_init(env, def); |
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472 break; |
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473 case MMU_TYPE_R4000: |
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474 r4k_mmu_init(env, def); |
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475 break; |
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476 case MMU_TYPE_FMT: |
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477 fixed_mmu_init(env, def); |
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478 break; |
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479 case MMU_TYPE_R3000: |
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480 case MMU_TYPE_R6000: |
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481 case MMU_TYPE_R8000: |
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482 default: |
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483 cpu_abort(env, "MMU type not supported\n"); |
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484 } |
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485 env->CP0_Random = env->tlb->nb_tlb - 1; |
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486 env->tlb->tlb_in_use = env->tlb->nb_tlb; |
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487 } |
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488 #endif /* CONFIG_USER_ONLY */ |
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489 |
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490 static void fpu_init (CPUMIPSState *env, const mips_def_t *def) |
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491 { |
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492 int i; |
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493 |
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494 for (i = 0; i < MIPS_FPU_MAX; i++) |
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495 env->fpus[i].fcr0 = def->CP1_fcr0; |
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496 |
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497 memcpy(&env->active_fpu, &env->fpus[0], sizeof(env->active_fpu)); |
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498 if (env->user_mode_only) { |
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499 if (env->CP0_Config1 & (1 << CP0C1_FP)) |
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500 env->hflags |= MIPS_HFLAG_FPU; |
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501 #ifdef TARGET_MIPS64 |
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502 if (env->active_fpu.fcr0 & (1 << FCR0_F64)) |
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503 env->hflags |= MIPS_HFLAG_F64; |
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504 #endif |
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505 } |
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506 } |
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507 |
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508 static void mvp_init (CPUMIPSState *env, const mips_def_t *def) |
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509 { |
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510 env->mvp = qemu_mallocz(sizeof(CPUMIPSMVPContext)); |
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511 |
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512 /* MVPConf1 implemented, TLB sharable, no gating storage support, |
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513 programmable cache partitioning implemented, number of allocatable |
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514 and sharable TLB entries, MVP has allocatable TCs, 2 VPEs |
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515 implemented, 5 TCs implemented. */ |
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516 env->mvp->CP0_MVPConf0 = (1 << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) | |
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517 (0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) | |
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518 // TODO: actually do 2 VPEs. |
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519 // (1 << CP0MVPC0_TCA) | (0x1 << CP0MVPC0_PVPE) | |
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520 // (0x04 << CP0MVPC0_PTC); |
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521 (1 << CP0MVPC0_TCA) | (0x0 << CP0MVPC0_PVPE) | |
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522 (0x04 << CP0MVPC0_PTC); |
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523 /* Usermode has no TLB support */ |
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524 if (!env->user_mode_only) |
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525 env->mvp->CP0_MVPConf0 |= (env->tlb->nb_tlb << CP0MVPC0_PTLBE); |
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526 |
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527 /* Allocatable CP1 have media extensions, allocatable CP1 have FP support, |
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528 no UDI implemented, no CP2 implemented, 1 CP1 implemented. */ |
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529 env->mvp->CP0_MVPConf1 = (1 << CP0MVPC1_CIM) | (1 << CP0MVPC1_CIF) | |
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530 (0x0 << CP0MVPC1_PCX) | (0x0 << CP0MVPC1_PCP2) | |
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531 (0x1 << CP0MVPC1_PCP1); |
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532 } |
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533 |
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534 static int cpu_mips_register (CPUMIPSState *env, const mips_def_t *def) |
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535 { |
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536 env->CP0_PRid = def->CP0_PRid; |
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537 env->CP0_Config0 = def->CP0_Config0; |
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538 #ifdef TARGET_WORDS_BIGENDIAN |
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539 env->CP0_Config0 |= (1 << CP0C0_BE); |
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540 #endif |
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541 env->CP0_Config1 = def->CP0_Config1; |
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542 env->CP0_Config2 = def->CP0_Config2; |
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543 env->CP0_Config3 = def->CP0_Config3; |
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544 env->CP0_Config6 = def->CP0_Config6; |
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545 env->CP0_Config7 = def->CP0_Config7; |
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546 env->SYNCI_Step = def->SYNCI_Step; |
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547 env->CCRes = def->CCRes; |
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548 env->CP0_Status_rw_bitmask = def->CP0_Status_rw_bitmask; |
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549 env->CP0_TCStatus_rw_bitmask = def->CP0_TCStatus_rw_bitmask; |
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550 env->CP0_SRSCtl = def->CP0_SRSCtl; |
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551 env->current_tc = 0; |
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552 env->SEGBITS = def->SEGBITS; |
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553 env->SEGMask = (target_ulong)((1ULL << def->SEGBITS) - 1); |
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554 #if defined(TARGET_MIPS64) |
|
555 if (def->insn_flags & ISA_MIPS3) { |
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556 env->hflags |= MIPS_HFLAG_64; |
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557 env->SEGMask |= 3ULL << 62; |
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558 } |
|
559 #endif |
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560 env->PABITS = def->PABITS; |
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561 env->PAMask = (target_ulong)((1ULL << def->PABITS) - 1); |
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562 env->CP0_SRSConf0_rw_bitmask = def->CP0_SRSConf0_rw_bitmask; |
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563 env->CP0_SRSConf0 = def->CP0_SRSConf0; |
|
564 env->CP0_SRSConf1_rw_bitmask = def->CP0_SRSConf1_rw_bitmask; |
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565 env->CP0_SRSConf1 = def->CP0_SRSConf1; |
|
566 env->CP0_SRSConf2_rw_bitmask = def->CP0_SRSConf2_rw_bitmask; |
|
567 env->CP0_SRSConf2 = def->CP0_SRSConf2; |
|
568 env->CP0_SRSConf3_rw_bitmask = def->CP0_SRSConf3_rw_bitmask; |
|
569 env->CP0_SRSConf3 = def->CP0_SRSConf3; |
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570 env->CP0_SRSConf4_rw_bitmask = def->CP0_SRSConf4_rw_bitmask; |
|
571 env->CP0_SRSConf4 = def->CP0_SRSConf4; |
|
572 env->insn_flags = def->insn_flags; |
|
573 |
|
574 #ifndef CONFIG_USER_ONLY |
|
575 if (!env->user_mode_only) |
|
576 mmu_init(env, def); |
|
577 #endif |
|
578 fpu_init(env, def); |
|
579 mvp_init(env, def); |
|
580 return 0; |
|
581 } |