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1 #ifndef CPU_SPARC_H |
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2 #define CPU_SPARC_H |
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3 |
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4 #include "config.h" |
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5 |
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6 #if !defined(TARGET_SPARC64) |
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7 #define TARGET_LONG_BITS 32 |
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8 #define TARGET_FPREGS 32 |
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9 #define TARGET_PAGE_BITS 12 /* 4k */ |
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10 #else |
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11 #define TARGET_LONG_BITS 64 |
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12 #define TARGET_FPREGS 64 |
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13 #define TARGET_PAGE_BITS 13 /* 8k */ |
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14 #endif |
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15 |
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16 #define TARGET_PHYS_ADDR_BITS 64 |
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17 |
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18 #include "cpu-defs.h" |
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19 |
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20 #include "softfloat.h" |
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21 |
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22 #define TARGET_HAS_ICE 1 |
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23 |
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24 #if !defined(TARGET_SPARC64) |
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25 #define ELF_MACHINE EM_SPARC |
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26 #else |
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27 #define ELF_MACHINE EM_SPARCV9 |
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28 #endif |
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29 |
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30 /*#define EXCP_INTERRUPT 0x100*/ |
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31 |
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32 /* trap definitions */ |
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33 #ifndef TARGET_SPARC64 |
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34 #define TT_TFAULT 0x01 |
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35 #define TT_ILL_INSN 0x02 |
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36 #define TT_PRIV_INSN 0x03 |
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37 #define TT_NFPU_INSN 0x04 |
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38 #define TT_WIN_OVF 0x05 |
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39 #define TT_WIN_UNF 0x06 |
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40 #define TT_UNALIGNED 0x07 |
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41 #define TT_FP_EXCP 0x08 |
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42 #define TT_DFAULT 0x09 |
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43 #define TT_TOVF 0x0a |
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44 #define TT_EXTINT 0x10 |
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45 #define TT_CODE_ACCESS 0x21 |
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46 #define TT_UNIMP_FLUSH 0x25 |
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47 #define TT_DATA_ACCESS 0x29 |
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48 #define TT_DIV_ZERO 0x2a |
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49 #define TT_NCP_INSN 0x24 |
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50 #define TT_TRAP 0x80 |
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51 #else |
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52 #define TT_TFAULT 0x08 |
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53 #define TT_CODE_ACCESS 0x0a |
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54 #define TT_ILL_INSN 0x10 |
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55 #define TT_UNIMP_FLUSH TT_ILL_INSN |
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56 #define TT_PRIV_INSN 0x11 |
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57 #define TT_NFPU_INSN 0x20 |
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58 #define TT_FP_EXCP 0x21 |
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59 #define TT_TOVF 0x23 |
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60 #define TT_CLRWIN 0x24 |
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61 #define TT_DIV_ZERO 0x28 |
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62 #define TT_DFAULT 0x30 |
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63 #define TT_DATA_ACCESS 0x32 |
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64 #define TT_UNALIGNED 0x34 |
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65 #define TT_PRIV_ACT 0x37 |
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66 #define TT_EXTINT 0x40 |
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67 #define TT_IVEC 0x60 |
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68 #define TT_TMISS 0x64 |
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69 #define TT_DMISS 0x68 |
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70 #define TT_DPROT 0x6c |
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71 #define TT_SPILL 0x80 |
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72 #define TT_FILL 0xc0 |
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73 #define TT_WOTHER 0x10 |
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74 #define TT_TRAP 0x100 |
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75 #endif |
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76 |
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77 #define PSR_NEG_SHIFT 23 |
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78 #define PSR_NEG (1 << PSR_NEG_SHIFT) |
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79 #define PSR_ZERO_SHIFT 22 |
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80 #define PSR_ZERO (1 << PSR_ZERO_SHIFT) |
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81 #define PSR_OVF_SHIFT 21 |
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82 #define PSR_OVF (1 << PSR_OVF_SHIFT) |
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83 #define PSR_CARRY_SHIFT 20 |
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84 #define PSR_CARRY (1 << PSR_CARRY_SHIFT) |
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85 #define PSR_ICC (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY) |
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86 #define PSR_EF (1<<12) |
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87 #define PSR_PIL 0xf00 |
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88 #define PSR_S (1<<7) |
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89 #define PSR_PS (1<<6) |
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90 #define PSR_ET (1<<5) |
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91 #define PSR_CWP 0x1f |
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92 |
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93 /* Trap base register */ |
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94 #define TBR_BASE_MASK 0xfffff000 |
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95 |
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96 #if defined(TARGET_SPARC64) |
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97 #define PS_IG (1<<11) |
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98 #define PS_MG (1<<10) |
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99 #define PS_RMO (1<<7) |
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100 #define PS_RED (1<<5) |
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101 #define PS_PEF (1<<4) |
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102 #define PS_AM (1<<3) |
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103 #define PS_PRIV (1<<2) |
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104 #define PS_IE (1<<1) |
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105 #define PS_AG (1<<0) |
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106 |
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107 #define FPRS_FEF (1<<2) |
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108 |
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109 #define HS_PRIV (1<<2) |
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110 #endif |
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111 |
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112 /* Fcc */ |
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113 #define FSR_RD1 (1ULL << 31) |
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114 #define FSR_RD0 (1ULL << 30) |
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115 #define FSR_RD_MASK (FSR_RD1 | FSR_RD0) |
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116 #define FSR_RD_NEAREST 0 |
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117 #define FSR_RD_ZERO FSR_RD0 |
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118 #define FSR_RD_POS FSR_RD1 |
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119 #define FSR_RD_NEG (FSR_RD1 | FSR_RD0) |
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120 |
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121 #define FSR_NVM (1ULL << 27) |
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122 #define FSR_OFM (1ULL << 26) |
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123 #define FSR_UFM (1ULL << 25) |
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124 #define FSR_DZM (1ULL << 24) |
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125 #define FSR_NXM (1ULL << 23) |
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126 #define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM) |
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127 |
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128 #define FSR_NVA (1ULL << 9) |
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129 #define FSR_OFA (1ULL << 8) |
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130 #define FSR_UFA (1ULL << 7) |
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131 #define FSR_DZA (1ULL << 6) |
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132 #define FSR_NXA (1ULL << 5) |
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133 #define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA) |
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134 |
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135 #define FSR_NVC (1ULL << 4) |
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136 #define FSR_OFC (1ULL << 3) |
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137 #define FSR_UFC (1ULL << 2) |
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138 #define FSR_DZC (1ULL << 1) |
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139 #define FSR_NXC (1ULL << 0) |
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140 #define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC) |
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141 |
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142 #define FSR_FTT2 (1ULL << 16) |
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143 #define FSR_FTT1 (1ULL << 15) |
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144 #define FSR_FTT0 (1ULL << 14) |
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145 //gcc warns about constant overflow for ~FSR_FTT_MASK |
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146 //#define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0) |
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147 #ifdef TARGET_SPARC64 |
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148 #define FSR_FTT_NMASK 0xfffffffffffe3fffULL |
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149 #define FSR_FTT_CEXC_NMASK 0xfffffffffffe3fe0ULL |
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150 #define FSR_LDFSR_OLDMASK 0x0000003f000fc000ULL |
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151 #define FSR_LDXFSR_MASK 0x0000003fcfc00fffULL |
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152 #define FSR_LDXFSR_OLDMASK 0x00000000000fc000ULL |
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153 #else |
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154 #define FSR_FTT_NMASK 0xfffe3fffULL |
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155 #define FSR_FTT_CEXC_NMASK 0xfffe3fe0ULL |
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156 #define FSR_LDFSR_OLDMASK 0x000fc000ULL |
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157 #endif |
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158 #define FSR_LDFSR_MASK 0xcfc00fffULL |
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159 #define FSR_FTT_IEEE_EXCP (1ULL << 14) |
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160 #define FSR_FTT_UNIMPFPOP (3ULL << 14) |
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161 #define FSR_FTT_SEQ_ERROR (4ULL << 14) |
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162 #define FSR_FTT_INVAL_FPR (6ULL << 14) |
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163 |
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164 #define FSR_FCC1_SHIFT 11 |
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165 #define FSR_FCC1 (1ULL << FSR_FCC1_SHIFT) |
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166 #define FSR_FCC0_SHIFT 10 |
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167 #define FSR_FCC0 (1ULL << FSR_FCC0_SHIFT) |
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168 |
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169 /* MMU */ |
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170 #define MMU_E (1<<0) |
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171 #define MMU_NF (1<<1) |
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172 |
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173 #define PTE_ENTRYTYPE_MASK 3 |
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174 #define PTE_ACCESS_MASK 0x1c |
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175 #define PTE_ACCESS_SHIFT 2 |
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176 #define PTE_PPN_SHIFT 7 |
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177 #define PTE_ADDR_MASK 0xffffff00 |
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178 |
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179 #define PG_ACCESSED_BIT 5 |
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180 #define PG_MODIFIED_BIT 6 |
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181 #define PG_CACHE_BIT 7 |
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182 |
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183 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT) |
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184 #define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT) |
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185 #define PG_CACHE_MASK (1 << PG_CACHE_BIT) |
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186 |
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187 /* 3 <= NWINDOWS <= 32. */ |
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188 #define MIN_NWINDOWS 3 |
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189 #define MAX_NWINDOWS 32 |
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190 |
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191 #if !defined(TARGET_SPARC64) |
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192 #define NB_MMU_MODES 2 |
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193 #else |
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194 #define NB_MMU_MODES 3 |
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195 typedef struct trap_state { |
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196 uint64_t tpc; |
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197 uint64_t tnpc; |
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198 uint64_t tstate; |
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199 uint32_t tt; |
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200 } trap_state; |
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201 #endif |
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202 |
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203 typedef struct sparc_def_t { |
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204 const char *name; |
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205 target_ulong iu_version; |
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206 uint32_t fpu_version; |
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207 uint32_t mmu_version; |
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208 uint32_t mmu_bm; |
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209 uint32_t mmu_ctpr_mask; |
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210 uint32_t mmu_cxr_mask; |
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211 uint32_t mmu_sfsr_mask; |
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212 uint32_t mmu_trcr_mask; |
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213 uint32_t mxcc_version; |
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214 uint32_t features; |
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215 uint32_t nwindows; |
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216 uint32_t maxtl; |
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217 } sparc_def_t; |
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218 |
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219 #define CPU_FEATURE_FLOAT (1 << 0) |
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220 #define CPU_FEATURE_FLOAT128 (1 << 1) |
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221 #define CPU_FEATURE_SWAP (1 << 2) |
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222 #define CPU_FEATURE_MUL (1 << 3) |
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223 #define CPU_FEATURE_DIV (1 << 4) |
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224 #define CPU_FEATURE_FLUSH (1 << 5) |
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225 #define CPU_FEATURE_FSQRT (1 << 6) |
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226 #define CPU_FEATURE_FMUL (1 << 7) |
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227 #define CPU_FEATURE_VIS1 (1 << 8) |
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228 #define CPU_FEATURE_VIS2 (1 << 9) |
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229 #define CPU_FEATURE_FSMULD (1 << 10) |
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230 #define CPU_FEATURE_HYPV (1 << 11) |
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231 #define CPU_FEATURE_CMT (1 << 12) |
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232 #define CPU_FEATURE_GL (1 << 13) |
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233 #ifndef TARGET_SPARC64 |
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234 #define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | \ |
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235 CPU_FEATURE_MUL | CPU_FEATURE_DIV | \ |
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236 CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \ |
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237 CPU_FEATURE_FMUL | CPU_FEATURE_FSMULD) |
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238 #else |
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239 #define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | \ |
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240 CPU_FEATURE_MUL | CPU_FEATURE_DIV | \ |
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241 CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \ |
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242 CPU_FEATURE_FMUL | CPU_FEATURE_VIS1 | \ |
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243 CPU_FEATURE_VIS2 | CPU_FEATURE_FSMULD) |
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244 enum { |
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245 mmu_us_12, // Ultrasparc < III (64 entry TLB) |
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246 mmu_us_3, // Ultrasparc III (512 entry TLB) |
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247 mmu_us_4, // Ultrasparc IV (several TLBs, 32 and 256MB pages) |
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248 mmu_sun4v, // T1, T2 |
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249 }; |
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250 #endif |
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251 |
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252 typedef struct CPUSPARCState { |
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253 target_ulong gregs[8]; /* general registers */ |
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254 target_ulong *regwptr; /* pointer to current register window */ |
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255 target_ulong pc; /* program counter */ |
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256 target_ulong npc; /* next program counter */ |
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257 target_ulong y; /* multiply/divide register */ |
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258 |
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259 /* emulator internal flags handling */ |
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260 target_ulong cc_src, cc_src2; |
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261 target_ulong cc_dst; |
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262 |
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263 target_ulong t0, t1; /* temporaries live across basic blocks */ |
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264 target_ulong cond; /* conditional branch result (XXX: save it in a |
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265 temporary register when possible) */ |
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266 |
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267 uint32_t psr; /* processor state register */ |
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268 target_ulong fsr; /* FPU state register */ |
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269 float32 fpr[TARGET_FPREGS]; /* floating point registers */ |
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270 uint32_t cwp; /* index of current register window (extracted |
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271 from PSR) */ |
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272 uint32_t wim; /* window invalid mask */ |
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273 target_ulong tbr; /* trap base register */ |
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274 int psrs; /* supervisor mode (extracted from PSR) */ |
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275 int psrps; /* previous supervisor mode */ |
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276 int psret; /* enable traps */ |
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277 uint32_t psrpil; /* interrupt blocking level */ |
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278 uint32_t pil_in; /* incoming interrupt level bitmap */ |
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279 int psref; /* enable fpu */ |
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280 target_ulong version; |
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281 int interrupt_index; |
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282 uint32_t nwindows; |
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283 /* NOTE: we allow 8 more registers to handle wrapping */ |
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284 target_ulong regbase[MAX_NWINDOWS * 16 + 8]; |
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285 |
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286 CPU_COMMON |
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287 |
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288 /* MMU regs */ |
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289 #if defined(TARGET_SPARC64) |
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290 uint64_t lsu; |
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291 #define DMMU_E 0x8 |
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292 #define IMMU_E 0x4 |
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293 uint64_t immuregs[16]; |
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294 uint64_t dmmuregs[16]; |
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295 uint64_t itlb_tag[64]; |
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296 uint64_t itlb_tte[64]; |
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297 uint64_t dtlb_tag[64]; |
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298 uint64_t dtlb_tte[64]; |
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299 uint32_t mmu_version; |
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300 #else |
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301 uint32_t mmuregs[32]; |
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302 uint64_t mxccdata[4]; |
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303 uint64_t mxccregs[8]; |
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304 uint64_t mmubpregs[4]; |
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305 uint64_t prom_addr; |
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306 #endif |
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307 /* temporary float registers */ |
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308 float64 dt0, dt1; |
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309 float128 qt0, qt1; |
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310 float_status fp_status; |
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311 #if defined(TARGET_SPARC64) |
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312 #define MAXTL_MAX 8 |
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313 #define MAXTL_MASK (MAXTL_MAX - 1) |
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314 trap_state *tsptr; |
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315 trap_state ts[MAXTL_MAX]; |
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316 uint32_t xcc; /* Extended integer condition codes */ |
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317 uint32_t asi; |
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318 uint32_t pstate; |
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319 uint32_t tl; |
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320 uint32_t maxtl; |
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321 uint32_t cansave, canrestore, otherwin, wstate, cleanwin; |
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322 uint64_t agregs[8]; /* alternate general registers */ |
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323 uint64_t bgregs[8]; /* backup for normal global registers */ |
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324 uint64_t igregs[8]; /* interrupt general registers */ |
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325 uint64_t mgregs[8]; /* mmu general registers */ |
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326 uint64_t fprs; |
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327 uint64_t tick_cmpr, stick_cmpr; |
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328 void *tick, *stick; |
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329 uint64_t gsr; |
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330 uint32_t gl; // UA2005 |
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331 /* UA 2005 hyperprivileged registers */ |
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332 uint64_t hpstate, htstate[MAXTL_MAX], hintp, htba, hver, hstick_cmpr, ssr; |
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333 void *hstick; // UA 2005 |
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334 uint32_t softint; |
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335 #define SOFTINT_TIMER 1 |
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336 #define SOFTINT_STIMER (1 << 16) |
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337 #endif |
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338 sparc_def_t *def; |
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339 } CPUSPARCState; |
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340 |
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341 /* helper.c */ |
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342 CPUSPARCState *cpu_sparc_init(const char *cpu_model); |
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343 void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu); |
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344 void sparc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, |
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345 ...)); |
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346 void cpu_lock(void); |
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347 void cpu_unlock(void); |
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348 int cpu_sparc_handle_mmu_fault(CPUSPARCState *env1, target_ulong address, int rw, |
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349 int mmu_idx, int is_softmmu); |
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350 target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev); |
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351 void dump_mmu(CPUSPARCState *env); |
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352 |
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353 /* translate.c */ |
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354 void gen_intermediate_code_init(CPUSPARCState *env); |
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355 |
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356 /* cpu-exec.c */ |
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357 int cpu_sparc_exec(CPUSPARCState *s); |
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358 |
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359 #define GET_PSR(env) (env->version | (env->psr & PSR_ICC) | \ |
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360 (env->psref? PSR_EF : 0) | \ |
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361 (env->psrpil << 8) | \ |
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362 (env->psrs? PSR_S : 0) | \ |
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363 (env->psrps? PSR_PS : 0) | \ |
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364 (env->psret? PSR_ET : 0) | env->cwp) |
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365 |
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366 #ifndef NO_CPU_IO_DEFS |
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367 static inline void memcpy32(target_ulong *dst, const target_ulong *src) |
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368 { |
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369 dst[0] = src[0]; |
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370 dst[1] = src[1]; |
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371 dst[2] = src[2]; |
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372 dst[3] = src[3]; |
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373 dst[4] = src[4]; |
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374 dst[5] = src[5]; |
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375 dst[6] = src[6]; |
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376 dst[7] = src[7]; |
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377 } |
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378 |
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379 static inline void cpu_set_cwp(CPUSPARCState *env1, int new_cwp) |
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380 { |
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381 /* put the modified wrap registers at their proper location */ |
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382 if (env1->cwp == env1->nwindows - 1) |
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383 memcpy32(env1->regbase, env1->regbase + env1->nwindows * 16); |
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384 env1->cwp = new_cwp; |
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385 /* put the wrap registers at their temporary location */ |
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386 if (new_cwp == env1->nwindows - 1) |
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387 memcpy32(env1->regbase + env1->nwindows * 16, env1->regbase); |
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388 env1->regwptr = env1->regbase + (new_cwp * 16); |
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389 } |
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390 |
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391 static inline int cpu_cwp_inc(CPUSPARCState *env1, int cwp) |
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392 { |
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393 if (unlikely(cwp >= env1->nwindows)) |
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394 cwp -= env1->nwindows; |
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395 return cwp; |
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396 } |
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397 |
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398 static inline int cpu_cwp_dec(CPUSPARCState *env1, int cwp) |
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399 { |
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400 if (unlikely(cwp < 0)) |
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401 cwp += env1->nwindows; |
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402 return cwp; |
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403 } |
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404 #endif |
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405 |
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406 #define PUT_PSR(env, val) do { int _tmp = val; \ |
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407 env->psr = _tmp & PSR_ICC; \ |
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408 env->psref = (_tmp & PSR_EF)? 1 : 0; \ |
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409 env->psrpil = (_tmp & PSR_PIL) >> 8; \ |
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410 env->psrs = (_tmp & PSR_S)? 1 : 0; \ |
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411 env->psrps = (_tmp & PSR_PS)? 1 : 0; \ |
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412 env->psret = (_tmp & PSR_ET)? 1 : 0; \ |
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413 cpu_set_cwp(env, _tmp & PSR_CWP); \ |
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414 } while (0) |
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415 |
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416 #ifdef TARGET_SPARC64 |
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417 #define GET_CCR(env) (((env->xcc >> 20) << 4) | ((env->psr & PSR_ICC) >> 20)) |
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418 #define PUT_CCR(env, val) do { int _tmp = val; \ |
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419 env->xcc = (_tmp >> 4) << 20; \ |
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420 env->psr = (_tmp & 0xf) << 20; \ |
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421 } while (0) |
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422 #define GET_CWP64(env) (env->nwindows - 1 - (env)->cwp) |
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423 |
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424 #ifndef NO_CPU_IO_DEFS |
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425 static inline void PUT_CWP64(CPUSPARCState *env1, int cwp) |
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426 { |
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427 if (unlikely(cwp >= env1->nwindows || cwp < 0)) |
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428 cwp = 0; |
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429 cpu_set_cwp(env1, env1->nwindows - 1 - cwp); |
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430 } |
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431 #endif |
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432 #endif |
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433 |
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434 /* cpu-exec.c */ |
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435 void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, |
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436 int is_asi, int size); |
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437 int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc); |
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438 |
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439 #define CPUState CPUSPARCState |
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440 #define cpu_init cpu_sparc_init |
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441 #define cpu_exec cpu_sparc_exec |
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442 #define cpu_gen_code cpu_sparc_gen_code |
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443 #define cpu_signal_handler cpu_sparc_signal_handler |
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444 #define cpu_list sparc_cpu_list |
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445 |
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446 #define CPU_SAVE_VERSION 5 |
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447 |
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448 /* MMU modes definitions */ |
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449 #define MMU_MODE0_SUFFIX _user |
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450 #define MMU_MODE1_SUFFIX _kernel |
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451 #ifdef TARGET_SPARC64 |
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452 #define MMU_MODE2_SUFFIX _hypv |
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453 #endif |
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454 #define MMU_USER_IDX 0 |
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455 #define MMU_KERNEL_IDX 1 |
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456 #define MMU_HYPV_IDX 2 |
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457 |
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458 static inline int cpu_mmu_index(CPUState *env1) |
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459 { |
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460 #if defined(CONFIG_USER_ONLY) |
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461 return MMU_USER_IDX; |
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462 #elif !defined(TARGET_SPARC64) |
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463 return env1->psrs; |
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464 #else |
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465 if (!env1->psrs) |
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466 return MMU_USER_IDX; |
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467 else if ((env1->hpstate & HS_PRIV) == 0) |
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468 return MMU_KERNEL_IDX; |
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469 else |
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470 return MMU_HYPV_IDX; |
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471 #endif |
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472 } |
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473 |
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474 static inline int cpu_fpu_enabled(CPUState *env1) |
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475 { |
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476 #if defined(CONFIG_USER_ONLY) |
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477 return 1; |
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478 #elif !defined(TARGET_SPARC64) |
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479 return env1->psref; |
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480 #else |
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481 return ((env1->pstate & PS_PEF) != 0) && ((env1->fprs & FPRS_FEF) != 0); |
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482 #endif |
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483 } |
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484 |
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485 #if defined(CONFIG_USER_ONLY) |
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486 static inline void cpu_clone_regs(CPUState *env, target_ulong newsp) |
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487 { |
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488 if (newsp) |
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489 env->regwptr[22] = newsp; |
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490 env->regwptr[0] = 0; |
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491 /* FIXME: Do we also need to clear CF? */ |
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492 /* XXXXX */ |
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493 printf ("HELPME: %s:%d\n", __FILE__, __LINE__); |
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494 } |
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495 #endif |
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496 |
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497 #include "cpu-all.h" |
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498 #include "exec-all.h" |
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499 |
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500 /* sum4m.c, sun4u.c */ |
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501 void cpu_check_irqs(CPUSPARCState *env); |
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502 |
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503 #ifdef TARGET_SPARC64 |
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504 /* sun4u.c */ |
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505 void cpu_tick_set_count(void *opaque, uint64_t count); |
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506 uint64_t cpu_tick_get_count(void *opaque); |
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507 void cpu_tick_set_limit(void *opaque, uint64_t limit); |
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508 #endif |
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509 |
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510 static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb) |
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511 { |
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512 env->pc = tb->pc; |
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513 env->npc = tb->cs_base; |
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514 } |
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515 |
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516 static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, |
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517 target_ulong *cs_base, int *flags) |
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518 { |
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519 *pc = env->pc; |
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520 *cs_base = env->npc; |
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521 #ifdef TARGET_SPARC64 |
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522 // AM . Combined FPU enable bits . PRIV . DMMU enabled . IMMU enabled |
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523 *flags = ((env->pstate & PS_AM) << 2) |
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524 | (((env->pstate & PS_PEF) >> 1) | ((env->fprs & FPRS_FEF) << 2)) |
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525 | (env->pstate & PS_PRIV) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2); |
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526 #else |
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527 // FPU enable . Supervisor |
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528 *flags = (env->psref << 4) | env->psrs; |
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529 #endif |
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530 } |
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531 |
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532 #endif |