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1 ;/* |
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2 ;* Copyright (c) 2009 Nokia Corporation and/or its subsidiary(-ies). |
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3 ;* All rights reserved. |
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4 ;* This component and the accompanying materials are made available |
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5 ;* under the terms of the License "Eclipse Public License v1.0" |
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6 ;* which accompanies this distribution, and is available |
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7 ;* at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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8 ;* |
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9 ;* Initial Contributors: |
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10 ;* Nokia Corporation - initial contribution. |
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11 ;* |
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12 ;* Contributors: |
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13 ;* |
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14 ;* Description: |
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15 ;* |
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16 ;*/ |
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17 |
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18 GBLL __VARIANT_S__ ; indicates that this is platform-specific code |
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19 GBLL __SYBORG_S__ ; indicates which source file this is |
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20 |
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21 INCLUDE bootcpu.inc |
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22 INCLUDE syborg.inc |
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23 ; |
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24 ;******************************************************************************* |
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25 ; |
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26 IMPORT ResetEntry |
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27 ; |
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28 ;******************************************************************************* |
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29 ; |
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30 AREA |Boot$$Code|, CODE, READONLY, ALIGN=6 |
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31 ; |
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32 ;******************************************************************************* |
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33 ; Initialise Hardware |
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34 ; Determine the hardware configuration |
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35 ; Determine the reset reason. If it is wakeup from a low power mode, perform |
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36 ; whatever reentry sequence is required and jump back to the kernel. |
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37 ; Set up the memory controller so that at least some RAM is available |
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38 ; Set R10 to point to the super page or to a temporary version of the super page |
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39 ; with at least the following fields valid: |
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40 ; iBootTable, iCodeBase, iActiveVariant, iCpuId |
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41 ; Initialise the debug serial port |
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42 ; |
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43 ; Enter with: |
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44 ; R12 points to TRomHeader |
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45 ; NO STACK |
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46 ; R14 = return address (as usual) |
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47 ; |
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48 ; All registers may be modified by this call |
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49 ;******************************************************************************* |
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50 EXPORT InitialiseHardware |
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51 InitialiseHardware ROUT |
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52 mov r13, lr ; save return address |
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53 |
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54 adrl r1, ParameterTable ; pass address of parameter table |
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55 bl InitCpu ; initialise CPU/MMU registers |
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56 |
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57 ;******************************************************************************* |
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58 ; DoInitialise Hardware |
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59 ; Initialise CPU registers |
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60 ; Determine the hardware configuration |
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61 ; Determine the reset reason. If it is wakeup from a low power mode, perform |
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62 ; whatever reentry sequence is required and jump back to the kernel. |
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63 ; Set up the memory controller so that at least some RAM is available |
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64 ; Set R10 to point to the super page or to a temporary version of the super page |
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65 ; with at least the following fields valid: |
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66 ; iBootTable, iCodeBase, iActiveVariant, iCpuId |
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67 ; In debug builds initialise the debug serial port |
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68 ; |
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69 ; Enter with: |
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70 ; R12 points to TRomHeader |
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71 ; NO STACK |
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72 ; R13 = return address (as usual) |
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73 ; |
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74 ; All registers may be modified by this call |
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75 ;******************************************************************************* |
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76 DoInitialiseHardware ROUT |
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77 |
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78 ; Hardware memory size is 128MB - 32MB reserved for bootloader |
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79 mov r4, #KHwRamSizeMb |
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80 |
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81 bl InitDebugPort |
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82 |
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83 ldr r7, =CFG_HWVD ; variant number |
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84 |
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85 lsl r10, r4, #20 ; R10 = top of RAM |
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86 sub r10, #0x2000 ; put super page at end for now |
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87 |
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88 ; Set up the required super page values |
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89 str r7, [r10, #SSuperPageBase_iActiveVariant] |
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90 |
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91 mov r1, #0 |
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92 str r1, [r10, #SSuperPageBase_iHwStartupReason] ; reset reason (from hardware) |
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93 |
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94 add r1, r10, #CpuPageOffset |
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95 str r1, [r10, #SSuperPageBase_iMachineData] |
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96 bl GetBootTableAddress |
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97 str r0, [r10, #SSuperPageBase_iBootTable] ; set the boot function table |
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98 str r12, [r10, #SSuperPageBase_iCodeBase] ; set the base address of bootstrap code |
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99 mrc p15, 0, r0, c0, c0, 0 ; read CPU ID from CP15 (remove if no CP15) |
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100 str r0, [r10, #SSuperPageBase_iCpuId] |
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101 |
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102 mov r0, r13 |
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103 add sp, r10, #CpuBootStackTop ; set up a boot stack |
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104 push {r0} ; save return address |
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105 bl DoInitHw2 ; any extra CPU-dependent stuff |
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106 |
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107 ldr r7, [r10, #SSuperPageBase_iActiveVariant] |
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108 DWORD r7, "ActiveVariant" |
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109 |
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110 pop {pc} ; return |
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111 |
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112 ;******************************************************************************* |
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113 DoInitHw2 ROUT |
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114 mrc p15, 0, r0, c0, c0, 0 |
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115 DWORD r0, "MMUID" |
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116 mrc p15, 0, r0, c0, c0, 1 |
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117 DWORD r0, "CacheType" |
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118 mrc p15, 0, r0, c0, c0, 2 |
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119 DWORD r0, "TCMType" |
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120 mrc p15, 0, r0, c0, c0, 3 |
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121 DWORD r0, "TLBType" |
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122 bx lr |
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123 |
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124 ;******************************************************************************* |
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125 ; Get a pointer to the list of hardware banks |
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126 ; |
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127 ; The pointer returned should point to a list of hardware banks declared with |
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128 ; the HW_MAPPING and/or HW_MAPPING_EXT macros. A zero word terminates the list. |
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129 ; For the direct memory model, all hardware on the system should be mapped here |
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130 ; and the mapping will set linear address = physical address. |
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131 ; For the moving or multiple model, only the hardware required to boot the kernel |
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132 ; and do debug tracing needs to be mapped here. The linear addresses used will |
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133 ; start at KPrimaryIOBase and step up as required with the order of banks in |
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134 ; the list being maintained in the linear addresses used. |
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135 ; |
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136 ; HW_MAPPING PB, SIZE, MULT |
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137 ; This declares a block of I/O with physical base PB and address range SIZE |
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138 ; blocks each of which has a size determined by MULT. The page size used for |
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139 ; the mapping is determined by MULT. The linear address base of the mapping |
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140 ; will be the next free linear address rounded up to the size specified by |
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141 ; MULT. |
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142 ; The permissions used for the mapping are the standard I/O permissions (BTP_Hw). |
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143 ; |
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144 ; HW_MAPPING_EXT PB, SIZE, MULT |
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145 ; This declares a block of I/O with physical base PB and address range SIZE |
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146 ; blocks each of which has a size determined by MULT. The page size used for |
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147 ; the mapping is determined by MULT. The linear address base of the mapping |
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148 ; will be the next free linear address rounded up to the size specified by |
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149 ; MULT. |
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150 ; The permissions used for the mapping are determined by a BTP_ENTRY macro |
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151 ; immediately following this macro in the HW bank list or by a DCD directive |
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152 ; specifying a different standard permission type. |
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153 ; |
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154 ; Configurations without an MMU need not implement this function. |
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155 ; |
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156 ; Enter with : |
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157 ; R10 points to super page |
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158 ; R12 points to ROM header |
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159 ; R13 points to valid stack |
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160 ; |
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161 ; Leave with : |
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162 ; R0 = pointer |
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163 ; Nothing else modified |
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164 ;******************************************************************************* |
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165 EXPORT GetHwBanks |
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166 GetHwBanks ROUT |
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167 adr r0, %FT1 |
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168 bx lr |
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169 1 |
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170 HW_MAPPING KHwBaseSic, 1, HW_MULT_4K |
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171 HW_MAPPING KHwBaseRtc, 1, HW_MULT_4K |
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172 HW_MAPPING KHwBaseTimer, 1, HW_MULT_4K |
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173 HW_MAPPING KHwBaseKmiKeyboard, 1, HW_MULT_4K |
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174 HW_MAPPING KHwBaseKmiPointer, 1, HW_MULT_4K |
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175 HW_MAPPING KHwBaseClcd, 1, HW_MULT_4K |
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176 HW_MAPPING KHwBaseUart0, 1, HW_MULT_4K |
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177 HW_MAPPING KHwBaseUart1, 1, HW_MULT_4K |
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178 HW_MAPPING KHwBaseUart2, 1, HW_MULT_4K |
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179 HW_MAPPING KHwBaseUart3, 1, HW_MULT_4K |
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180 HW_MAPPING KHwBaseHostFs, 1, HW_MULT_4K |
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181 HW_MAPPING KHwBaseSnap, 1, HW_MULT_4K |
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182 HW_MAPPING KHwBaseNet, 1, HW_MULT_4K |
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183 HW_MAPPING KHwBaseNand, 1, HW_MULT_4K |
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184 HW_MAPPING KHwBaseAudio, 1, HW_MULT_4K |
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185 HW_MAPPING KHwBasePlatform, 8, HW_MULT_4K |
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186 |
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187 DCD 0 ; terminator |
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188 |
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189 ;******************************************************************************* |
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190 ; Notify an unrecoverable error during the boot process |
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191 ; |
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192 ; Enter with: |
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193 ; R14 = address at which fault detected |
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194 ; |
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195 ; Don't return |
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196 ;******************************************************************************* |
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197 EXPORT Fault |
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198 Fault ROUT |
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199 b BasicFaultHandler ; generic handler dumps registers via debug |
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200 ; serial port |
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201 |
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202 ;******************************************************************************* |
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203 ; Reboot the system |
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204 ; |
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205 ; Enter with: |
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206 ; R0 = reboot reason code |
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207 ; |
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208 ; Don't return (of course) |
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209 ;******************************************************************************* |
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210 ALIGN 32, 0 |
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211 EXPORT RestartEntry |
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212 RestartEntry ROUT |
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213 |
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214 ; Save R0 parameter in HW dependent register which is preserved over reset |
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215 ; Put HW specific code here to reset system |
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216 GETCPSR r1 |
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217 orr r1, #0xC0 |
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218 SETCPSR r1 ; disable interrupts |
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219 |
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220 ldr r10, =KSuperPageLinAddr |
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221 adr r0, Run_Physical |
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222 bl RomLinearToPhysical ; physical address in r0 |
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223 |
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224 ; Disable MMU |
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225 mrc p15, 0, r1, c1, c0, 0 ; get MMUCR |
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226 bic r1, #MMUCR_M ; clear M bit |
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227 mcr p15, 0, r1, c1, c0, 0 ; set MMUCR |
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228 bx r0 ; jump to the physical address |
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229 |
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230 ; Now running from physical address |
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231 |
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232 Run_Physical |
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233 mov r3, #KHwNorFlashBaseAddr ; r3 = NOR flash image base |
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234 |
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235 ; Jump to the NOR flash image |
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236 bx r3 |
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237 |
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238 ;******************************************************************************* |
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239 ; Get a pointer to the list of RAM banks |
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240 ; |
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241 ; The pointer returned should point to a list of {BASE; MAXSIZE;} pairs, where |
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242 ; BASE is the physical base address of the bank and MAXSIZE is the maximum |
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243 ; amount of RAM which may be present in that bank. MAXSIZE should be a power of |
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244 ; 2 and BASE should be a multiple of MAXSIZE. The generic code will examine the |
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245 ; specified range of addresses and determine the actual amount of RAM if any |
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246 ; present in the bank. The list is terminated by an entry with zero size. |
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247 ; |
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248 ; The pointer returned will usually be to constant data, but could equally well |
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249 ; point to RAM if dynamic determination of the list is required. |
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250 ; |
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251 ; Enter with : |
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252 ; R10 points to super page |
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253 ; R12 points to ROM header |
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254 ; R13 points to valid stack |
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255 ; |
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256 ; Leave with : |
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257 ; R0 = pointer |
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258 ; Nothing else modified |
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259 ;******************************************************************************* |
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260 EXPORT GetRamBanks |
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261 GetRamBanks ROUT |
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262 push {r1-r3,lr} |
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263 mov r0, #KHwRamSizeMb |
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264 lsl r2, r0, #20 ; R2 = RAM size in bytes |
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265 mov r1, #KHwRamBaseAddr ; R1 = base address of usable RAM area |
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266 sub r2, r1 ; R2 = size of usable RAM area |
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267 orr r1, #RAM_VERBATIM ; prevent testing (overlay would break it) |
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268 mov r3, #0 |
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269 mov lr, #0 ; terminator |
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270 add r0, r10, #CpuPageOffset ; |
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271 stm r0, {r1-r3,lr} ; store single bank descriptor and terminator |
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272 pop {r1-r3,pc} |
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273 |
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274 ;******************************************************************************* |
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275 ; Get a pointer to the list of ROM banks |
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276 ; |
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277 ; The pointer returned should point to a list of entries of SRomBank structures, |
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278 ; usually declared with the ROM_BANK macro. |
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279 ; The list is terminated by a zero size entry (four zero words) |
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280 ; |
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281 ; ROM_BANK PB, SIZE, LB, W, T, RS, SS |
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282 ; PB = physical base address of bank |
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283 ; SIZE = size of bank |
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284 ; LB = linear base if override required - usually set this to 0 |
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285 ; W = bus width (ROM_WIDTH_8, ROM_WIDTH_16, ROM_WIDTH_32) |
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286 ; T = type (see TRomType enum in kernboot.h) |
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287 ; RS = random speed |
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288 ; SS = sequential speed |
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289 ; |
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290 ; Only PB, SIZE, LB are used by the rest of the bootstrap. |
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291 ; The information given here can be modified by the SetupRomBank call, if |
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292 ; dynamic detection and sizing of ROMs is required. |
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293 ; |
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294 ; Enter with : |
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295 ; R10 points to super page |
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296 ; R12 points to ROM header |
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297 ; R13 points to valid stack |
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298 ; |
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299 ; Leave with : |
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300 ; R0 = pointer |
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301 ; Nothing else modified |
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302 ;******************************************************************************* |
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303 EXPORT GetRomBanks |
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304 GetRomBanks ROUT |
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305 adr r0, RomBanksFlashTable ; NOR flash |
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306 bx lr |
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307 |
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308 RomBanksFlashTable |
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309 ROM_BANK KHwNorFlashBaseAddr, KHwNorFlashCodeSize, 0, ROM_WIDTH_32, ERomTypeXIPFlash, 0, 0 |
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310 DCD 0,0,0,0 ; terminator |
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311 |
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312 ;******************************************************************************* |
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313 ; Set up RAM bank |
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314 ; |
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315 ; Do any additional RAM controller initialisation for each RAM bank which wasn't |
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316 ; done by InitialiseHardware. |
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317 ; Called twice for each RAM bank :- |
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318 ; First with R3 = 0xFFFFFFFF before bank has been probed |
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319 ; Then, if RAM is present, with R3 indicating validity of each byte lane, ie |
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320 ; R3 bit 0=1 if D0-7 are valid, bit1=1 if D8-15 are valid etc. |
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321 ; For each call R1 specifies the bank physical base address. |
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322 ; |
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323 ; Enter with : |
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324 ; R10 points to super page |
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325 ; R12 points to ROM header |
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326 ; R13 points to stack |
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327 ; R1 = physical base address of bank |
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328 ; R3 = width (bottom 4 bits indicate validity of byte lanes) |
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329 ; 0xffffffff = preliminary initialise |
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330 ; |
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331 ; Leave with : |
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332 ; No registers modified |
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333 ;******************************************************************************* |
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334 EXPORT SetupRamBank |
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335 SetupRamBank ROUT |
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336 bx lr |
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337 |
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338 ;******************************************************************************* |
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339 ; Set up ROM bank |
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340 ; |
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341 ; Do any required autodetection and autosizing of ROMs and any additional memory |
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342 ; controller initialisation for each ROM bank which wasn't done by |
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343 ; InitialiseHardware. |
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344 ; |
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345 ; The first time this function is called R11=0 and R0 points to the list of |
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346 ; ROM banks returned by the BTF_RomBanks call. This allows any preliminary setup |
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347 ; before autodetection begins. |
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348 ; |
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349 ; This function is subsequently called once for each ROM bank with R11 pointing |
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350 ; to the current information held about that ROM bank (SRomBank structure). |
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351 ; The structure pointed to by R11 should be updated with the size and width |
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352 ; determined. The size should be set to zero if there is no ROM present in the |
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353 ; bank. |
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354 ; |
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355 ; Enter with : |
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356 ; R10 points to super page |
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357 ; R12 points to ROM header |
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358 ; R13 points to stack |
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359 ; R11 points to SRomBank info for this bank |
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360 ; R11 = 0 for preliminary initialise (all banks) |
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361 ; |
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362 ; Leave with : |
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363 ; Update SRomBank info with detected size/width |
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364 ; Set the size field to 0 if the ROM bank is absent |
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365 ; Can modify R0-R4 but not other registers |
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366 ; |
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367 ;******************************************************************************* |
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368 EXPORT SetupRomBank |
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369 SetupRomBank ROUT ; only get here if running from ROM |
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370 cmp r11, #0 |
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371 bxeq lr ; don't do anything for preliminary |
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372 ldm r11, {r0,r1} ; r0 = base, r1 = size |
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373 lsr r0, pc, #20 |
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374 lsl r0, #20 ; r0 = image base |
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375 ldr r1, [r12, #TRomHeader_iRomSize] ; r1 = size of ROM block |
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376 stm r11, {r0,r1} |
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377 bx lr |
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378 |
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379 ;******************************************************************************* |
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380 ; Reserve physical memory |
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381 ; |
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382 ; Reserve any physical RAM needed for platform-specific purposes before the |
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383 ; bootstrap begins allocating RAM for page tables/kernel data etc. |
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384 ; |
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385 ; There are two methods for this: |
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386 ; 1. The function ExciseRamArea may be used. This will remove a contiguous |
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387 ; region of physical RAM from the RAM bank list. That region will never |
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388 ; again be identified as RAM. |
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389 ; 2. A list of excluded physical address ranges may be written at [R11]. |
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390 ; This should be a list of (base,size) pairs terminated by a (0,0) entry. |
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391 ; This RAM will still be identified as RAM by the kernel but will not |
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392 ; be allocated by the bootstrap and will subsequently be marked as |
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393 ; allocated by the kernel immediately after boot. |
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394 ; |
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395 ; Enter with : |
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396 ; R10 points to super page |
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397 ; R11 indicates where preallocated RAM list should be written. |
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398 ; R12 points to ROM header |
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399 ; R13 points to stack |
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400 ; |
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401 ; Leave with : |
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402 ; R0-R3 may be modified. Other registers should be preserved. |
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403 ;******************************************************************************* |
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404 EXPORT ReservePhysicalMemory |
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405 ReservePhysicalMemory ROUT |
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406 bx lr |
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407 |
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408 ;******************************************************************************* |
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409 ; Do final platform-specific initialisation before booting the kernel |
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410 ; |
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411 ; Typical uses for this call would be: |
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412 ; 1. Mapping cache flushing areas |
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413 ; 2. Setting up pointers to routines in the bootstrap which are used by |
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414 ; the variant or drivers (eg idle code). |
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415 ; |
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416 ; Enter with : |
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417 ; R10 points to super page |
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418 ; R11 points to TRomImageHeader for the kernel |
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419 ; R12 points to ROM header |
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420 ; R13 points to stack |
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421 ; |
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422 ; Leave with : |
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423 ; R0-R9 may be modified. Other registers should be preserved. |
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424 ; |
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425 ;******************************************************************************* |
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426 EXPORT FinalInitialise |
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427 FinalInitialise ROUT |
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428 bx lr |
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429 |
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430 ;******************************************************************************* |
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431 ; Debug port write routine associated with debug port in the super page |
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432 ; Enter with : |
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433 ; R0 character to be written |
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434 ; R12 points to rom header |
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435 ; R13 points to valid stack |
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436 ; |
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437 ; Leave with : |
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438 ; nothing modified |
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439 ;******************************************************************************* |
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440 EXPORT DoWriteC |
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441 DoWriteC ROUT |
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442 IF CFG_DebugBootRom |
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443 push {r1,lr} |
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444 bl GetDebugPortBase ; r1 = base address of UART registers |
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445 |
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446 str r0, [r1, #4] ; Store to data register |
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447 |
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448 pop {r1,pc} |
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449 ELSE |
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450 bx lr |
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451 ENDIF |
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452 |
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453 ;******************************************************************************* |
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454 ; Initialise the debug port |
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455 ; |
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456 ; Enter with : |
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457 ; R12 points to ROM header |
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458 ; There is no valid stack |
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459 ; |
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460 ; Leave with : |
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461 ; R0-R2 modified |
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462 ; Other registers unmodified |
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463 ;******************************************************************************* |
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464 InitDebugPort ROUT |
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465 GET_ADDRESS r1, KHwBaseUart0, KHwLinBaseUart0 |
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466 ldr r0,[r1, #0] |
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467 bx lr |
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468 |
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469 ;******************************************************************************* |
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470 ; Get the base address of the debug UART |
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471 ; |
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472 ; Enter with : |
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473 ; R12 points to ROM header |
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474 ; There may be no stack |
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475 ; |
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476 ; Leave with : |
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477 ; R1 = base address of port, 0 for JTAG |
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478 ; Z flag set for JTAG, clear for non-JTAG |
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479 ; No other registers modified |
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480 ;******************************************************************************* |
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481 GetDebugPortBase ROUT |
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482 ldr r1, [r12, #TRomHeader_iDebugPort] |
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483 cmp r1, #42 ; JTAG? |
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484 movseq r1, #0 |
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485 bxeq lr ; yes - return 0 and set Z |
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486 cmp r1, #1 |
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487 blo GetUartPort0 |
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488 beq GetUartPort1 |
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489 cmp r1, #3 |
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490 blo GetUartPort2 |
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491 beq GetUartPort3 |
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492 GetUartPort0 |
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493 GET_ADDRESS r1, KHwBaseUart0, KHwLinBaseUart0 |
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494 movs r1, r1 ; clear Z |
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495 bx lr |
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496 |
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497 GetUartPort1 |
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498 GET_ADDRESS r1, KHwBaseUart1, KHwLinBaseUart1 |
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499 movs r1, r1 ; clear Z |
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500 bx lr |
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501 |
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502 GetUartPort2 |
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503 GET_ADDRESS r1, KHwBaseUart2, KHwLinBaseUart2 |
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504 movs r1, r1 ; clear Z |
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505 bx lr |
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506 |
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507 GetUartPort3 |
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508 GET_ADDRESS r1, KHwBaseUart3, KHwLinBaseUart3 |
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509 movs r1, r1 ; clear Z |
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510 bx lr |
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511 |
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512 ;******************************************************************************* |
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513 ; Return parameter specified by R0 (see TBootParam enum) |
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514 ; |
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515 ; Enter with : |
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516 ; R0 = parameter number |
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517 ; |
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518 ; Leave with : |
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519 ; If parameter value is supplied, R0 = value and N flag clear |
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520 ; If parameter value is not supplied, N flag set. In this case the |
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521 ; parameter may be defaulted or the system may fault. |
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522 ; R0, R1 modified. No other registers modified. |
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523 ; |
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524 ;******************************************************************************* |
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525 GetParameters ROUT |
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526 adr r1, ParameterTable |
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527 b FindParameter |
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528 |
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529 ParameterTable |
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530 DCD -1 ; terminator |
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531 |
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532 ;******************************************************************************* |
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533 ; BOOT FUNCTION TABLE |
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534 ;******************************************************************************* |
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535 GetBootTableAddress ROUT |
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536 adr r0, SyborgBootTable |
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537 bx lr |
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538 |
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539 SyborgBootTable |
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540 DCD DoWriteC ; output a debug character |
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541 DCD GetRamBanks ; get list of RAM banks |
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542 DCD SetupRamBank ; set up a RAM bank |
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543 DCD GetRomBanks ; get list of ROM banks |
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544 DCD SetupRomBank ; set up a ROM bank |
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545 DCD GetHwBanks ; get list of HW banks |
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546 DCD ReservePhysicalMemory ; reserve physical RAM if required |
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547 DCD GetParameters ; get addresses for direct memory model |
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548 DCD FinalInitialise ; Final initialisation before booting the kernel |
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549 DCD HandleAllocRequest ; allocate memory (usually in generic code) |
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550 DCD GetPdeValue ; usually in generic code |
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551 DCD GetPteValue ; usually in generic code |
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552 DCD PageTableUpdate ; usually in generic code |
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553 DCD EnableMmu ; Enable the MMU (usually in generic code) |
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554 |
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555 ; These entries specify the standard MMU permissions for various areas |
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556 |
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557 IF CFG_MMMultiple |
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558 ; IF CFG_MMFlexible |
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559 IF CFG_ARMV7 |
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560 BTP_ENTRY CLIENT_DOMAIN, PERM_RORO, MEMORY_FULLY_CACHED, 1, 1, 0, 0 ; ROM |
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561 BTP_ENTRY CLIENT_DOMAIN, PERM_RWNO, MEMORY_FULLY_CACHED, 0, 1, 0, 0 ; kernel data/stack/heap |
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562 BTP_ENTRY CLIENT_DOMAIN, PERM_RWNO, MEMORY_FULLY_CACHED, 0, 1, 0, 0 ; super page/CPU page |
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563 BTP_ENTRY CLIENT_DOMAIN, PERM_RWNO, MEMORY_FULLY_CACHED, 0, 1, 0, 0 ; page directory/tables |
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564 BTP_ENTRY CLIENT_DOMAIN, PERM_RONO, MEMORY_FULLY_CACHED, 1, 1, 0, 0 ; exception vectors |
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565 BTP_ENTRY CLIENT_DOMAIN, PERM_RWNO, MEMORY_STRONGLY_ORDERED, 0, 1, 0, 0 ; hardware registers |
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566 DCD 0 ; unused (minicache flush) |
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567 DCD 0 ; unused (maincache flush) |
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568 BTP_ENTRY CLIENT_DOMAIN, PERM_RWNO, MEMORY_FULLY_CACHED, 0, 1, 0, 0 ; page table info |
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569 BTP_ENTRY CLIENT_DOMAIN, PERM_RWRW, MEMORY_FULLY_CACHED, 1, 1, 0, 0 ; user RAM |
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570 BTP_ENTRY CLIENT_DOMAIN, PERM_RONO, MEMORY_STRONGLY_ORDERED, 1, 1, 0, 0 ; temporary identity mapping |
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571 BTP_ENTRY CLIENT_DOMAIN, UNC_PERM, MEMORY_STRONGLY_ORDERED, 0, 1, 0, 0 ; uncached |
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572 ENDIF |
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573 IF CFG_ARMV6 |
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574 BTP_ENTRY CLIENT_DOMAIN, PERM_RORO, CACHE_WBWA, 1, 1, 0, 0 ; ROM |
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575 BTP_ENTRY CLIENT_DOMAIN, PERM_RWNO, CACHE_WBWA, 0, 1, 0, 0 ; kernel data/stack/heap |
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576 BTP_ENTRY CLIENT_DOMAIN, PERM_RWNO, CACHE_WBWA, 0, 1, 0, 0 ; super page/CPU page |
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577 BTP_ENTRY CLIENT_DOMAIN, PERM_RWNO, CACHE_WBWA, 0, 1, 0, 0 ; page directory/tables |
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578 BTP_ENTRY CLIENT_DOMAIN, PERM_RONO, CACHE_WTRA, 1, 1, 0, 0 ; exception vectors |
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579 BTP_ENTRY CLIENT_DOMAIN, PERM_RWNO, CACHE_SO, 0, 1, 0, 0 ; hardware registers |
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580 DCD 0 ; unused (minicache flush) |
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581 DCD 0 ; unused (maincache flush) |
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582 BTP_ENTRY CLIENT_DOMAIN, PERM_RWNO, CACHE_WBWA, 0, 1, 0, 0 ; page table info |
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583 BTP_ENTRY CLIENT_DOMAIN, PERM_RWRW, CACHE_WBWA, 1, 1, 0, 0 ; user RAM |
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584 BTP_ENTRY CLIENT_DOMAIN, PERM_RONO, CACHE_SO, 1, 1, 0, 0 ; temporary identity mapping |
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585 BTP_ENTRY CLIENT_DOMAIN, UNC_PERM, CACHE_SO, 0, 1, 0, 0 ; uncached |
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586 ENDIF |
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587 ENDIF |
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588 IF CFG_MMMoving |
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589 BTP_ENTRY CLIENT_DOMAIN, PERM_RORO, CACHE_WT ; ROM |
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590 BTP_ENTRY CLIENT_DOMAIN, PERM_RWNO, CACHE_WB ; kernel data/stack/heap |
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591 BTP_ENTRY CLIENT_DOMAIN, PERM_RWNO, CACHE_WB ; super page/CPU page |
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592 BTP_ENTRY CLIENT_DOMAIN, PERM_RWNO, CACHE_WT ; page directory/tables |
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593 BTP_ENTRY CLIENT_DOMAIN, PERM_RORO, CACHE_WT ; exception vectors |
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594 BTP_ENTRY CLIENT_DOMAIN, PERM_RWRO, CACHE_NCNB ; hardware registers |
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595 DCD 0 ; unused (minicache flush) |
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596 DCD 0 ; unused (maincache flush) |
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597 BTP_ENTRY CLIENT_DOMAIN, PERM_RWNO, CACHE_WB ; page table info |
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598 BTP_ENTRY CLIENT_DOMAIN, PERM_RWRW, CACHE_WB ; user RAM |
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599 BTP_ENTRY CLIENT_DOMAIN, PERM_RORO, CACHE_NCNB ; temporary identity mapping |
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600 BTP_ENTRY CLIENT_DOMAIN, UNC_PERM, CACHE_NCNB ; uncached |
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601 ENDIF |
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602 |
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603 END |