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/*
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* Device.h
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*
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* Copyright(c) 1998 - 2010 Texas Instruments. All rights reserved.
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* All rights reserved.
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*
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* This program and the accompanying materials are made available under the
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* terms of the Eclipse Public License v1.0 or BSD License which accompanies
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* this distribution. The Eclipse Public License is available at
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* http://www.eclipse.org/legal/epl-v10.html and the BSD License is as below.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name Texas Instruments nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/****************************************************************************
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*
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* MODULE: Device.h
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* PURPOSE: Contains Wlan hardware registers defines/structures
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*
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****************************************************************************/
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#ifndef DEVICE_H
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#define DEVICE_H
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#include "Device1273.h"
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#define ACX_PHI_CCA_THRSH_ENABLE_ENERGY_D 0x140A
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#define ACX_PHI_CCA_THRSH_DISABLE_ENERGY_D 0xFFEF
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/*
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* Wlan hardware Registers.
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*/
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/*======================================================================
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Interrupt Registers
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=======================================================================*/
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#define ACX_REG_INTERRUPT_TRIG ( INT_TRIG )
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#define ACX_REG_INTERRUPT_TRIG_H ( INT_TRIG_H )
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/*=============================================
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Host Interrupt Mask Register - 32bit (RW)
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------------------------------------------
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Setting a bit in this register masks the
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corresponding interrupt to the host.
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0 - RX0 - Rx first dubble buffer Data Interrupt
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1 - TXD - Tx Data Interrupt
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2 - TXXFR - Tx Transfer Interrupt
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3 - RX1 - Rx second dubble buffer Data Interrupt
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4 - RXXFR - Rx Transfer Interrupt
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5 - EVENT_A - Event Mailbox interrupt
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6 - EVENT_B - Event Mailbox interrupt
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7 - WNONHST - Wake On Host Interrupt
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8 - TRACE_A - Debug Trace interrupt
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9 - TRACE_B - Debug Trace interrupt
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10 - CDCMP - Command Complete Interrupt
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11 -
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12 -
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13 -
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14 - ICOMP - Initialization Complete Interrupt
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16 - SG SE - Soft Gemini - Sense enable interrupt
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17 - SG SD - Soft Gemini - Sense disable interrupt
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18 - -
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19 - -
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20 - -
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21- -
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Default: 0x0001
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*==============================================*/
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#define ACX_REG_INTERRUPT_MASK ( HINT_MASK )
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/*=============================================
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Host Interrupt Mask Set 16bit, (Write only)
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------------------------------------------
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Setting a bit in this register sets
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the corresponding bin in ACX_HINT_MASK register
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without effecting the mask
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state of other bits (0 = no effect).
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==============================================*/
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#define ACX_HINT_MASK_SET_REG HINT_MASK_SET
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/*=============================================
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Host Interrupt Mask Clear 16bit,(Write only)
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------------------------------------------
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Setting a bit in this register clears
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the corresponding bin in ACX_HINT_MASK register
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without effecting the mask
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state of other bits (0 = no effect).
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=============================================*/
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#define ACX_HINT_MASK_CLR_REG HINT_MASK_CLR
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/*=============================================
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Host Interrupt Status Nondestructive Read
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16bit,(Read only)
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------------------------------------------
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The host can read this register to determine
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which interrupts are active.
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Reading this register doesn't
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effect its content.
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=============================================*/
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#define ACX_REG_INTERRUPT_NO_CLEAR ( HINT_STS_ND )
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/*=============================================
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Host Interrupt Status Clear on Read Register
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16bit,(Read only)
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------------------------------------------
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The host can read this register to determine
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which interrupts are active.
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Reading this register clears it,
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thus making all interrupts inactive.
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==============================================*/
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#define ACX_REG_INTERRUPT_CLEAR ( HINT_STS_CLR )
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/*=============================================
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Host Interrupt Acknowledge Register
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16bit,(Write only)
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------------------------------------------
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The host can set individual bits in this
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register to clear (acknowledge) the corresp.
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interrupt status bits in the HINT_STS_CLR and
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HINT_STS_ND registers, thus making the
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assotiated interrupt inactive. (0-no effect)
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==============================================*/
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#define ACX_REG_INTERRUPT_ACK ( HINT_ACK )
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/*===============================================
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Host Software Reset - 32bit RW
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------------------------------------------
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[31:1] Reserved
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0 SOFT_RESET Soft Reset - When this bit is set,
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it holds the Wlan hardware in a soft reset state.
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This reset disables all MAC and baseband processor
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clocks except the CardBus/PCI interface clock.
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It also initializes all MAC state machines except
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the host interface. It does not reload the
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contents of the EEPROM. When this bit is cleared
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(not self-clearing), the Wlan hardware
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exits the software reset state.
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===============================================*/
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#define ACX_REG_SLV_SOFT_RESET ( SLV_SOFT_RESET )
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#define SLV_SOFT_RESET_BIT 0x00000001
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/*===============================================
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EEPROM Burst Read Start - 32bit RW
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------------------------------------------
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[31:1] Reserved
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0 ACX_EE_START - EEPROM Burst Read Start 0
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Setting this bit starts a burst read from
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the external EEPROM.
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If this bit is set (after reset) before an EEPROM read/write,
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the burst read starts at EEPROM address 0.
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Otherwise, it starts at the address
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following the address of the previous access.
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TheWlan hardware hardware clears this bit automatically.
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Default: 0x00000000
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*================================================*/
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#define ACX_REG_EE_START ( EE_START )
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#define START_EEPROM_MGR 0x00000001
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/*=======================================================================
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Embedded ARM CPU Control
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========================================================================*/
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/*===============================================
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Halt eCPU - 32bit RW
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------------------------------------------
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0 HALT_ECPU Halt Embedded CPU - This bit is the
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compliment of bit 1 (MDATA2) in the SOR_CFG register.
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During a hardware reset, this bit holds
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the inverse of MDATA2.
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When downloading firmware from the host,
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set this bit (pull down MDATA2).
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The host clears this bit after downloading the firmware into
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zero-wait-state SSRAM.
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When loading firmware from Flash, clear this bit (pull up MDATA2)
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so that the eCPU can run the bootloader code in Flash
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HALT_ECPU eCPU State
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--------------------
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1 halt eCPU
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0 enable eCPU
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===============================================*/
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#define ACX_REG_ECPU_CONTROL ( ECPU_CTRL )
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/*=======================================================================
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Command/Information Mailbox Pointers
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========================================================================*/
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/*===============================================
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Command Mailbox Pointer - 32bit RW
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------------------------------------------
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This register holds the start address of
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the command mailbox located in the Wlan hardware memory.
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The host must read this pointer after a reset to
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find the location of the command mailbox.
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The Wlan hardware initializes the command mailbox
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pointer with the default address of the command mailbox.
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The command mailbox pointer is not valid until after
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the host receives the Init Complete interrupt from
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the Wlan hardware.
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===============================================*/
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#define REG_COMMAND_MAILBOX_PTR ( SCR_PAD0 )
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/*===============================================
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Information Mailbox Pointer - 32bit RW
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------------------------------------------
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This register holds the start address of
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the information mailbox located in the Wlan hardware memory.
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The host must read this pointer after a reset to find
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the location of the information mailbox.
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The Wlan hardware initializes the information mailbox pointer
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with the default address of the information mailbox.
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The information mailbox pointer is not valid
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until after the host receives the Init Complete interrupt from
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the Wlan hardware.
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===============================================*/
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#define REG_EVENT_MAILBOX_PTR ( SCR_PAD1 )
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/*=======================================================================
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Misc
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========================================================================*/
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#define REG_ENABLE_TX_RX ( IO_CONTROL_ENABLE )
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/*
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* Rx configuration (filter) information element
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* ---------------------------------------------
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*/
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#define REG_RX_CONFIG ( RX_CFG )
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#define REG_RX_FILTER ( RX_FILTER_CFG )
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#define RX_CFG_ENABLE_PHY_HEADER_PLCP 0x0002
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#define RX_CFG_PROMISCUOUS 0x0008 /* promiscuous - receives all valid frames */
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#define RX_CFG_BSSID 0x0020 /* receives frames from any BSSID */
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#define RX_CFG_MAC 0x0010 /* receives frames destined to any MAC address */
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#define RX_CFG_ENABLE_ONLY_MY_DEST_MAC 0x0010
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#define RX_CFG_ENABLE_ANY_DEST_MAC 0x0000
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#define RX_CFG_ENABLE_ONLY_MY_BSSID 0x0020
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#define RX_CFG_ENABLE_ANY_BSSID 0x0000
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#define RX_CFG_DISABLE_BCAST 0x0200 /* discards all broadcast frames */
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#define RX_CFG_ENABLE_ONLY_MY_SSID 0x0400
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#define RX_CFG_ENABLE_RX_CMPLT_FCS_ERROR 0x0800
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#define RX_CFG_COPY_RX_STATUS 0x2000
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#define RX_CFG_TSF 0x10000
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#define RX_CONFIG_OPTION_ANY_DST_MY_BSS ( RX_CFG_ENABLE_ANY_DEST_MAC | RX_CFG_ENABLE_ONLY_MY_BSSID)
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#define RX_CONFIG_OPTION_MY_DST_ANY_BSS ( RX_CFG_ENABLE_ONLY_MY_DEST_MAC | RX_CFG_ENABLE_ANY_BSSID)
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#define RX_CONFIG_OPTION_ANY_DST_ANY_BSS ( RX_CFG_ENABLE_ANY_DEST_MAC | RX_CFG_ENABLE_ANY_BSSID)
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#define RX_CONFIG_OPTION_MY_DST_MY_BSS ( RX_CFG_ENABLE_ONLY_MY_DEST_MAC | RX_CFG_ENABLE_ONLY_MY_BSSID)
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#define RX_CONFIG_OPTION_FOR_SCAN ( RX_CFG_ENABLE_PHY_HEADER_PLCP | RX_CFG_ENABLE_RX_CMPLT_FCS_ERROR | RX_CFG_COPY_RX_STATUS | RX_CFG_TSF)
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#define RX_CONFIG_OPTION_FOR_MEASUREMENT ( RX_CFG_ENABLE_ANY_DEST_MAC )
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#define RX_CONFIG_OPTION_FOR_JOIN ( RX_CFG_ENABLE_ONLY_MY_BSSID | RX_CFG_ENABLE_ONLY_MY_DEST_MAC )
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#define RX_CONFIG_OPTION_FOR_IBSS_JOIN ( RX_CFG_ENABLE_ONLY_MY_SSID | RX_CFG_ENABLE_ONLY_MY_DEST_MAC )
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#define RX_FILTER_OPTION_DEF ( CFG_RX_MGMT_EN | CFG_RX_DATA_EN | CFG_RX_CTL_EN | CFG_RX_RCTS_ACK | CFG_RX_BCN_EN | CFG_RX_AUTH_EN | CFG_RX_ASSOC_EN)
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#define RX_FILTER_OPTION_FILTER_ALL 0
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#define RX_FILTER_OPTION_DEF_PRSP_BCN ( CFG_RX_PRSP_EN | CFG_RX_MGMT_EN | CFG_RX_CTL_EN | CFG_RX_RCTS_ACK | CFG_RX_BCN_EN)
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#define RX_FILTER_OPTION_JOIN ( CFG_RX_MGMT_EN | CFG_RX_DATA_EN | CFG_RX_CTL_EN | CFG_RX_BCN_EN | CFG_RX_AUTH_EN | CFG_RX_ASSOC_EN | CFG_RX_RCTS_ACK | CFG_RX_PRSP_EN)
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/*===============================================
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Phy regs
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===============================================*/
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#define ACX_PHY_ADDR_REG SBB_ADDR
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#define ACX_PHY_DATA_REG SBB_DATA
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#define ACX_PHY_CTRL_REG SBB_CTL
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#define ACX_PHY_REG_WR_MASK 0x00000001ul
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#define ACX_PHY_REG_RD_MASK 0x00000002ul
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/*===============================================
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EEPROM Read/Write Request 32bit RW
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------------------------------------------
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1 EE_READ - EEPROM Read Request 1 - Setting this bit
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loads a single byte of data into the EE_DATA
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register from the EEPROM location specified in
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the EE_ADDR register.
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The Wlan hardware hardware clears this bit automatically.
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EE_DATA is valid when this bit is cleared.
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0 EE_WRITE - EEPROM Write Request - Setting this bit
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writes a single byte of data from the EE_DATA register into the
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EEPROM location specified in the EE_ADDR register.
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The Wlan hardware hardware clears this bit automatically.
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*===============================================*/
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#define ACX_EE_CTL_REG EE_CTL
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#define EE_WRITE 0x00000001ul
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#define EE_READ 0x00000002ul
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/*===============================================
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EEPROM Address - 32bit RW
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------------------------------------------
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This register specifies the address
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within the EEPROM from/to which to read/write data.
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===============================================*/
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#define ACX_EE_ADDR_REG EE_ADDR
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/*===============================================
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EEPROM Data - 32bit RW
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328 |
------------------------------------------
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This register either holds the read 8 bits of
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data from the EEPROM or the write data
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to be written to the EEPROM.
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332 |
===============================================*/
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#define ACX_EE_DATA_REG EE_DATA
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/*===============================================
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336 |
EEPROM Base Address - 32bit RW
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337 |
------------------------------------------
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This register holds the upper nine bits
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339 |
[23:15] of the 24-bit Wlan hardware memory
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address for burst reads from EEPROM accesses.
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The EEPROM provides the lower 15 bits of this address.
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The MSB of the address from the EEPROM is ignored.
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===============================================*/
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#define ACX_EE_CFG EE_CFG
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/*===============================================
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GPIO Output Values -32bit, RW
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------------------------------------------
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[31:16] Reserved
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350 |
[15: 0] Specify the output values (at the output driver inputs) for
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GPIO[15:0], respectively.
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===============================================*/
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#define ACX_GPIO_OUT_REG GPIO_OUT
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#define ACX_MAX_GPIO_LINES 15
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/*===============================================
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357 |
Contention window -32bit, RW
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358 |
------------------------------------------
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359 |
[31:26] Reserved
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360 |
[25:16] Max (0x3ff)
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[15:07] Reserved
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[06:00] Current contention window value - default is 0x1F
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===============================================*/
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364 |
#define ACX_CONT_WIND_CFG_REG CONT_WIND_CFG
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#define ACX_CONT_WIND_MIN_MASK 0x0000007f
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#define ACX_CONT_WIND_MAX 0x03ff0000
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/*
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* Indirect slave register/memory registers
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* ----------------------------------------
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*/
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#define HW_SLAVE_REG_ADDR_REG 0x00000004
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#define HW_SLAVE_REG_DATA_REG 0x00000008
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#define HW_SLAVE_REG_CTRL_REG 0x0000000c
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#define SLAVE_AUTO_INC 0x00010000
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#define SLAVE_NO_AUTO_INC 0x00000000
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#define SLAVE_HOST_LITTLE_ENDIAN 0x00000000
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#define HW_SLAVE_MEM_ADDR_REG SLV_MEM_ADDR
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#define HW_SLAVE_MEM_DATA_REG SLV_MEM_DATA
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#define HW_SLAVE_MEM_CTRL_REG SLV_MEM_CTL
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#define HW_SLAVE_MEM_ENDIAN_REG SLV_END_CTL
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384 |
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#define HW_FUNC_EVENT_INT_EN 0x8000
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386 |
#define HW_FUNC_EVENT_MASK_REG 0x00000034
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387 |
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388 |
#define ACX_MAC_TIMESTAMP_REG (MAC_TIMESTAMP)
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389 |
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390 |
/*===============================================
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391 |
HI_CFG Interface Configuration Register Values
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------------------------------------------
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===============================================*/
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#define HI_CFG_UART_ENABLE 0x00000004
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#define HI_CFG_RST232_ENABLE 0x00000008
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#define HI_CFG_CLOCK_REQ_SELECT 0x00000010
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#define HI_CFG_HOST_INT_ENABLE 0x00000020
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#define HI_CFG_VLYNQ_OUTPUT_ENABLE 0x00000040
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#define HI_CFG_HOST_INT_ACTIVE_LOW 0x00000080
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#define HI_CFG_UART_TX_OUT_GPIO_15 0x00000100
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#define HI_CFG_UART_TX_OUT_GPIO_14 0x00000200
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#define HI_CFG_UART_TX_OUT_GPIO_7 0x00000400
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403 |
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/*
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* NOTE: USE_ACTIVE_HIGH compilation flag should be defined in makefile
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* for platforms using active high interrupt level
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*/
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#ifdef USE_IRQ_ACTIVE_HIGH
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#define HI_CFG_DEF_VAL \
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HI_CFG_UART_ENABLE | \
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HI_CFG_RST232_ENABLE | \
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HI_CFG_CLOCK_REQ_SELECT | \
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HI_CFG_HOST_INT_ENABLE
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#else
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415 |
#define HI_CFG_DEF_VAL \
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HI_CFG_UART_ENABLE | \
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HI_CFG_RST232_ENABLE | \
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HI_CFG_CLOCK_REQ_SELECT | \
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HI_CFG_HOST_INT_ENABLE | \
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HI_CFG_HOST_INT_ACTIVE_LOW
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#endif
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422 |
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#endif /* DEVICE_H */
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