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/*
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* HwInit.c
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*
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* Copyright(c) 1998 - 2010 Texas Instruments. All rights reserved.
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* All rights reserved.
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*
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* This program and the accompanying materials are made available under the
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* terms of the Eclipse Public License v1.0 or BSD License which accompanies
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* this distribution. The Eclipse Public License is available at
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* http://www.eclipse.org/legal/epl-v10.html and the BSD License is as below.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name Texas Instruments nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*******************************************************************************/
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/* */
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/* MODULE: HwInit.c */
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/* PURPOSE: HwInit module manages the init process of the TNETW, included */
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/* firmware download process. It shall perform Hard Reset the chip */
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/* if possible (this will require a Reset line to be connected to */
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/* the host); Start InterfaceCtrl; Download NVS and FW */
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/* */
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/* */
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/*******************************************************************************/
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#define __FILE_ID__ FILE_ID_105
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#include "tidef.h"
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#include "osApi.h"
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#include "report.h"
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#include "HwInit_api.h"
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#include "FwEvent_api.h"
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#include "TwIf.h"
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#include "TWDriver.h"
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#include "TWDriverInternal.h"
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#include "eventMbox_api.h"
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#include "CmdBld.h"
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#include "CmdMBox_api.h"
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extern void TWD_FinalizeOnFailure (TI_HANDLE hTWD);
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extern void cmdBld_FinalizeDownload (TI_HANDLE hCmdBld, TBootAttr *pBootAttr, FwStaticData_t *pFwInfo);
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/************************************************************************
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* Defines
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************************************************************************/
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/* Download phase partition */
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#define PARTITION_DOWN_MEM_ADDR 0
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#define PARTITION_DOWN_MEM_SIZE 0x177C0
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#define PARTITION_DOWN_REG_ADDR REGISTERS_BASE
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#define PARTITION_DOWN_REG_SIZE 0x8800
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/* Working phase partition */
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#define PARTITION_WORK_MEM_ADDR1 0x40000
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#define PARTITION_WORK_MEM_SIZE1 0x14FC0
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#define PARTITION_WORK_MEM_ADDR2 REGISTERS_BASE
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#define PARTITION_WORK_MEM_SIZE2 0xA000
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#define PARTITION_WORK_MEM_ADDR3 0x3004F8
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#define PARTITION_WORK_MEM_SIZE3 0x4
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#define PARTITION_WORK_MEM_ADDR4 0x40404
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/* DRPW setting partition */
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#define PARTITION_DRPW_MEM_ADDR 0x40000
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#define PARTITION_DRPW_MEM_SIZE 0x14FC0
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#define PARTITION_DRPW_REG_ADDR DRPW_BASE
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#define PARTITION_DRPW_REG_SIZE 0x6000
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/* Total range of bus addresses range */
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#define PARTITION_TOTAL_ADDR_RANGE 0x1FFC0
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/* Maximal block size in a single SDIO transfer --> Firmware image load chunk size */
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#ifdef _VLCT_
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#define MAX_SDIO_BLOCK (4000)
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#else
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#define MAX_SDIO_BLOCK (500)
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#endif
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#define ACX_EEPROMLESS_IND_REG (SCR_PAD4)
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#define USE_EEPROM (0)
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#define SOFT_RESET_MAX_TIME (1000000)
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#define SOFT_RESET_STALL_TIME (1000)
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#define NVS_DATA_BUNDARY_ALIGNMENT (4)
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#define MAX_HW_INIT_CONSECUTIVE_TXN 15
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#define WORD_SIZE 4
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#define WORD_ALIGNMENT_MASK 0x3
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#define DEF_NVS_SIZE (NVS_TOTAL_LENGTH)
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#define RADIO_SM_WAIT_LOOP 32
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#define FREF_CLK_FREQ_MASK 0x7
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#define FREF_CLK_TYPE_MASK BIT_3
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#define FREF_CLK_POLARITY_MASK BIT_4
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#define FREF_CLK_TYPE_BITS 0xfffffe7f
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#define CLK_REQ_PRCM 0x100
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#define FREF_CLK_POLARITY_BITS 0xfffff8ff
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#define CLK_REQ_OUTN_SEL 0x700
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/* time to wait till we check if fw is running */
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#define STALL_TIMEOUT 10
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#define FIN_LOOP 10
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/************************************************************************
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* Macros
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************************************************************************/
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#define SET_DEF_NVS(aNVS) aNVS[0]=0x01; aNVS[1]=0x6d; aNVS[2]=0x54; aNVS[3]=0x56; aNVS[4]=0x34; \
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aNVS[5]=0x12; aNVS[6]=0x28; aNVS[7]=0x01; aNVS[8]=0x71; aNVS[9]=0x54; \
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aNVS[10]=0x00; aNVS[11]=0x08; aNVS[12]=0x00; aNVS[13]=0x00; aNVS[14]=0x00; \
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aNVS[15]=0x00; aNVS[16]=0x00; aNVS[17]=0x00; aNVS[18]=0x00; aNVS[19]=0x00; \
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aNVS[20]=0x00; aNVS[21]=0x00; aNVS[22]=0x00; aNVS[23]=0x00; aNVS[24]=eNVS_NON_FILE;\
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aNVS[25]=0x00; aNVS[26]=0x00; aNVS[27]=0x00;
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#define SET_PARTITION(pPartition,uAddr1,uMemSize1,uAddr2,uMemSize2,uAddr3,uMemSize3,uAddr4) \
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((TPartition*)pPartition)[0].uMemAdrr = uAddr1; \
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((TPartition*)pPartition)[0].uMemSize = uMemSize1; \
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((TPartition*)pPartition)[1].uMemAdrr = uAddr2; \
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((TPartition*)pPartition)[1].uMemSize = uMemSize2; \
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((TPartition*)pPartition)[2].uMemAdrr = uAddr3; \
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((TPartition*)pPartition)[2].uMemSize = uMemSize3; \
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((TPartition*)pPartition)[3].uMemAdrr = uAddr4;
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#define HW_INIT_PTXN_SET(pHwInit, pTxn) pTxn = (TTxnStruct*)&(pHwInit->aHwInitTxn[pHwInit->uTxnIndex].tTxnStruct);
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#define BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, uAddr, uVal, uSize, direction, fCB, hCB) \
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HW_INIT_PTXN_SET(pHwInit, pTxn) \
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TXN_PARAM_SET_DIRECTION(pTxn, direction); \
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*((TI_UINT32*)(pHwInit->aHwInitTxn[pHwInit->uTxnIndex].pData)) = (TI_UINT32)uVal; \
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BUILD_TTxnStruct(pTxn, uAddr, pHwInit->aHwInitTxn[pHwInit->uTxnIndex].pData, uSize, fCB, hCB)
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#define BUILD_HW_INIT_FW_STATIC_TXN(pHwInit, pTxn, uAddr, fCB, hCB) \
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HW_INIT_PTXN_SET(pHwInit, pTxn) \
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TXN_PARAM_SET_DIRECTION(pTxn, TXN_DIRECTION_READ); \
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BUILD_TTxnStruct(pTxn, uAddr, pHwInit->tFwStaticTxn.pFwStaticInfo, sizeof(FwStaticData_t), fCB, hCB)
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#define BUILD_HW_INIT_FW_DL_TXN(pHwInit, pTxn, uAddr, uVal, uSize, direction, fCB, hCB) \
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HW_INIT_PTXN_SET(pHwInit, pTxn) \
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TXN_PARAM_SET_DIRECTION(pTxn, direction); \
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BUILD_TTxnStruct(pTxn, uAddr, uVal, uSize, fCB, hCB)
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#define SET_DRP_PARTITION(pPartition)\
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SET_PARTITION(pPartition, PARTITION_DRPW_MEM_ADDR, PARTITION_DRPW_MEM_SIZE, PARTITION_DRPW_REG_ADDR, PARTITION_DRPW_REG_SIZE, 0, 0, 0)
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#define SET_FW_LOAD_PARTITION(pPartition,uFwAddress)\
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SET_PARTITION(pPartition,uFwAddress,PARTITION_DOWN_MEM_SIZE, PARTITION_DOWN_REG_ADDR, PARTITION_DOWN_REG_SIZE,0,0,0)
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#define SET_WORK_PARTITION(pPartition)\
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SET_PARTITION(pPartition,PARTITION_WORK_MEM_ADDR1, PARTITION_WORK_MEM_SIZE1, PARTITION_WORK_MEM_ADDR2, PARTITION_WORK_MEM_SIZE2, PARTITION_WORK_MEM_ADDR3, PARTITION_WORK_MEM_SIZE3, PARTITION_WORK_MEM_ADDR4)
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/* Handle return status inside a state machine */
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#define EXCEPT(phwinit,status) \
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switch (status) { \
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case TI_OK: \
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case TXN_STATUS_OK: \
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case TXN_STATUS_COMPLETE: \
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break; \
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case TXN_STATUS_PENDING: \
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return TXN_STATUS_PENDING; \
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default: \
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phwinit->DownloadStatus = TXN_STATUS_ERROR; \
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TWD_FinalizeOnFailure (phwinit->hTWD); \
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return TXN_STATUS_ERROR; \
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}
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/* Handle return status inside an init sequence state machine */
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#define EXCEPT_I(phwinit,status) \
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switch (status) { \
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case TI_OK: \
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case TXN_STATUS_COMPLETE: \
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break; \
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case TXN_STATUS_PENDING: \
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phwinit->uInitSeqStatus = status; \
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return TXN_STATUS_PENDING; \
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default: \
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TWD_FinalizeOnFailure (phwinit->hTWD); \
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return TXN_STATUS_ERROR; \
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}
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/* Handle return status inside a load image state machine */
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#define EXCEPT_L(phwinit,status) \
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switch (status) { \
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case TXN_STATUS_OK: \
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case TXN_STATUS_COMPLETE: \
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break; \
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case TXN_STATUS_PENDING: \
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phwinit->DownloadStatus = status; \
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return TXN_STATUS_PENDING; \
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default: \
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phwinit->DownloadStatus = status; \
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TWD_FinalizeOnFailure (phwinit->hTWD); \
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return TXN_STATUS_ERROR; \
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}
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/************************************************************************
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* Types
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************************************************************************/
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enum
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{
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REF_FREQ_19_2 = 0,
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REF_FREQ_26_0 = 1,
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REF_FREQ_38_4 = 2,
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REF_FREQ_40_0 = 3,
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REF_FREQ_33_6 = 4,
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REF_FREQ_NUM = 5
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};
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enum
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{
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LUT_PARAM_INTEGER_DIVIDER = 0,
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LUT_PARAM_FRACTIONAL_DIVIDER = 1,
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LUT_PARAM_ATTN_BB = 2,
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LUT_PARAM_ALPHA_BB = 3,
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LUT_PARAM_STOP_TIME_BB = 4,
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LUT_PARAM_BB_PLL_LOOP_FILTER = 5,
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LUT_PARAM_NUM = 6
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};
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typedef struct
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{
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TTxnStruct tTxnStruct;
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TI_UINT8 *pData;
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} THwInitTxn;
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typedef struct
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{
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TTxnStruct tTxnStruct;
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TI_UINT8 *pFwStaticInfo;
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} TFwStaticTxn;
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/* The HW Init module object */
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typedef struct
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{
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/* Handles */
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TI_HANDLE hOs;
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TI_HANDLE hReport;
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TI_HANDLE hTWD;
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TI_HANDLE hBusTxn;
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TI_HANDLE hTwIf;
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TI_HANDLE hFileInfo; /* holds parameters of FW Image Portion - for DW Download */
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TEndOfHwInitCb fInitHwCb;
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/* Firmware image ptr */
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TI_UINT8 *pFwBuf;
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/* Firmware image length */
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TI_UINT32 uFwLength;
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TI_UINT32 uFwAddress;
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TI_UINT32 bFwBufLast;
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TI_UINT32 uFwLastAddr;
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/* EEPROM image ptr */
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TI_UINT8 *pEEPROMBuf;
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/* EEPROM image length */
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TI_UINT32 uEEPROMLen;
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TI_UINT8 *pEEPROMCurPtr;
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TI_UINT32 uEEPROMCurLen;
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TBootAttr tBootAttr;
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TI_HANDLE hHwCtrl;
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ETxnStatus DownloadStatus;
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/* Upper module callback for the init stage */
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fnotify_t fCb;
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/* Upper module handle for the init stage */
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TI_HANDLE hCb;
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/* Init stage */
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TI_UINT32 uInitStage;
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/* Reset statge */
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TI_UINT32 uResetStage;
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/* EEPROM burst stage */
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TI_UINT32 uEEPROMStage;
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/* Init state machine temporary data */
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TI_UINT32 uInitData;
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/* ELP command image */
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TI_UINT32 uElpCmd;
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/* Chip ID */
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TI_UINT32 uChipId;
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/* Boot state machine temporary data */
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TI_UINT32 uBootData;
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TI_UINT32 uSelfClearTime;
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TI_UINT8 uEEPROMBurstLen;
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TI_UINT8 uEEPROMBurstLoop;
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TI_UINT32 uEEPROMRegAddr;
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TI_STATUS uEEPROMStatus;
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TI_UINT32 uNVSStartAddr;
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TI_UINT32 uNVSNumChar;
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TI_UINT32 uNVSNumByte;
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TI_STATUS uNVSStatus;
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TI_UINT32 uScrPad6;
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TI_UINT32 uRefFreq;
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TI_UINT32 uInitSeqStage;
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TI_STATUS uInitSeqStatus;
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TI_UINT32 uLoadStage;
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TI_UINT32 uBlockReadNum;
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TI_UINT32 uBlockWriteNum;
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TI_UINT32 uPartitionLimit;
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TI_UINT32 uFinStage;
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TI_UINT32 uFinData;
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TI_UINT32 uFinLoop;
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TI_UINT32 uRegStage;
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TI_UINT32 uRegLoop;
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TI_UINT32 uRegSeqStage;
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TI_UINT32 uRegData;
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#ifndef _VLCT_
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TI_HANDLE hStallTimer;
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#endif
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/* Top register Read/Write SM temporary data*/
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TI_UINT32 uTopRegAddr;
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TI_UINT32 uTopRegValue;
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TI_UINT32 uTopRegMask;
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TI_UINT32 uTopRegUpdateValue;
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TI_UINT32 uTopStage;
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TI_STATUS uTopStatus;
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TI_UINT8 *puFwTmpBuf;
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TFinalizeCb fFinalizeDownload;
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TI_HANDLE hFinalizeDownload;
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/* Size of the Fw image, retrieved from the image itself */
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TI_UINT32 uFwDataLen;
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TI_UINT8 aDefaultNVS[DEF_NVS_SIZE];
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TI_UINT8 uTxnIndex;
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THwInitTxn aHwInitTxn[MAX_HW_INIT_CONSECUTIVE_TXN];
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TFwStaticTxn tFwStaticTxn;
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TI_UINT32 uSavedDataForWspiHdr; /* For saving the 4 bytes before the NVS data for WSPI case
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where they are overrun by the WSPI BusDrv */
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TPartition aPartition[NUM_OF_PARTITION];
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} THwInit;
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/************************************************************************
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* Local Functions Prototypes
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************************************************************************/
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static void hwInit_SetPartition (THwInit *pHwInit,
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|
375 |
TPartition *pPartition);
|
|
376 |
static TI_STATUS hwInit_BootSm (TI_HANDLE hHwInit);
|
|
377 |
static TI_STATUS hwInit_ResetSm (TI_HANDLE hHwInit);
|
|
378 |
static TI_STATUS hwInit_EepromlessStartBurstSm (TI_HANDLE hHwInit);
|
|
379 |
static TI_STATUS hwInit_LoadFwImageSm (TI_HANDLE hHwInit);
|
|
380 |
static TI_STATUS hwInit_FinalizeDownloadSm (TI_HANDLE hHwInit);
|
|
381 |
static TI_STATUS hwInit_TopRegisterRead(TI_HANDLE hHwInit);
|
|
382 |
static TI_STATUS hwInit_InitTopRegisterRead(TI_HANDLE hHwInit, TI_UINT32 uAddress);
|
|
383 |
static TI_STATUS hwInit_TopRegisterWrite(TI_HANDLE hHwInit);
|
|
384 |
static TI_STATUS hwInit_InitTopRegisterWrite(TI_HANDLE hHwInit, TI_UINT32 uAddress, TI_UINT32 uValue);
|
|
385 |
#ifndef _VLCT_
|
|
386 |
static void hwInit_StallTimerCb (TI_HANDLE hHwInit);
|
|
387 |
#endif
|
|
388 |
|
|
389 |
|
|
390 |
/*******************************************************************************
|
|
391 |
* PUBLIC FUNCTIONS IMPLEMENTATION *
|
|
392 |
********************************************************************************/
|
|
393 |
|
|
394 |
|
|
395 |
/*************************************************************************
|
|
396 |
* hwInit_Create *
|
|
397 |
**************************************************************************
|
|
398 |
* DESCRIPTION: This function initializes the HwInit module.
|
|
399 |
*
|
|
400 |
* INPUT: hOs - handle to Os Abstraction Layer
|
|
401 |
*
|
|
402 |
* RETURN: Handle to the allocated HwInit module
|
|
403 |
*************************************************************************/
|
|
404 |
TI_HANDLE hwInit_Create (TI_HANDLE hOs)
|
|
405 |
{
|
|
406 |
THwInit *pHwInit;
|
|
407 |
int i;
|
|
408 |
|
|
409 |
/* Allocate HwInit module */
|
|
410 |
pHwInit = os_memoryAlloc (hOs, sizeof(THwInit),MemoryNormal);
|
|
411 |
|
|
412 |
if (pHwInit == NULL)
|
|
413 |
{
|
|
414 |
WLAN_OS_REPORT(("Error allocating the HwInit Module\n"));
|
|
415 |
return NULL;
|
|
416 |
}
|
|
417 |
|
|
418 |
/* Reset HwInit module */
|
|
419 |
os_memoryZero (hOs, pHwInit, sizeof(THwInit));
|
|
420 |
|
|
421 |
/* Allocate Register buffer */
|
|
422 |
for (i = 0; i < MAX_HW_INIT_CONSECUTIVE_TXN; i++)
|
|
423 |
{
|
|
424 |
pHwInit->aHwInitTxn[i].pData = os_memoryAlloc (hOs, sizeof(TI_UINT32) + WSPI_PAD_LEN_READ,MemoryDMA);
|
|
425 |
if (pHwInit->aHwInitTxn[i].pData == NULL)
|
|
426 |
{
|
|
427 |
return NULL;
|
|
428 |
}
|
|
429 |
os_memoryZero (hOs, pHwInit->aHwInitTxn[i].pData, sizeof(TI_UINT32) + WSPI_PAD_LEN_READ);
|
|
430 |
pHwInit->aHwInitTxn[i].pData += WSPI_PAD_LEN_READ;
|
|
431 |
}
|
|
432 |
|
|
433 |
pHwInit->tFwStaticTxn.pFwStaticInfo = os_memoryAlloc (hOs, sizeof (FwStaticData_t) + WSPI_PAD_LEN_READ,MemoryDMA);
|
|
434 |
if (pHwInit->tFwStaticTxn.pFwStaticInfo == NULL)
|
|
435 |
{
|
|
436 |
return NULL;
|
|
437 |
}
|
|
438 |
os_memoryZero (hOs, pHwInit->tFwStaticTxn.pFwStaticInfo, sizeof (FwStaticData_t) + WSPI_PAD_LEN_READ);
|
|
439 |
pHwInit->tFwStaticTxn.pFwStaticInfo += WSPI_PAD_LEN_READ;
|
|
440 |
|
|
441 |
|
|
442 |
|
|
443 |
pHwInit->puFwTmpBuf = os_memoryAlloc (hOs, WSPI_PAD_LEN_READ + MAX_SDIO_BLOCK,MemoryDMA);
|
|
444 |
if (pHwInit->puFwTmpBuf == NULL)
|
|
445 |
{
|
|
446 |
return NULL;
|
|
447 |
}
|
|
448 |
os_memoryZero (hOs, pHwInit->puFwTmpBuf, WSPI_PAD_LEN_READ + MAX_SDIO_BLOCK);
|
|
449 |
pHwInit->puFwTmpBuf += WSPI_PAD_LEN_READ;
|
|
450 |
|
|
451 |
pHwInit->hOs = hOs;
|
|
452 |
|
|
453 |
return (TI_HANDLE)pHwInit;
|
|
454 |
}
|
|
455 |
|
|
456 |
|
|
457 |
/***************************************************************************
|
|
458 |
* hwInit_Destroy *
|
|
459 |
****************************************************************************
|
|
460 |
* DESCRIPTION: This function unload the HwInit module.
|
|
461 |
*
|
|
462 |
* INPUTS: hHwInit - the object
|
|
463 |
*
|
|
464 |
* OUTPUT:
|
|
465 |
*
|
|
466 |
* RETURNS: TI_OK - Unload succesfull
|
|
467 |
* TI_NOK - Unload unsuccesfull
|
|
468 |
***************************************************************************/
|
|
469 |
TI_STATUS hwInit_Destroy (TI_HANDLE hHwInit)
|
|
470 |
{
|
|
471 |
THwInit *pHwInit = (THwInit *)hHwInit;
|
|
472 |
int i;
|
|
473 |
|
|
474 |
for (i = 0; i < MAX_HW_INIT_CONSECUTIVE_TXN; i++)
|
|
475 |
{
|
|
476 |
if (pHwInit->aHwInitTxn[i].pData)
|
|
477 |
{
|
|
478 |
os_memoryFree (pHwInit->hOs, pHwInit->aHwInitTxn[i].pData - WSPI_PAD_LEN_READ, sizeof(TI_UINT32) + WSPI_PAD_LEN_READ);
|
|
479 |
}
|
|
480 |
}
|
|
481 |
|
|
482 |
if (pHwInit->puFwTmpBuf)
|
|
483 |
{
|
|
484 |
|
|
485 |
os_memoryFree (pHwInit->hOs, pHwInit->puFwTmpBuf - WSPI_PAD_LEN_READ, WSPI_PAD_LEN_READ + MAX_SDIO_BLOCK);
|
|
486 |
}
|
|
487 |
|
|
488 |
if (pHwInit->pEEPROMBuf)
|
|
489 |
{
|
|
490 |
os_memoryFree (pHwInit->hOs, pHwInit->pEEPROMBuf, pHwInit->uEEPROMLen);
|
|
491 |
}
|
|
492 |
|
|
493 |
if (pHwInit->tFwStaticTxn.pFwStaticInfo)
|
|
494 |
{
|
|
495 |
os_memoryFree (pHwInit->hOs, pHwInit->tFwStaticTxn.pFwStaticInfo - WSPI_PAD_LEN_READ, sizeof (FwStaticData_t) + WSPI_PAD_LEN_READ);
|
|
496 |
}
|
|
497 |
|
|
498 |
#ifndef _VLCT_
|
|
499 |
if (pHwInit->hStallTimer)
|
|
500 |
{
|
|
501 |
os_timerDestroy(pHwInit->hOs, pHwInit->hStallTimer);
|
|
502 |
}
|
|
503 |
#endif
|
|
504 |
|
|
505 |
/* Free HwInit Module */
|
|
506 |
os_memoryFree (pHwInit->hOs, pHwInit, sizeof(THwInit));
|
|
507 |
|
|
508 |
return TI_OK;
|
|
509 |
}
|
|
510 |
|
|
511 |
|
|
512 |
/***************************************************************************
|
|
513 |
* hwInit_Init *
|
|
514 |
****************************************************************************
|
|
515 |
* DESCRIPTION: This function configures the hwInit module
|
|
516 |
*
|
|
517 |
* RETURNS: TI_OK - Configuration successful
|
|
518 |
* TI_NOK - Configuration unsuccessful
|
|
519 |
***************************************************************************/
|
|
520 |
TI_STATUS hwInit_Init (TI_HANDLE hHwInit,
|
|
521 |
TI_HANDLE hReport,
|
|
522 |
TI_HANDLE hTWD,
|
|
523 |
TI_HANDLE hFinalizeDownload,
|
|
524 |
TFinalizeCb fFinalizeDownload,
|
|
525 |
TEndOfHwInitCb fInitHwCb)
|
|
526 |
{
|
|
527 |
THwInit *pHwInit = (THwInit *)hHwInit;
|
|
528 |
TTxnStruct* pTxn;
|
|
529 |
|
|
530 |
/* Configure modules handles */
|
|
531 |
pHwInit->hReport = hReport;
|
|
532 |
pHwInit->hTWD = hTWD;
|
|
533 |
pHwInit->hTwIf = ((TTwd *)hTWD)->hTwIf;
|
|
534 |
pHwInit->hOs = ((TTwd *)hTWD)->hOs;
|
|
535 |
pHwInit->fInitHwCb = fInitHwCb;
|
|
536 |
pHwInit->fFinalizeDownload = fFinalizeDownload;
|
|
537 |
pHwInit->hFinalizeDownload = hFinalizeDownload;
|
|
538 |
|
|
539 |
SET_DEF_NVS(pHwInit->aDefaultNVS)
|
|
540 |
|
|
541 |
for (pHwInit->uTxnIndex=0;pHwInit->uTxnIndex<MAX_HW_INIT_CONSECUTIVE_TXN;pHwInit->uTxnIndex++)
|
|
542 |
{
|
|
543 |
HW_INIT_PTXN_SET(pHwInit, pTxn)
|
|
544 |
/* Setting write as default transaction */
|
|
545 |
TXN_PARAM_SET(pTxn, TXN_LOW_PRIORITY, TXN_FUNC_ID_WLAN, TXN_DIRECTION_WRITE, TXN_INC_ADDR)
|
|
546 |
}
|
|
547 |
|
|
548 |
#ifndef _VLCT_
|
|
549 |
pHwInit->hStallTimer = os_timerCreate (pHwInit->hOs, hwInit_StallTimerCb, hHwInit);
|
|
550 |
if (pHwInit->hStallTimer == NULL)
|
|
551 |
{
|
|
552 |
return TI_NOK;
|
|
553 |
}
|
|
554 |
#endif
|
|
555 |
|
|
556 |
TRACE0(pHwInit->hReport, REPORT_SEVERITY_INIT, ".....HwInit configured successfully\n");
|
|
557 |
|
|
558 |
return TI_OK;
|
|
559 |
}
|
|
560 |
|
|
561 |
|
|
562 |
TI_STATUS hwInit_SetNvsImage (TI_HANDLE hHwInit, TI_UINT8 *pbuf, TI_UINT32 length)
|
|
563 |
{
|
|
564 |
THwInit *pHwInit = (THwInit *)hHwInit;
|
|
565 |
|
|
566 |
if (length == 0) {
|
|
567 |
TRACE0 (pHwInit->hReport, REPORT_SEVERITY_WARNING,"NVS File Length iz zero");
|
|
568 |
pHwInit->pEEPROMBuf = NULL;
|
|
569 |
return TI_OK;
|
|
570 |
}
|
|
571 |
/* We need to guarantee that the NVS buffer will be DMA'ble (physically continous) */
|
|
572 |
pHwInit->pEEPROMBuf = os_memoryAlloc (pHwInit->hOs, length, MemoryDMA);
|
|
573 |
|
|
574 |
if (pHwInit->pEEPROMBuf == NULL)
|
|
575 |
{
|
|
576 |
return TI_NOK;
|
|
577 |
}
|
|
578 |
|
|
579 |
os_memoryCopy(pHwInit->hOs, pHwInit->pEEPROMBuf, pbuf, length);
|
|
580 |
|
|
581 |
pHwInit->uEEPROMLen = length;
|
|
582 |
|
|
583 |
return TI_OK;
|
|
584 |
}
|
|
585 |
|
|
586 |
|
|
587 |
TI_STATUS hwInit_SetFwImage (TI_HANDLE hHwInit, TFileInfo *pFileInfo)
|
|
588 |
{
|
|
589 |
THwInit *pHwInit = (THwInit *)hHwInit;
|
|
590 |
|
|
591 |
if ((hHwInit == NULL) || (pFileInfo == NULL))
|
|
592 |
{
|
|
593 |
return TI_NOK;
|
|
594 |
}
|
|
595 |
|
|
596 |
pHwInit->pFwBuf = pFileInfo->pBuffer;
|
|
597 |
pHwInit->uFwLength = pFileInfo->uLength;
|
|
598 |
pHwInit->uFwAddress = pFileInfo->uAddress;
|
|
599 |
pHwInit->bFwBufLast = pFileInfo->bLast;
|
|
600 |
|
|
601 |
return TI_OK;
|
|
602 |
}
|
|
603 |
|
|
604 |
|
|
605 |
/**
|
|
606 |
* \fn hwInit_SetPartition
|
|
607 |
* \brief Set HW addresses partition
|
|
608 |
*
|
|
609 |
* Set the HW address ranges for download or working memory and registers access.
|
|
610 |
* Generate and configure the bus access address mapping table.
|
|
611 |
* The partition is split between register (fixed partition of 24KB size, exists in all modes),
|
|
612 |
* and memory (dynamically changed during init and gets constant value in run-time, 104KB size).
|
|
613 |
* The TwIf configures the memory mapping table on the device by issuing write transaction to
|
|
614 |
* table address (note that the TxnQ and bus driver see this as a regular transaction).
|
|
615 |
*
|
|
616 |
* \note In future versions, a specific bus may not support partitioning (as in wUART),
|
|
617 |
* In this case the HwInit module shall not call this function (will learn the bus
|
|
618 |
* configuration from the INI file).
|
|
619 |
*
|
|
620 |
* \param pHwInit - The module's object
|
|
621 |
* \param uMemAddr - The memory partition base address
|
|
622 |
* \param uMemSize - The memory partition size
|
|
623 |
* \param uRegAddr - The registers partition base address
|
|
624 |
* \param uRegSize - The register partition size
|
|
625 |
* \return void
|
|
626 |
* \sa
|
|
627 |
*/
|
|
628 |
static void hwInit_SetPartition (THwInit *pHwInit,
|
|
629 |
TPartition *pPartition)
|
|
630 |
{
|
|
631 |
TRACE7(pHwInit->hReport, REPORT_SEVERITY_INFORMATION, "hwInit_SetPartition: uMemAddr1=0x%x, MemSize1=0x%x uMemAddr2=0x%x, MemSize2=0x%x, uMemAddr3=0x%x, MemSize3=0x%x, uMemAddr4=0x%x, MemSize4=0x%x\n",pPartition[0].uMemAdrr, pPartition[0].uMemSize,pPartition[1].uMemAdrr, pPartition[1].uMemSize,pPartition[2].uMemAdrr, pPartition[2].uMemSize,pPartition[3].uMemAdrr );
|
|
632 |
|
|
633 |
/* Prepare partition Txn data and send to HW */
|
|
634 |
twIf_SetPartition (pHwInit->hTwIf,pPartition);
|
|
635 |
}
|
|
636 |
|
|
637 |
|
|
638 |
/****************************************************************************
|
|
639 |
* hwInit_Boot()
|
|
640 |
****************************************************************************
|
|
641 |
* DESCRIPTION: Start HW init sequence which writes and reads some HW registers
|
|
642 |
* that are needed prior to FW download.
|
|
643 |
*
|
|
644 |
* INPUTS: None
|
|
645 |
*
|
|
646 |
* OUTPUT: None
|
|
647 |
*
|
|
648 |
* RETURNS: TI_OK or TI_NOK
|
|
649 |
****************************************************************************/
|
|
650 |
TI_STATUS hwInit_Boot (TI_HANDLE hHwInit)
|
|
651 |
{
|
|
652 |
THwInit *pHwInit = (THwInit *)hHwInit;
|
|
653 |
TTwd *pTWD = (TTwd *)pHwInit->hTWD;
|
|
654 |
TWlanParams *pWlanParams = &DB_WLAN(pTWD->hCmdBld);
|
|
655 |
TBootAttr tBootAttr;
|
|
656 |
|
|
657 |
tBootAttr.MacClock = pWlanParams->MacClock;
|
|
658 |
tBootAttr.ArmClock = pWlanParams->ArmClock;
|
|
659 |
|
|
660 |
/*
|
|
661 |
* Initialize the status of download to pending
|
|
662 |
* It will be set to TXN_STATUS_COMPLETE at the FinalizeDownload function
|
|
663 |
*/
|
|
664 |
pHwInit->DownloadStatus = TXN_STATUS_PENDING;
|
|
665 |
|
|
666 |
/* Call the boot sequence state machine */
|
|
667 |
pHwInit->uInitStage = 0;
|
|
668 |
|
|
669 |
os_memoryCopy (pHwInit->hOs, &pHwInit->tBootAttr, &tBootAttr, sizeof(TBootAttr));
|
|
670 |
|
|
671 |
hwInit_BootSm (hHwInit);
|
|
672 |
|
|
673 |
/*
|
|
674 |
* If it returns the status of the StartInstance only then we can here query for the download status
|
|
675 |
* and then return the status up to the TNETW_Driver.
|
|
676 |
* This return value will go back up to the TNETW Driver layer so that the init from OS will know
|
|
677 |
* if to wait for the InitComplte or not in case of TXN_STATUS_ERROR.
|
|
678 |
* This value will always be pending since the SPI is ASYNC
|
|
679 |
* and in SDIOa timer is set so it will be ASync also in anyway.
|
|
680 |
*/
|
|
681 |
return pHwInit->DownloadStatus;
|
|
682 |
}
|
|
683 |
|
|
684 |
|
|
685 |
/****************************************************************************
|
|
686 |
* DESCRIPTION: Firmware boot state machine
|
|
687 |
*
|
|
688 |
* INPUTS:
|
|
689 |
*
|
|
690 |
* OUTPUT: None
|
|
691 |
*
|
|
692 |
* RETURNS: TI_OK
|
|
693 |
****************************************************************************/
|
|
694 |
static TI_STATUS hwInit_BootSm (TI_HANDLE hHwInit)
|
|
695 |
{
|
|
696 |
THwInit *pHwInit = (THwInit *)hHwInit;
|
|
697 |
TI_STATUS status = 0;
|
|
698 |
TTxnStruct *pTxn;
|
|
699 |
TI_UINT32 uData;
|
|
700 |
TTwd *pTWD = (TTwd *) pHwInit->hTWD;
|
|
701 |
IniFileGeneralParam *pGenParams = &DB_GEN(pTWD->hCmdBld);
|
|
702 |
TI_UINT32 clkVal = 0x3;
|
|
703 |
|
|
704 |
switch (pHwInit->uInitStage)
|
|
705 |
{
|
|
706 |
case 0:
|
|
707 |
pHwInit->uInitStage++;
|
|
708 |
pHwInit->uTxnIndex = 0;
|
|
709 |
SET_WORK_PARTITION(pHwInit->aPartition)
|
|
710 |
|
|
711 |
/* Set the bus addresses partition to its "running" mode */
|
|
712 |
hwInit_SetPartition (pHwInit,pHwInit->aPartition);
|
|
713 |
|
|
714 |
#ifdef _VLCT_
|
|
715 |
/* Set FW to test mode */
|
|
716 |
BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, SCR_PAD8, 0xBABABABE,
|
|
717 |
REGISTER_SIZE, TXN_DIRECTION_WRITE, NULL, NULL)
|
|
718 |
twIf_Transact(pHwInit->hTwIf, pTxn);
|
|
719 |
pHwInit->uTxnIndex++;
|
|
720 |
#endif
|
|
721 |
|
|
722 |
if (( 0 == (pGenParams->RefClk & FREF_CLK_FREQ_MASK)) || (2 == (pGenParams->RefClk & FREF_CLK_FREQ_MASK))
|
|
723 |
|| (4 == (pGenParams->RefClk & FREF_CLK_FREQ_MASK)))
|
|
724 |
{/* ref clk: 19.2/38.4/38.4-XTAL */
|
|
725 |
clkVal = 0x3;
|
|
726 |
}
|
|
727 |
if ((1 == (pGenParams->RefClk & FREF_CLK_FREQ_MASK)) || (3 == (pGenParams->RefClk & FREF_CLK_FREQ_MASK)))
|
|
728 |
{/* ref clk: 26/52 */
|
|
729 |
clkVal = 0x5;
|
|
730 |
}
|
|
731 |
|
|
732 |
WLAN_OS_REPORT(("CHIP VERSION... set 1273 chip top registers\n"));
|
|
733 |
|
|
734 |
/* set the reference clock freq' to be used (pll_selinpfref field) */
|
|
735 |
BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, PLL_PARAMETERS, clkVal,
|
|
736 |
REGISTER_SIZE, TXN_DIRECTION_WRITE, NULL, NULL)
|
|
737 |
twIf_Transact(pHwInit->hTwIf, pTxn);
|
|
738 |
|
|
739 |
pHwInit->uTxnIndex++;
|
|
740 |
|
|
741 |
/* read the PAUSE value to highest threshold */
|
|
742 |
BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, PLL_PARAMETERS, 0,
|
|
743 |
REGISTER_SIZE, TXN_DIRECTION_READ, (TTxnDoneCb)hwInit_BootSm, hHwInit)
|
|
744 |
status = twIf_Transact(pHwInit->hTwIf, pTxn);
|
|
745 |
|
|
746 |
EXCEPT (pHwInit, status)
|
|
747 |
|
|
748 |
case 1:
|
|
749 |
pHwInit->uInitStage ++;
|
|
750 |
/* We don't zero pHwInit->uTxnIndex at the begining because we need it's value to the next transaction */
|
|
751 |
uData = *((TI_UINT32*)(pHwInit->aHwInitTxn[pHwInit->uTxnIndex].pData));
|
|
752 |
if (uData == 0xFFFFFFFF)
|
|
753 |
{
|
|
754 |
TRACE0(pHwInit->hReport, REPORT_SEVERITY_ERROR , "hwInit_BootSm: Failed to read PLL parameters\n");
|
|
755 |
pHwInit->DownloadStatus = TXN_STATUS_ERROR;
|
|
756 |
TWD_FinalizeOnFailure (pHwInit->hTWD);
|
|
757 |
return TXN_STATUS_ERROR;
|
|
758 |
}
|
|
759 |
else
|
|
760 |
{
|
|
761 |
uData &= ~(0x3ff);
|
|
762 |
}
|
|
763 |
|
|
764 |
/* Now we can zero the index */
|
|
765 |
pHwInit->uTxnIndex = 0;
|
|
766 |
|
|
767 |
/* set the the PAUSE value to highest threshold */
|
|
768 |
uData |= WU_COUNTER_PAUSE_VAL;
|
|
769 |
BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, WU_COUNTER_PAUSE, uData,
|
|
770 |
REGISTER_SIZE, TXN_DIRECTION_WRITE, NULL, NULL)
|
|
771 |
twIf_Transact(pHwInit->hTwIf, pTxn);
|
|
772 |
|
|
773 |
pHwInit->uTxnIndex++;
|
|
774 |
|
|
775 |
/* Continue the ELP wake up sequence */
|
|
776 |
BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL,
|
|
777 |
REGISTER_SIZE, TXN_DIRECTION_WRITE, NULL, NULL)
|
|
778 |
twIf_Transact(pHwInit->hTwIf, pTxn);
|
|
779 |
|
|
780 |
/* Wait 500uS */
|
|
781 |
os_StalluSec (pHwInit->hOs, 500);
|
|
782 |
|
|
783 |
SET_DRP_PARTITION(pHwInit->aPartition)
|
|
784 |
/* Set the bus addresses partition to DRPw registers region */
|
|
785 |
hwInit_SetPartition (pHwInit,pHwInit->aPartition);
|
|
786 |
|
|
787 |
pHwInit->uTxnIndex++;
|
|
788 |
|
|
789 |
/* Read-modify-write DRPW_SCRATCH_START register (see next state) to be used by DRPw FW.
|
|
790 |
The RTRIM value will be added by the FW before taking DRPw out of reset */
|
|
791 |
BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, DRPW_SCRATCH_START, 0,
|
|
792 |
REGISTER_SIZE, TXN_DIRECTION_READ,(TTxnDoneCb)hwInit_BootSm, hHwInit)
|
|
793 |
status = twIf_Transact(pHwInit->hTwIf, pTxn);
|
|
794 |
|
|
795 |
EXCEPT (pHwInit, status)
|
|
796 |
|
|
797 |
case 2:
|
|
798 |
pHwInit->uInitStage ++;
|
|
799 |
|
|
800 |
/* multiply fref value by 2, so that {0,1,2,3} values will become {0,2,4,6} */
|
|
801 |
/* Then, move it 4 places to the right, to alter Fref relevant bits in register 0x2c */
|
|
802 |
clkVal = *((TI_UINT32*)(pHwInit->aHwInitTxn[pHwInit->uTxnIndex].pData));
|
|
803 |
pHwInit->uTxnIndex = 0; /* Reset index only after getting the last read value! */
|
|
804 |
clkVal |= (pGenParams->RefClk << 1) << 4;
|
|
805 |
|
|
806 |
/* Disable LPD mode */
|
|
807 |
clkVal &= 0xf9ffffff;
|
|
808 |
BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, DRPW_SCRATCH_START, clkVal,
|
|
809 |
REGISTER_SIZE, TXN_DIRECTION_WRITE, NULL, NULL)
|
|
810 |
twIf_Transact(pHwInit->hTwIf, pTxn);
|
|
811 |
|
|
812 |
pHwInit->uTxnIndex++;
|
|
813 |
|
|
814 |
SET_WORK_PARTITION(pHwInit->aPartition)
|
|
815 |
/* Set the bus addresses partition back to its "running" mode */
|
|
816 |
hwInit_SetPartition (pHwInit,pHwInit->aPartition);
|
|
817 |
|
|
818 |
/*
|
|
819 |
* end of CHIP init seq.
|
|
820 |
*/
|
|
821 |
|
|
822 |
/* Disable interrupts */
|
|
823 |
BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, ACX_REG_INTERRUPT_MASK, ACX_INTR_ALL,
|
|
824 |
REGISTER_SIZE, TXN_DIRECTION_WRITE, NULL, NULL)
|
|
825 |
twIf_Transact(pHwInit->hTwIf, pTxn);
|
|
826 |
|
|
827 |
pHwInit->uTxnIndex++;
|
|
828 |
|
|
829 |
/* Read the CHIP ID to get an indication that the bus is TI_OK */
|
|
830 |
BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, CHIP_ID, 0,
|
|
831 |
REGISTER_SIZE, TXN_DIRECTION_READ,(TTxnDoneCb)hwInit_BootSm, hHwInit)
|
|
832 |
status = twIf_Transact(pHwInit->hTwIf, pTxn);
|
|
833 |
|
|
834 |
EXCEPT (pHwInit, status)
|
|
835 |
|
|
836 |
case 3:
|
|
837 |
pHwInit->uInitStage ++;
|
|
838 |
|
|
839 |
/* We don't zero pHwInit->uTxnIndex at the begining because we need it's value to the next transaction */
|
|
840 |
pHwInit->uChipId = *((TI_UINT32*)(pHwInit->aHwInitTxn[pHwInit->uTxnIndex].pData));
|
|
841 |
|
|
842 |
/* This is only sanity check that the HW exists, we can continue and fail on FwLoad */
|
|
843 |
if (pHwInit->uChipId == CHIP_ID_1273_PG10)
|
|
844 |
{
|
|
845 |
WLAN_OS_REPORT(("Working on a 1273 PG 1.0 board.\n"));
|
|
846 |
}
|
|
847 |
else if (pHwInit->uChipId == CHIP_ID_1273_PG20)
|
|
848 |
{
|
|
849 |
WLAN_OS_REPORT(("Working on a 1273 PG 2.0 board.\n"));
|
|
850 |
}
|
|
851 |
else
|
|
852 |
{
|
|
853 |
WLAN_OS_REPORT (("Error!! Found unknown Chip Id = 0x%x\n", pHwInit->uChipId));
|
|
854 |
|
|
855 |
/*
|
|
856 |
* NOTE: no exception because of forward compatibility
|
|
857 |
*/
|
|
858 |
}
|
|
859 |
|
|
860 |
/*
|
|
861 |
* Soft reset
|
|
862 |
*/
|
|
863 |
pHwInit->uResetStage = 0;
|
|
864 |
pHwInit->uSelfClearTime = 0;
|
|
865 |
pHwInit->uBootData = 0;
|
|
866 |
status = hwInit_ResetSm (pHwInit);
|
|
867 |
|
|
868 |
EXCEPT (pHwInit, status)
|
|
869 |
|
|
870 |
case 4:
|
|
871 |
pHwInit->uInitStage ++;
|
|
872 |
|
|
873 |
TRACE0(pHwInit->hReport, REPORT_SEVERITY_INIT , "TNET SOFT-RESET\n");
|
|
874 |
|
|
875 |
WLAN_OS_REPORT(("Starting to process NVS...\n"));
|
|
876 |
|
|
877 |
/*
|
|
878 |
* Start EEPROM/NVS burst
|
|
879 |
*/
|
|
880 |
|
|
881 |
if (pHwInit->pEEPROMBuf)
|
|
882 |
{
|
|
883 |
/* NVS file exists (EEPROM-less support) */
|
|
884 |
pHwInit->uEEPROMCurLen = pHwInit->uEEPROMLen;
|
|
885 |
|
|
886 |
TRACE2(pHwInit->hReport, REPORT_SEVERITY_INIT , "EEPROM Image addr=0x%x, EEPROM Len=0x0x%x\n", pHwInit->pEEPROMBuf, pHwInit->uEEPROMLen);
|
|
887 |
WLAN_OS_REPORT (("NVS found, EEPROM Image addr=0x%x, EEPROM Len=0x0x%x\n",
|
|
888 |
pHwInit->pEEPROMBuf, pHwInit->uEEPROMLen));
|
|
889 |
}
|
|
890 |
else
|
|
891 |
{
|
|
892 |
WLAN_OS_REPORT (("No Nvs, Setting default MAC address\n"));
|
|
893 |
pHwInit->uEEPROMCurLen = DEF_NVS_SIZE;
|
|
894 |
pHwInit->pEEPROMBuf = (TI_UINT8*)(&pHwInit->aDefaultNVS[0]);
|
|
895 |
WLAN_OS_REPORT (("pHwInit->uEEPROMCurLen: %x\n", pHwInit->uEEPROMCurLen));
|
|
896 |
WLAN_OS_REPORT (("ERROR: If you are not calibating the device, you will soon get errors !!!\n"));
|
|
897 |
|
|
898 |
}
|
|
899 |
|
|
900 |
pHwInit->pEEPROMCurPtr = pHwInit->pEEPROMBuf;
|
|
901 |
pHwInit->uEEPROMStage = 0;
|
|
902 |
status = hwInit_EepromlessStartBurstSm (hHwInit);
|
|
903 |
|
|
904 |
EXCEPT (pHwInit, status)
|
|
905 |
|
|
906 |
case 5:
|
|
907 |
pHwInit->uInitStage ++;
|
|
908 |
pHwInit->uTxnIndex = 0;
|
|
909 |
|
|
910 |
if (pHwInit->pEEPROMBuf)
|
|
911 |
{
|
|
912 |
/* Signal FW that we are eeprom less */
|
|
913 |
BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, ACX_EEPROMLESS_IND_REG, ACX_EEPROMLESS_IND_REG,
|
|
914 |
REGISTER_SIZE, TXN_DIRECTION_WRITE, NULL, NULL)
|
|
915 |
twIf_Transact(pHwInit->hTwIf, pTxn);
|
|
916 |
|
|
917 |
TRACE0(pHwInit->hReport, REPORT_SEVERITY_INIT , "DRIVER NVS BURST-READ\n");
|
|
918 |
}
|
|
919 |
else
|
|
920 |
{
|
|
921 |
/* 1273 - EEPROM is not support by FPGA yet */
|
|
922 |
/*
|
|
923 |
* Start ACX EEPROM
|
|
924 |
*/
|
|
925 |
/*pHwInit->uRegister = START_EEPROM_MGR;
|
|
926 |
TXN_PARAM_SET(pTxn, TXN_LOW_PRIORITY, TXN_FUNC_ID_WLAN, TXN_DIRECTION_WRITE, TXN_INC_ADDR)
|
|
927 |
BUILD_TTxnStruct(pTxn, ACX_REG_EE_START, &pHwInit->uRegister, REGISTER_SIZE, 0, NULL, NULL)
|
|
928 |
twIf_Transact(pHwInit->hTwIf, pTxn);*/
|
|
929 |
|
|
930 |
/*
|
|
931 |
* The stall is needed so the EEPROM NVS burst read will complete
|
|
932 |
*/
|
|
933 |
os_StalluSec (pHwInit->hOs, 40000);
|
|
934 |
|
|
935 |
BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, ACX_EEPROMLESS_IND_REG, USE_EEPROM,
|
|
936 |
REGISTER_SIZE, TXN_DIRECTION_WRITE, NULL, NULL)
|
|
937 |
twIf_Transact(pHwInit->hTwIf, pTxn);
|
|
938 |
|
|
939 |
TRACE0(pHwInit->hReport, REPORT_SEVERITY_INIT , "STARTING EEPROM NVS BURST-READ\n");
|
|
940 |
}
|
|
941 |
|
|
942 |
pHwInit->uTxnIndex++;
|
|
943 |
|
|
944 |
/* Read Chip ID */
|
|
945 |
BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, CHIP_ID, 0,
|
|
946 |
REGISTER_SIZE, TXN_DIRECTION_READ,(TTxnDoneCb)hwInit_BootSm, hHwInit)
|
|
947 |
status = twIf_Transact(pHwInit->hTwIf, pTxn);
|
|
948 |
|
|
949 |
EXCEPT (pHwInit, status)
|
|
950 |
|
|
951 |
case 6:
|
|
952 |
pHwInit->uInitStage ++;
|
|
953 |
/* We don't zero pHwInit->uTxnIndex at the begining because we need it's value to the next transaction */
|
|
954 |
pHwInit->uBootData = *((TI_UINT32*)(pHwInit->aHwInitTxn[pHwInit->uTxnIndex].pData));
|
|
955 |
/* Now we can zero the index */
|
|
956 |
pHwInit->uTxnIndex = 0;
|
|
957 |
|
|
958 |
WLAN_OS_REPORT(("Chip ID is 0x%X.\n", pHwInit->uBootData));
|
|
959 |
|
|
960 |
/* Read Scr2 to verify that the HW is ready */
|
|
961 |
BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, SCR_PAD2, 0,
|
|
962 |
REGISTER_SIZE, TXN_DIRECTION_READ,(TTxnDoneCb)hwInit_BootSm, hHwInit)
|
|
963 |
status = twIf_Transact(pHwInit->hTwIf, pTxn);
|
|
964 |
EXCEPT (pHwInit, status)
|
|
965 |
|
|
966 |
case 7:
|
|
967 |
pHwInit->uInitStage ++;
|
|
968 |
|
|
969 |
/* We don't zero pHwInit->uTxnIndex at the begining because we need it's value to the next transaction */
|
|
970 |
pHwInit->uBootData = *((TI_UINT32*)(pHwInit->aHwInitTxn[pHwInit->uTxnIndex].pData));
|
|
971 |
|
|
972 |
if (pHwInit->uBootData == 0xffffffff)
|
|
973 |
{
|
|
974 |
TRACE0(pHwInit->hReport, REPORT_SEVERITY_FATAL_ERROR , "Error in SCR_PAD2 register\n");
|
|
975 |
EXCEPT (pHwInit, TXN_STATUS_ERROR)
|
|
976 |
}
|
|
977 |
|
|
978 |
/* Call the restart sequence */
|
|
979 |
pHwInit->uInitSeqStage = 0;
|
|
980 |
pHwInit->uInitSeqStatus = TXN_STATUS_COMPLETE;
|
|
981 |
|
|
982 |
EXCEPT (pHwInit, status)
|
|
983 |
|
|
984 |
|
|
985 |
case 8:
|
|
986 |
pHwInit->uInitStage++;
|
|
987 |
|
|
988 |
if ((pGenParams->RefClk & FREF_CLK_TYPE_MASK) != 0x0)
|
|
989 |
{
|
|
990 |
status = hwInit_InitTopRegisterRead(hHwInit, 0x448);
|
|
991 |
EXCEPT (pHwInit, status)
|
|
992 |
}
|
|
993 |
|
|
994 |
case 9:
|
|
995 |
pHwInit->uInitStage++;
|
|
996 |
|
|
997 |
if ((pGenParams->RefClk & FREF_CLK_TYPE_MASK) != 0x0)
|
|
998 |
{
|
|
999 |
pHwInit->uTopRegValue &= FREF_CLK_TYPE_BITS;
|
|
1000 |
pHwInit->uTopRegValue |= CLK_REQ_PRCM;
|
|
1001 |
|
|
1002 |
status = hwInit_InitTopRegisterWrite( hHwInit, 0x448, pHwInit->uTopRegValue);
|
|
1003 |
EXCEPT (pHwInit, status)
|
|
1004 |
}
|
|
1005 |
|
|
1006 |
case 10:
|
|
1007 |
pHwInit->uInitStage++;
|
|
1008 |
|
|
1009 |
if ((pGenParams->RefClk & FREF_CLK_POLARITY_MASK) == 0x0)
|
|
1010 |
{
|
|
1011 |
status = hwInit_InitTopRegisterRead(hHwInit, 0xCB2);
|
|
1012 |
EXCEPT (pHwInit, status)
|
|
1013 |
}
|
|
1014 |
|
|
1015 |
case 11:
|
|
1016 |
pHwInit->uInitStage++;
|
|
1017 |
if ((pGenParams->RefClk & FREF_CLK_POLARITY_MASK) == 0x0)
|
|
1018 |
{
|
|
1019 |
pHwInit->uTopRegValue &= FREF_CLK_POLARITY_BITS;
|
|
1020 |
pHwInit->uTopRegValue |= CLK_REQ_OUTN_SEL;
|
|
1021 |
|
|
1022 |
status = hwInit_InitTopRegisterWrite( hHwInit, 0xCB2, pHwInit->uTopRegValue);
|
|
1023 |
EXCEPT (pHwInit, status)
|
|
1024 |
}
|
|
1025 |
|
|
1026 |
case 12:
|
|
1027 |
pHwInit->uInitStage = 0;
|
|
1028 |
|
|
1029 |
/* Set the Download Status to COMPLETE */
|
|
1030 |
pHwInit->DownloadStatus = TXN_STATUS_COMPLETE;
|
|
1031 |
|
|
1032 |
/* Call upper layer callback */
|
|
1033 |
if (pHwInit->fInitHwCb)
|
|
1034 |
{
|
|
1035 |
(*pHwInit->fInitHwCb) (pHwInit->hTWD);
|
|
1036 |
}
|
|
1037 |
|
|
1038 |
return TI_OK;
|
|
1039 |
}
|
|
1040 |
|
|
1041 |
return TI_OK;
|
|
1042 |
}
|
|
1043 |
|
|
1044 |
|
|
1045 |
TI_STATUS hwInit_LoadFw (TI_HANDLE hHwInit)
|
|
1046 |
{
|
|
1047 |
THwInit *pHwInit = (THwInit *)hHwInit;
|
|
1048 |
TI_STATUS status;
|
|
1049 |
|
|
1050 |
/* check parameters */
|
|
1051 |
if (hHwInit == NULL)
|
|
1052 |
{
|
|
1053 |
EXCEPT (pHwInit, TXN_STATUS_ERROR)
|
|
1054 |
}
|
|
1055 |
|
|
1056 |
if (pHwInit->pFwBuf)
|
|
1057 |
{
|
|
1058 |
TRACE0(pHwInit->hReport, REPORT_SEVERITY_INIT , "CPU halt -> download code\n");
|
|
1059 |
|
|
1060 |
/* Load firmware image */
|
|
1061 |
pHwInit->uLoadStage = 0;
|
|
1062 |
status = hwInit_LoadFwImageSm (pHwInit);
|
|
1063 |
|
|
1064 |
switch (status)
|
|
1065 |
{
|
|
1066 |
case TI_OK:
|
|
1067 |
case TXN_STATUS_OK:
|
|
1068 |
case TXN_STATUS_COMPLETE:
|
|
1069 |
WLAN_OS_REPORT (("Firmware successfully downloaded.\n"));
|
|
1070 |
break;
|
|
1071 |
case TXN_STATUS_PENDING:
|
|
1072 |
WLAN_OS_REPORT (("Starting to download firmware...\n"));
|
|
1073 |
break;
|
|
1074 |
default:
|
|
1075 |
TRACE0(pHwInit->hReport, REPORT_SEVERITY_ERROR , "Firmware download failed!\n");
|
|
1076 |
break;
|
|
1077 |
}
|
|
1078 |
|
|
1079 |
EXCEPT (pHwInit, status);
|
|
1080 |
}
|
|
1081 |
else
|
|
1082 |
{
|
|
1083 |
TRACE0(pHwInit->hReport, REPORT_SEVERITY_INIT , "Firmware not downloaded...\n");
|
|
1084 |
|
|
1085 |
EXCEPT (pHwInit, TXN_STATUS_ERROR)
|
|
1086 |
}
|
|
1087 |
|
|
1088 |
WLAN_OS_REPORT (("FW download OK...\n"));
|
|
1089 |
return TI_OK;
|
|
1090 |
}
|
|
1091 |
|
|
1092 |
|
|
1093 |
/****************************************************************************
|
|
1094 |
* hwInit_FinalizeDownloadSm()
|
|
1095 |
****************************************************************************
|
|
1096 |
* DESCRIPTION: Run the Hardware firmware
|
|
1097 |
* Wait for Init Complete
|
|
1098 |
* Configure the Bus Access with Addresses available on the scratch pad register
|
|
1099 |
* Change the SDIO/SPI partitions to be able to see all the memory addresses
|
|
1100 |
*
|
|
1101 |
* INPUTS: None
|
|
1102 |
*
|
|
1103 |
* OUTPUT: None
|
|
1104 |
*
|
|
1105 |
* RETURNS: None
|
|
1106 |
****************************************************************************/
|
|
1107 |
static TI_STATUS hwInit_FinalizeDownloadSm (TI_HANDLE hHwInit)
|
|
1108 |
{
|
|
1109 |
THwInit *pHwInit = (THwInit *)hHwInit;
|
|
1110 |
TTwd *pTWD = (TTwd *)pHwInit->hTWD;
|
|
1111 |
TI_STATUS status = TI_OK;
|
|
1112 |
TI_UINT32 uIntVect;
|
|
1113 |
TTxnStruct* pTxn;
|
|
1114 |
|
|
1115 |
while (TI_TRUE)
|
|
1116 |
{
|
|
1117 |
switch (pHwInit->uFinStage)
|
|
1118 |
{
|
|
1119 |
case 0:
|
|
1120 |
pHwInit->uFinStage = 1;
|
|
1121 |
pHwInit->uTxnIndex = 0;
|
|
1122 |
/*
|
|
1123 |
* Run the firmware (I) - Read current value from ECPU Control Reg.
|
|
1124 |
*/
|
|
1125 |
BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, ACX_REG_ECPU_CONTROL, 0,
|
|
1126 |
REGISTER_SIZE, TXN_DIRECTION_READ, (TTxnDoneCb)hwInit_FinalizeDownloadSm, hHwInit)
|
|
1127 |
status = twIf_Transact(pHwInit->hTwIf, pTxn);
|
|
1128 |
|
|
1129 |
EXCEPT (pHwInit, status)
|
|
1130 |
|
|
1131 |
case 1:
|
|
1132 |
pHwInit->uFinStage ++;
|
|
1133 |
/* We don't zero pHwInit->uTxnIndex at the begining because we need it's value to the next transaction */
|
|
1134 |
pHwInit->uFinData = *((TI_UINT32*)(pHwInit->aHwInitTxn[pHwInit->uTxnIndex].pData));
|
|
1135 |
/* Now we can zero the index */
|
|
1136 |
pHwInit->uTxnIndex = 0;
|
|
1137 |
|
|
1138 |
/*
|
|
1139 |
* Run the firmware (II) - Take HW out of reset (write ECPU_CONTROL_HALT to ECPU Control Reg.)
|
|
1140 |
*/
|
|
1141 |
BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, ACX_REG_ECPU_CONTROL, (pHwInit->uFinData | ECPU_CONTROL_HALT),
|
|
1142 |
REGISTER_SIZE, TXN_DIRECTION_WRITE, NULL, NULL)
|
|
1143 |
twIf_Transact(pHwInit->hTwIf, pTxn);
|
|
1144 |
|
|
1145 |
WLAN_OS_REPORT (("Firmware running.\n"));
|
|
1146 |
|
|
1147 |
/*
|
|
1148 |
* CHIP ID Debug
|
|
1149 |
*/
|
|
1150 |
|
|
1151 |
pHwInit->uTxnIndex++;
|
|
1152 |
|
|
1153 |
BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, CHIP_ID, 0,
|
|
1154 |
REGISTER_SIZE, TXN_DIRECTION_READ, (TTxnDoneCb)hwInit_FinalizeDownloadSm, hHwInit)
|
|
1155 |
status = twIf_Transact(pHwInit->hTwIf, pTxn);
|
|
1156 |
|
|
1157 |
EXCEPT (pHwInit, status)
|
|
1158 |
|
|
1159 |
case 2:
|
|
1160 |
pHwInit->uFinStage ++;
|
|
1161 |
pHwInit->uFinLoop = 0;
|
|
1162 |
|
|
1163 |
/* We don't zero pHwInit->uTxnIndex at the begining because we need it's value to the next transaction */
|
|
1164 |
pHwInit->uFinData = *((TI_UINT32*)(pHwInit->aHwInitTxn[pHwInit->uTxnIndex].pData));
|
|
1165 |
|
|
1166 |
TRACE1(pHwInit->hReport, REPORT_SEVERITY_INIT , "CHIP ID IS %x\n", pHwInit->uFinData);
|
|
1167 |
|
|
1168 |
TRACE0(pHwInit->hReport, REPORT_SEVERITY_INIT , "Wait init complete\n");
|
|
1169 |
|
|
1170 |
case 3:
|
|
1171 |
pHwInit->uTxnIndex = 0;
|
|
1172 |
|
|
1173 |
/*
|
|
1174 |
* Wait for init complete
|
|
1175 |
*/
|
|
1176 |
if (pHwInit->uFinLoop < FIN_LOOP)
|
|
1177 |
{
|
|
1178 |
pHwInit->uFinStage = 4;
|
|
1179 |
|
|
1180 |
#ifdef _VLCT_
|
|
1181 |
os_StalluSec (pHwInit->hOs, 50);*/
|
|
1182 |
#endif
|
|
1183 |
|
|
1184 |
/* Read interrupt status register */
|
|
1185 |
BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, ACX_REG_INTERRUPT_NO_CLEAR, 0,
|
|
1186 |
REGISTER_SIZE, TXN_DIRECTION_READ, (TTxnDoneCb)hwInit_FinalizeDownloadSm, hHwInit)
|
|
1187 |
status = twIf_Transact(pHwInit->hTwIf, pTxn);
|
|
1188 |
|
|
1189 |
EXCEPT (pHwInit, status)
|
|
1190 |
}
|
|
1191 |
else
|
|
1192 |
{
|
|
1193 |
pHwInit->uFinStage = 5;
|
|
1194 |
}
|
|
1195 |
continue;
|
|
1196 |
|
|
1197 |
case 4:
|
|
1198 |
/* We don't zero pHwInit->uTxnIndex at the begining because we need it's value to the next transaction */
|
|
1199 |
pHwInit->uFinData = *((TI_UINT32*)(pHwInit->aHwInitTxn[pHwInit->uTxnIndex].pData));
|
|
1200 |
/* Now we can zero the index */
|
|
1201 |
pHwInit->uTxnIndex = 0;
|
|
1202 |
|
|
1203 |
if (pHwInit->uFinData == 0xffffffff) /* error */
|
|
1204 |
{
|
|
1205 |
TRACE0(pHwInit->hReport, REPORT_SEVERITY_ERROR , "Error reading hardware complete init indication\n");
|
|
1206 |
|
|
1207 |
pHwInit->DownloadStatus = TXN_STATUS_ERROR;
|
|
1208 |
EXCEPT (pHwInit, TXN_STATUS_ERROR)
|
|
1209 |
}
|
|
1210 |
|
|
1211 |
if (IS_MASK_ON (pHwInit->uFinData, ACX_INTR_INIT_COMPLETE))
|
|
1212 |
{
|
|
1213 |
pHwInit->uFinStage = 5;
|
|
1214 |
|
|
1215 |
/* Interrupt ACK */
|
|
1216 |
BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, ACX_REG_INTERRUPT_ACK, ACX_INTR_INIT_COMPLETE,
|
|
1217 |
REGISTER_SIZE, TXN_DIRECTION_WRITE, NULL, NULL)
|
|
1218 |
twIf_Transact(pHwInit->hTwIf, pTxn);
|
|
1219 |
|
|
1220 |
break;
|
|
1221 |
}
|
|
1222 |
else
|
|
1223 |
{
|
|
1224 |
pHwInit->uFinStage = 3;
|
|
1225 |
pHwInit->uFinLoop ++;
|
|
1226 |
|
|
1227 |
#ifndef _VLCT_
|
|
1228 |
os_timerStart (pHwInit->hOs, pHwInit->hStallTimer, STALL_TIMEOUT);
|
|
1229 |
return TI_PENDING;
|
|
1230 |
#endif
|
|
1231 |
}
|
|
1232 |
#ifdef _VLCT_
|
|
1233 |
continue;
|
|
1234 |
#endif
|
|
1235 |
|
|
1236 |
case 5:
|
|
1237 |
pHwInit->uFinStage++;
|
|
1238 |
|
|
1239 |
if (pHwInit->uFinLoop >= FIN_LOOP)
|
|
1240 |
{
|
|
1241 |
TRACE0(pHwInit->hReport, REPORT_SEVERITY_ERROR , "Timeout waiting for the hardware to complete initialization\n");
|
|
1242 |
|
|
1243 |
pHwInit->DownloadStatus = TXN_STATUS_ERROR;
|
|
1244 |
EXCEPT (pHwInit, TXN_STATUS_ERROR);
|
|
1245 |
}
|
|
1246 |
|
|
1247 |
TRACE0(pHwInit->hReport, REPORT_SEVERITY_INIT , "Firmware init complete...\n");
|
|
1248 |
|
|
1249 |
/*
|
|
1250 |
* There are valid addresses of the command and event mailbox
|
|
1251 |
* on the scratch pad registers
|
|
1252 |
*/
|
|
1253 |
/* Hardware config command mail box */
|
|
1254 |
status = cmdMbox_ConfigHw (pTWD->hCmdMbox,
|
|
1255 |
(fnotify_t)hwInit_FinalizeDownloadSm,
|
|
1256 |
hHwInit);
|
|
1257 |
EXCEPT (pHwInit, status)
|
|
1258 |
|
|
1259 |
case 6:
|
|
1260 |
pHwInit->uFinStage++;
|
|
1261 |
|
|
1262 |
/* Hardware config event mail box */
|
|
1263 |
status = eventMbox_InitMboxAddr (pTWD->hEventMbox,
|
|
1264 |
(fnotify_t)hwInit_FinalizeDownloadSm,
|
|
1265 |
hHwInit);
|
|
1266 |
EXCEPT (pHwInit, status);
|
|
1267 |
|
|
1268 |
case 7:
|
|
1269 |
pHwInit->uFinStage++;
|
|
1270 |
pHwInit->uTxnIndex = 0;
|
|
1271 |
|
|
1272 |
SET_WORK_PARTITION(pHwInit->aPartition)
|
|
1273 |
/* Set the bus addresses partition to its "running" mode */
|
|
1274 |
hwInit_SetPartition (pHwInit,pHwInit->aPartition);
|
|
1275 |
|
|
1276 |
/*
|
|
1277 |
* In case of full asynchronous mode the firmware event must be ready
|
|
1278 |
* to receive event from the command mailbox
|
|
1279 |
*/
|
|
1280 |
|
|
1281 |
uIntVect = fwEvent_GetInitMask (pTWD->hFwEvent);
|
|
1282 |
|
|
1283 |
/* Clearing all the interrupt status register sources */
|
|
1284 |
BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, ACX_REG_INTERRUPT_MASK, (~uIntVect),
|
|
1285 |
REGISTER_SIZE, TXN_DIRECTION_WRITE, NULL, NULL)
|
|
1286 |
twIf_Transact(pHwInit->hTwIf, pTxn);
|
|
1287 |
|
|
1288 |
|
|
1289 |
pHwInit->uTxnIndex++;
|
|
1290 |
|
|
1291 |
BUILD_HW_INIT_FW_STATIC_TXN(pHwInit, pTxn, cmdMbox_GetMboxAddress (pTWD->hCmdMbox),
|
|
1292 |
(TTxnDoneCb)hwInit_FinalizeDownloadSm, hHwInit)
|
|
1293 |
status = twIf_Transact(pHwInit->hTwIf, pTxn);
|
|
1294 |
|
|
1295 |
EXCEPT (pHwInit, status);
|
|
1296 |
continue;
|
|
1297 |
|
|
1298 |
case 8:
|
|
1299 |
|
|
1300 |
pHwInit->uFinStage = 0;
|
|
1301 |
|
|
1302 |
cmdBld_FinalizeDownload (pTWD->hCmdBld, &pHwInit->tBootAttr, (FwStaticData_t *)(pHwInit->tFwStaticTxn.pFwStaticInfo));
|
|
1303 |
|
|
1304 |
/* Set the Download Status to COMPLETE */
|
|
1305 |
pHwInit->DownloadStatus = TXN_STATUS_COMPLETE;
|
|
1306 |
|
|
1307 |
return TXN_STATUS_COMPLETE;
|
|
1308 |
|
|
1309 |
} /* End switch */
|
|
1310 |
|
|
1311 |
} /* End while */
|
|
1312 |
|
|
1313 |
}
|
|
1314 |
|
|
1315 |
|
|
1316 |
/****************************************************************************
|
|
1317 |
* hwInit_ResetSm()
|
|
1318 |
****************************************************************************
|
|
1319 |
* DESCRIPTION: Reset hardware state machine
|
|
1320 |
*
|
|
1321 |
* INPUTS: None
|
|
1322 |
*
|
|
1323 |
* OUTPUT: None
|
|
1324 |
*
|
|
1325 |
* RETURNS: TI_OK or TI_NOK
|
|
1326 |
****************************************************************************/
|
|
1327 |
static TI_STATUS hwInit_ResetSm (TI_HANDLE hHwInit)
|
|
1328 |
{
|
|
1329 |
THwInit *pHwInit = (THwInit *)hHwInit;
|
|
1330 |
TI_STATUS status = TI_OK;
|
|
1331 |
TTxnStruct* pTxn;
|
|
1332 |
|
|
1333 |
pHwInit->uTxnIndex = 0;
|
|
1334 |
|
|
1335 |
/* Disable Rx/Tx */
|
|
1336 |
BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, REG_ENABLE_TX_RX, 0x0,
|
|
1337 |
REGISTER_SIZE, TXN_DIRECTION_WRITE, NULL, NULL)
|
|
1338 |
twIf_Transact(pHwInit->hTwIf, pTxn);
|
|
1339 |
|
|
1340 |
pHwInit->uTxnIndex++;
|
|
1341 |
|
|
1342 |
/* Disable auto calibration on start */
|
|
1343 |
BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, SPARE_A2, 0xFFFF,
|
|
1344 |
REGISTER_SIZE, TXN_DIRECTION_WRITE,(TTxnDoneCb)hwInit_BootSm, hHwInit)
|
|
1345 |
status = twIf_Transact(pHwInit->hTwIf, pTxn);
|
|
1346 |
|
|
1347 |
return status;
|
|
1348 |
}
|
|
1349 |
|
|
1350 |
|
|
1351 |
/****************************************************************************
|
|
1352 |
* hwInit_EepromlessStartBurstSm()
|
|
1353 |
****************************************************************************
|
|
1354 |
* DESCRIPTION: prepare eepromless configuration before boot
|
|
1355 |
*
|
|
1356 |
* INPUTS:
|
|
1357 |
*
|
|
1358 |
* OUTPUT:
|
|
1359 |
*
|
|
1360 |
* RETURNS:
|
|
1361 |
****************************************************************************/
|
|
1362 |
static TI_STATUS hwInit_EepromlessStartBurstSm (TI_HANDLE hHwInit)
|
|
1363 |
{
|
|
1364 |
THwInit *pHwInit = (THwInit *)hHwInit;
|
|
1365 |
TI_STATUS status = TI_OK;
|
|
1366 |
TI_UINT8 *uAddr;
|
|
1367 |
TI_UINT32 uDeltaLength;
|
|
1368 |
TTxnStruct* pTxn;
|
|
1369 |
|
|
1370 |
pHwInit->uTxnIndex = 0;
|
|
1371 |
|
|
1372 |
while (TI_TRUE)
|
|
1373 |
{
|
|
1374 |
switch (pHwInit->uEEPROMStage)
|
|
1375 |
{
|
|
1376 |
/*
|
|
1377 |
* Stages 0, 1 handles the eeprom format parameters:
|
|
1378 |
* ------------------------------------------------
|
|
1379 |
* Length - 8bit --> The length is counted in 32bit words
|
|
1380 |
* Address - 16bit
|
|
1381 |
* Data - (Length * 4) bytes
|
|
1382 |
*
|
|
1383 |
* Note: The nvs is in big endian format and we need to change it to little endian
|
|
1384 |
*/
|
|
1385 |
case 0:
|
|
1386 |
/* Check if address LSB = 1 --> Register address */
|
|
1387 |
if ((pHwInit->uEEPROMRegAddr = pHwInit->pEEPROMCurPtr[1]) & 1)
|
|
1388 |
{
|
|
1389 |
/* Mask the register's address LSB before writing to it */
|
|
1390 |
pHwInit->uEEPROMRegAddr &= 0xfe;
|
|
1391 |
/* Change the address's endian */
|
|
1392 |
pHwInit->uEEPROMRegAddr |= (TI_UINT32)pHwInit->pEEPROMCurPtr[2] << 8;
|
|
1393 |
/* Length of burst data */
|
|
1394 |
pHwInit->uEEPROMBurstLen = pHwInit->pEEPROMCurPtr[0];
|
|
1395 |
pHwInit->pEEPROMCurPtr += 3;
|
|
1396 |
pHwInit->uEEPROMBurstLoop = 0;
|
|
1397 |
/*
|
|
1398 |
* We've finished reading the burst information.
|
|
1399 |
* Go to stage 1 in order to write it
|
|
1400 |
*/
|
|
1401 |
pHwInit->uEEPROMStage = 1;
|
|
1402 |
}
|
|
1403 |
/* If address LSB = 0 --> We're not in the burst section */
|
|
1404 |
else
|
|
1405 |
{
|
|
1406 |
/* End of Burst transaction: we should see 7 zeroed bytes */
|
|
1407 |
if (pHwInit->pEEPROMCurPtr[0] == 0)
|
|
1408 |
{
|
|
1409 |
pHwInit->pEEPROMCurPtr += 7;
|
|
1410 |
}
|
|
1411 |
pHwInit->uEEPROMCurLen -= (pHwInit->pEEPROMCurPtr - pHwInit->pEEPROMBuf + 1);
|
|
1412 |
pHwInit->uEEPROMCurLen = (pHwInit->uEEPROMCurLen + NVS_DATA_BUNDARY_ALIGNMENT - 1) & 0xfffffffc;
|
|
1413 |
/* End of Burst transaction, go to TLV section */
|
|
1414 |
pHwInit->uEEPROMStage = 2;
|
|
1415 |
}
|
|
1416 |
continue;
|
|
1417 |
|
|
1418 |
case 1:
|
|
1419 |
if (pHwInit->uEEPROMBurstLoop < pHwInit->uEEPROMBurstLen)
|
|
1420 |
{
|
|
1421 |
/* Change the data's endian */
|
|
1422 |
TI_UINT32 val = (pHwInit->pEEPROMCurPtr[0] |
|
|
1423 |
(pHwInit->pEEPROMCurPtr[1] << 8) |
|
|
1424 |
(pHwInit->pEEPROMCurPtr[2] << 16) |
|
|
1425 |
(pHwInit->pEEPROMCurPtr[3] << 24));
|
|
1426 |
|
|
1427 |
TRACE2(pHwInit->hReport, REPORT_SEVERITY_INIT , "NVS::BurstRead: *(%08x) = %x\n", pHwInit->uEEPROMRegAddr, val);
|
|
1428 |
|
|
1429 |
BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, (REGISTERS_BASE+pHwInit->uEEPROMRegAddr), val,
|
|
1430 |
REGISTER_SIZE, TXN_DIRECTION_WRITE, (TTxnDoneCb)hwInit_EepromlessStartBurstSm, hHwInit)
|
|
1431 |
status = twIf_Transact(pHwInit->hTwIf, pTxn);
|
|
1432 |
|
|
1433 |
pHwInit->uEEPROMStatus = status;
|
|
1434 |
pHwInit->uEEPROMRegAddr += WORD_SIZE;
|
|
1435 |
pHwInit->pEEPROMCurPtr += WORD_SIZE;
|
|
1436 |
/* While not end of burst, we stay in stage 1 */
|
|
1437 |
pHwInit->uEEPROMStage = 1;
|
|
1438 |
pHwInit->uEEPROMBurstLoop ++;
|
|
1439 |
|
|
1440 |
EXCEPT (pHwInit, status);
|
|
1441 |
}
|
|
1442 |
else
|
|
1443 |
{
|
|
1444 |
/* If end of burst return to stage 0 to read the next one */
|
|
1445 |
pHwInit->uEEPROMStage = 0;
|
|
1446 |
}
|
|
1447 |
|
|
1448 |
continue;
|
|
1449 |
|
|
1450 |
case 2:
|
|
1451 |
|
|
1452 |
|
|
1453 |
pHwInit->uEEPROMStage = 3;
|
|
1454 |
|
|
1455 |
SET_WORK_PARTITION(pHwInit->aPartition)
|
|
1456 |
/* Set the bus addresses partition to its "running" mode */
|
|
1457 |
hwInit_SetPartition (pHwInit,pHwInit->aPartition);
|
|
1458 |
continue;
|
|
1459 |
|
|
1460 |
case 3:
|
|
1461 |
TRACE0(pHwInit->hReport, REPORT_SEVERITY_INIT , "Reached TLV section\n");
|
|
1462 |
|
|
1463 |
/* Align the host address */
|
|
1464 |
if (((TI_UINT32)pHwInit->pEEPROMCurPtr & WORD_ALIGNMENT_MASK) && (pHwInit->uEEPROMCurLen > 0) )
|
|
1465 |
{
|
|
1466 |
uAddr = (TI_UINT8*)(((TI_UINT32)pHwInit->pEEPROMCurPtr & 0xFFFFFFFC)+WORD_SIZE);
|
|
1467 |
uDeltaLength = uAddr - pHwInit->pEEPROMCurPtr + 1;
|
|
1468 |
|
|
1469 |
pHwInit->pEEPROMCurPtr = uAddr;
|
|
1470 |
pHwInit->uEEPROMCurLen-= uDeltaLength;
|
|
1471 |
}
|
|
1472 |
|
|
1473 |
TRACE2(pHwInit->hReport, REPORT_SEVERITY_INIT , "NVS::WriteTLV: pEEPROMCurPtr= %x, Length=%d\n", pHwInit->pEEPROMCurPtr, pHwInit->uEEPROMCurLen);
|
|
1474 |
|
|
1475 |
if (pHwInit->uEEPROMCurLen)
|
|
1476 |
{
|
|
1477 |
/* Save the 4 bytes before the NVS data for WSPI case where they are overrun by the WSPI BusDrv */
|
|
1478 |
pHwInit->uSavedDataForWspiHdr = *(TI_UINT32 *)(pHwInit->pEEPROMCurPtr - WSPI_PAD_LEN_WRITE);
|
|
1479 |
|
|
1480 |
/* Prepare the Txn structure for the NVS transaction to the CMD_MBOX */
|
|
1481 |
HW_INIT_PTXN_SET(pHwInit, pTxn)
|
|
1482 |
TXN_PARAM_SET_DIRECTION(pTxn, TXN_DIRECTION_WRITE);
|
|
1483 |
BUILD_TTxnStruct(pTxn, CMD_MBOX_ADDRESS, pHwInit->pEEPROMCurPtr, pHwInit->uEEPROMCurLen,
|
|
1484 |
(TTxnDoneCb)hwInit_EepromlessStartBurstSm, hHwInit)
|
|
1485 |
|
|
1486 |
/* Transact the NVS data to the CMD_MBOX */
|
|
1487 |
status = twIf_Transact(pHwInit->hTwIf, pTxn);
|
|
1488 |
|
|
1489 |
pHwInit->uEEPROMCurLen = 0;
|
|
1490 |
pHwInit->uNVSStatus = status;
|
|
1491 |
|
|
1492 |
EXCEPT (pHwInit, status);
|
|
1493 |
}
|
|
1494 |
else
|
|
1495 |
{
|
|
1496 |
/* Restore the 4 bytes before the NVS data for WSPI case were they are overrun by the WSPI BusDrv */
|
|
1497 |
*(TI_UINT32 *)(pHwInit->pEEPROMCurPtr - WSPI_PAD_LEN_WRITE) = pHwInit->uSavedDataForWspiHdr;
|
|
1498 |
|
|
1499 |
/* Call the upper level state machine */
|
|
1500 |
if (pHwInit->uEEPROMStatus == TXN_STATUS_PENDING ||
|
|
1501 |
pHwInit->uNVSStatus == TXN_STATUS_PENDING)
|
|
1502 |
{
|
|
1503 |
hwInit_BootSm (hHwInit);
|
|
1504 |
}
|
|
1505 |
|
|
1506 |
return TXN_STATUS_COMPLETE;
|
|
1507 |
}
|
|
1508 |
} /* End switch */
|
|
1509 |
|
|
1510 |
} /* End while */
|
|
1511 |
}
|
|
1512 |
|
|
1513 |
/****************************************************************************
|
|
1514 |
* hwInit_LoadFwImageSm()
|
|
1515 |
****************************************************************************
|
|
1516 |
* DESCRIPTION: Load image from the host and download into the hardware
|
|
1517 |
*
|
|
1518 |
* INPUTS: None
|
|
1519 |
*
|
|
1520 |
* OUTPUT: None
|
|
1521 |
*
|
|
1522 |
* RETURNS: TI_OK or TI_NOK
|
|
1523 |
****************************************************************************/
|
|
1524 |
|
|
1525 |
|
|
1526 |
#define ADDRESS_SIZE (sizeof(TI_INT32))
|
|
1527 |
|
|
1528 |
static TI_STATUS hwInit_LoadFwImageSm (TI_HANDLE hHwInit)
|
|
1529 |
{
|
|
1530 |
THwInit *pHwInit = (THwInit *)hHwInit;
|
|
1531 |
TI_STATUS status = TI_OK;
|
|
1532 |
ETxnStatus TxnStatus;
|
|
1533 |
TI_UINT32 uMaxPartitionSize = PARTITION_DOWN_MEM_SIZE;
|
|
1534 |
TTxnStruct* pTxn;
|
|
1535 |
|
|
1536 |
pHwInit->uTxnIndex = 0;
|
|
1537 |
|
|
1538 |
while (TI_TRUE)
|
|
1539 |
{
|
|
1540 |
switch (pHwInit->uLoadStage)
|
|
1541 |
{
|
|
1542 |
case 0:
|
|
1543 |
pHwInit->uLoadStage = 1;
|
|
1544 |
|
|
1545 |
/* Check the Downloaded FW alignment */
|
|
1546 |
if ((pHwInit->uFwLength % ADDRESS_SIZE) != 0)
|
|
1547 |
{
|
|
1548 |
TRACE1(pHwInit->hReport, REPORT_SEVERITY_ERROR , "Length of downloaded Portion (%d) is not aligned\n",pHwInit->uFwLength);
|
|
1549 |
EXCEPT_L (pHwInit, TXN_STATUS_ERROR);
|
|
1550 |
}
|
|
1551 |
|
|
1552 |
TRACE2(pHwInit->hReport, REPORT_SEVERITY_INIT , "Image addr=0x%x, Len=0x%x\n", pHwInit->pFwBuf, pHwInit->uFwLength);
|
|
1553 |
|
|
1554 |
SET_FW_LOAD_PARTITION(pHwInit->aPartition,pHwInit->uFwAddress)
|
|
1555 |
/* Set bus memory partition to current download area */
|
|
1556 |
hwInit_SetPartition (pHwInit,pHwInit->aPartition);
|
|
1557 |
status = TI_OK;
|
|
1558 |
break;
|
|
1559 |
|
|
1560 |
case 1:
|
|
1561 |
|
|
1562 |
pHwInit->uLoadStage = 2;
|
|
1563 |
/* if initial size is smaller than MAX_SDIO_BLOCK - go strait to stage 4 to write partial block */
|
|
1564 |
if (pHwInit->uFwLength < MAX_SDIO_BLOCK)
|
|
1565 |
{
|
|
1566 |
pHwInit->uLoadStage = 4;
|
|
1567 |
}
|
|
1568 |
|
|
1569 |
pHwInit->uBlockReadNum = 0;
|
|
1570 |
pHwInit->uBlockWriteNum = 0;
|
|
1571 |
pHwInit->uPartitionLimit = pHwInit->uFwAddress + uMaxPartitionSize;
|
|
1572 |
|
|
1573 |
break;
|
|
1574 |
|
|
1575 |
case 2:
|
|
1576 |
|
|
1577 |
/* Load firmware by blocks */
|
|
1578 |
if (pHwInit->uBlockReadNum < (pHwInit->uFwLength / MAX_SDIO_BLOCK))
|
|
1579 |
{
|
|
1580 |
pHwInit->uLoadStage = 3;
|
|
1581 |
|
|
1582 |
/* Change partition */
|
|
1583 |
/* The +2 is for the last block and the block remainder */
|
|
1584 |
if ( ((pHwInit->uBlockWriteNum + 2) * MAX_SDIO_BLOCK + pHwInit->uFwAddress) > pHwInit->uPartitionLimit)
|
|
1585 |
{
|
|
1586 |
pHwInit->uFwAddress += pHwInit->uBlockWriteNum * MAX_SDIO_BLOCK;
|
|
1587 |
/* update uPartitionLimit */
|
|
1588 |
pHwInit->uPartitionLimit = pHwInit->uFwAddress + uMaxPartitionSize;
|
|
1589 |
SET_FW_LOAD_PARTITION(pHwInit->aPartition,pHwInit->uFwAddress)
|
|
1590 |
/* Set bus memory partition to current download area */
|
|
1591 |
hwInit_SetPartition (pHwInit,pHwInit->aPartition);
|
|
1592 |
TxnStatus = TXN_STATUS_OK;
|
|
1593 |
pHwInit->uBlockWriteNum = 0;
|
|
1594 |
TRACE1(pHwInit->hReport, REPORT_SEVERITY_INIT , "Change partition to address offset = 0x%x\n", pHwInit->uFwAddress + pHwInit->uBlockWriteNum * MAX_SDIO_BLOCK);
|
|
1595 |
EXCEPT_L (pHwInit, TxnStatus);
|
|
1596 |
}
|
|
1597 |
}
|
|
1598 |
else
|
|
1599 |
{
|
|
1600 |
pHwInit->uLoadStage = 4;
|
|
1601 |
TRACE0(pHwInit->hReport, REPORT_SEVERITY_INIT , "Load firmware with Portions\n");
|
|
1602 |
}
|
|
1603 |
break;
|
|
1604 |
|
|
1605 |
case 3:
|
|
1606 |
pHwInit->uLoadStage = 2;
|
|
1607 |
|
|
1608 |
pHwInit->uTxnIndex = 0;
|
|
1609 |
|
|
1610 |
/* Copy image block to temporary buffer */
|
|
1611 |
|
|
1612 |
os_memoryCopy (pHwInit->hOs,
|
|
1613 |
(void *)pHwInit->puFwTmpBuf,
|
|
1614 |
(void *)(pHwInit->pFwBuf + pHwInit->uBlockReadNum * MAX_SDIO_BLOCK),
|
|
1615 |
MAX_SDIO_BLOCK);
|
|
1616 |
|
|
1617 |
/* Load the block. Save WSPI_PAD_LEN_WRITE space for WSPI bus command */
|
|
1618 |
BUILD_HW_INIT_FW_DL_TXN(pHwInit, pTxn, (pHwInit->uFwAddress + pHwInit->uBlockWriteNum * MAX_SDIO_BLOCK),
|
|
1619 |
pHwInit->puFwTmpBuf, MAX_SDIO_BLOCK, TXN_DIRECTION_WRITE,
|
|
1620 |
(TTxnDoneCb)hwInit_LoadFwImageSm, hHwInit)
|
|
1621 |
TxnStatus = twIf_Transact(pHwInit->hTwIf, pTxn);
|
|
1622 |
|
|
1623 |
/* Log ERROR if the transaction returned ERROR */
|
|
1624 |
if (TxnStatus == TXN_STATUS_ERROR)
|
|
1625 |
{
|
|
1626 |
TRACE1(pHwInit->hReport, REPORT_SEVERITY_ERROR , "hwInit_LoadFwImageSm: twIf_Transact retruned status=0x%x\n", TxnStatus);
|
|
1627 |
}
|
|
1628 |
|
|
1629 |
pHwInit->uBlockWriteNum ++;
|
|
1630 |
pHwInit->uBlockReadNum ++;
|
|
1631 |
EXCEPT_L (pHwInit, TxnStatus);
|
|
1632 |
break;
|
|
1633 |
|
|
1634 |
case 4:
|
|
1635 |
pHwInit->uLoadStage = 5;
|
|
1636 |
|
|
1637 |
pHwInit->uTxnIndex = 0;
|
|
1638 |
|
|
1639 |
/* If No Last block to write */
|
|
1640 |
if ( pHwInit->uFwLength % MAX_SDIO_BLOCK == 0 )
|
|
1641 |
{
|
|
1642 |
break;
|
|
1643 |
}
|
|
1644 |
|
|
1645 |
|
|
1646 |
/* Copy the last image block */
|
|
1647 |
|
|
1648 |
os_memoryCopy (pHwInit->hOs,
|
|
1649 |
(void *)pHwInit->puFwTmpBuf,
|
|
1650 |
(void *)(pHwInit->pFwBuf + pHwInit->uBlockReadNum * MAX_SDIO_BLOCK),
|
|
1651 |
pHwInit->uFwLength % MAX_SDIO_BLOCK);
|
|
1652 |
|
|
1653 |
/* Load the last block */
|
|
1654 |
BUILD_HW_INIT_FW_DL_TXN(pHwInit, pTxn, (pHwInit->uFwAddress + pHwInit->uBlockWriteNum * MAX_SDIO_BLOCK),
|
|
1655 |
pHwInit->puFwTmpBuf, (pHwInit->uFwLength % MAX_SDIO_BLOCK), TXN_DIRECTION_WRITE,
|
|
1656 |
(TTxnDoneCb)hwInit_LoadFwImageSm, hHwInit)
|
|
1657 |
TxnStatus = twIf_Transact(pHwInit->hTwIf, pTxn);
|
|
1658 |
|
|
1659 |
if (TxnStatus == TXN_STATUS_ERROR)
|
|
1660 |
{
|
|
1661 |
TRACE1(pHwInit->hReport, REPORT_SEVERITY_ERROR , "hwInit_LoadFwImageSm: last block retruned status=0x%x\n", TxnStatus);
|
|
1662 |
}
|
|
1663 |
|
|
1664 |
EXCEPT_L (pHwInit, TxnStatus);
|
|
1665 |
break;
|
|
1666 |
|
|
1667 |
case 5:
|
|
1668 |
pHwInit->uLoadStage = 0;
|
|
1669 |
|
|
1670 |
/*If end of overall FW Download Process: Finalize download (run firmware)*/
|
|
1671 |
if ( pHwInit->bFwBufLast == TI_TRUE )
|
|
1672 |
{
|
|
1673 |
/* The download has completed */
|
|
1674 |
WLAN_OS_REPORT (("Finished downloading firmware.\n"));
|
|
1675 |
status = hwInit_FinalizeDownloadSm (hHwInit);
|
|
1676 |
}
|
|
1677 |
/* Have to wait to more FW Portions */
|
|
1678 |
else
|
|
1679 |
{
|
|
1680 |
/* Call the upper layer callback */
|
|
1681 |
if ( pHwInit->fFinalizeDownload != NULL )
|
|
1682 |
{
|
|
1683 |
(pHwInit->fFinalizeDownload) (pHwInit->hFinalizeDownload);
|
|
1684 |
}
|
|
1685 |
|
|
1686 |
status = TI_OK;
|
|
1687 |
}
|
|
1688 |
return status;
|
|
1689 |
|
|
1690 |
} /* End switch */
|
|
1691 |
|
|
1692 |
} /* End while */
|
|
1693 |
|
|
1694 |
} /* hwInit_LoadFwImageSm() */
|
|
1695 |
|
|
1696 |
#define READ_TOP_REG_LOOP 32
|
|
1697 |
|
|
1698 |
/****************************************************************************
|
|
1699 |
* hwInit_ReadRadioParamsSm ()
|
|
1700 |
****************************************************************************
|
|
1701 |
* DESCRIPTION: hwInit_ReadRadioParamsSm
|
|
1702 |
* INPUTS: None
|
|
1703 |
*
|
|
1704 |
* OUTPUT: None
|
|
1705 |
*
|
|
1706 |
* RETURNS: TI_OK or TI_NOK
|
|
1707 |
****************************************************************************/
|
|
1708 |
TI_STATUS hwInit_ReadRadioParamsSm (TI_HANDLE hHwInit)
|
|
1709 |
{
|
|
1710 |
THwInit *pHwInit = (THwInit *)hHwInit;
|
|
1711 |
TTwd *pTWD = (TTwd *)pHwInit->hTWD;
|
|
1712 |
IniFileGeneralParam *pGenParams = &DB_GEN(pTWD->hCmdBld);
|
|
1713 |
TI_UINT32 val= 0, value;
|
|
1714 |
TI_UINT32 add = FUNC7_SEL;
|
|
1715 |
TI_UINT32 retAddress;
|
|
1716 |
TTxnStruct *pTxn;
|
|
1717 |
TI_STATUS status = 0;
|
|
1718 |
|
|
1719 |
while (TI_TRUE)
|
|
1720 |
{
|
|
1721 |
switch (pHwInit->uRegStage)
|
|
1722 |
{
|
|
1723 |
case 0:
|
|
1724 |
pHwInit->uRegStage = 1;
|
|
1725 |
pHwInit->uTxnIndex++;
|
|
1726 |
|
|
1727 |
/*
|
|
1728 |
* Select GPIO over Debug for BT_FUNC7 clear bit 17
|
|
1729 |
*/
|
|
1730 |
BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, GPIO_SELECT, 0,
|
|
1731 |
REGISTER_SIZE, TXN_DIRECTION_READ, (TTxnDoneCb)hwInit_ReadRadioParamsSm, hHwInit)
|
|
1732 |
status = twIf_Transact(pHwInit->hTwIf, pTxn);
|
|
1733 |
|
|
1734 |
EXCEPT (pHwInit, status)
|
|
1735 |
|
|
1736 |
case 1:
|
|
1737 |
pHwInit->uRegStage ++;
|
|
1738 |
pHwInit->uRegLoop = 0;
|
|
1739 |
|
|
1740 |
/* We don't zero pHwInit->uTxnIndex at the begining because we need it's value to the next transaction */
|
|
1741 |
val = *((TI_UINT32*)(pHwInit->aHwInitTxn[pHwInit->uTxnIndex].pData));
|
|
1742 |
val &= 0xFFFDFFFF; /*clear bit 17*/
|
|
1743 |
/* Now we can zero the index */
|
|
1744 |
pHwInit->uTxnIndex = 0;
|
|
1745 |
|
|
1746 |
BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, GPIO_SELECT, val,
|
|
1747 |
REGISTER_SIZE, TXN_DIRECTION_WRITE, NULL, NULL)
|
|
1748 |
|
|
1749 |
twIf_Transact(pHwInit->hTwIf, pTxn);
|
|
1750 |
|
|
1751 |
pHwInit->uTxnIndex++;
|
|
1752 |
|
|
1753 |
pHwInit->uRegData = FUNC7_SEL;
|
|
1754 |
|
|
1755 |
continue;
|
|
1756 |
|
|
1757 |
case 2:
|
|
1758 |
pHwInit->uRegStage ++;
|
|
1759 |
add = pHwInit->uRegData;
|
|
1760 |
|
|
1761 |
/* Select GPIO over Debug for BT_FUNC7*/
|
|
1762 |
retAddress = (TI_UINT32)(add / 2);
|
|
1763 |
val = (retAddress & 0x7FF);
|
|
1764 |
val |= BIT_16 | BIT_17;
|
|
1765 |
|
|
1766 |
BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, OCP_POR_CTR, val,
|
|
1767 |
REGISTER_SIZE, TXN_DIRECTION_WRITE, NULL, NULL)
|
|
1768 |
twIf_Transact(pHwInit->hTwIf, pTxn);
|
|
1769 |
|
|
1770 |
pHwInit->uTxnIndex++;
|
|
1771 |
|
|
1772 |
BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, OCP_CMD, 0x2,
|
|
1773 |
REGISTER_SIZE, TXN_DIRECTION_WRITE, NULL, NULL)
|
|
1774 |
twIf_Transact(pHwInit->hTwIf, pTxn);
|
|
1775 |
|
|
1776 |
continue;
|
|
1777 |
|
|
1778 |
case 3:
|
|
1779 |
pHwInit->uRegStage ++;
|
|
1780 |
pHwInit->uTxnIndex++;
|
|
1781 |
|
|
1782 |
BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, OCP_DATA_RD, 0,
|
|
1783 |
REGISTER_SIZE, TXN_DIRECTION_READ, (TTxnDoneCb)hwInit_ReadRadioParamsSm, hHwInit)
|
|
1784 |
status = twIf_Transact(pHwInit->hTwIf, pTxn);
|
|
1785 |
|
|
1786 |
EXCEPT (pHwInit, status)
|
|
1787 |
|
|
1788 |
|
|
1789 |
case 4:
|
|
1790 |
val = *((TI_UINT32*)(pHwInit->aHwInitTxn[pHwInit->uTxnIndex].pData));
|
|
1791 |
pHwInit->uTxnIndex = 0;
|
|
1792 |
if (val & BIT_18)
|
|
1793 |
{
|
|
1794 |
if ((val & BIT_16) && (!(val & BIT_17)))
|
|
1795 |
{
|
|
1796 |
pHwInit->uRegStage ++;
|
|
1797 |
pHwInit->uRegLoop = 0;
|
|
1798 |
|
|
1799 |
}
|
|
1800 |
else
|
|
1801 |
{
|
|
1802 |
TRACE0(pHwInit->hReport, REPORT_SEVERITY_ERROR , "hwInit_ReadRadioParamsSm: can't writing bt_func7_sel\n");
|
|
1803 |
TWD_FinalizeFEMRead(pHwInit->hTWD);
|
|
1804 |
|
|
1805 |
return TI_NOK;
|
|
1806 |
}
|
|
1807 |
}
|
|
1808 |
else
|
|
1809 |
{
|
|
1810 |
if (pHwInit->uRegLoop < READ_TOP_REG_LOOP)
|
|
1811 |
{
|
|
1812 |
pHwInit->uRegStage = 3;
|
|
1813 |
pHwInit->uRegLoop++;
|
|
1814 |
}
|
|
1815 |
else
|
|
1816 |
{
|
|
1817 |
|
|
1818 |
TRACE0(pHwInit->hReport, REPORT_SEVERITY_ERROR , "Timeout waiting for writing bt_func7_sel\n");
|
|
1819 |
TWD_FinalizeFEMRead(pHwInit->hTWD);
|
|
1820 |
|
|
1821 |
return TI_NOK;
|
|
1822 |
|
|
1823 |
}
|
|
1824 |
}
|
|
1825 |
|
|
1826 |
continue;
|
|
1827 |
|
|
1828 |
case 5:
|
|
1829 |
|
|
1830 |
pHwInit->uRegStage ++;
|
|
1831 |
add = pHwInit->uRegData;
|
|
1832 |
retAddress = (TI_UINT32)(add / 2);
|
|
1833 |
value = (retAddress & 0x7FF);
|
|
1834 |
value |= BIT_16 | BIT_17;
|
|
1835 |
|
|
1836 |
BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, OCP_POR_CTR, value,
|
|
1837 |
REGISTER_SIZE, TXN_DIRECTION_WRITE, NULL, NULL)
|
|
1838 |
twIf_Transact(pHwInit->hTwIf, pTxn);
|
|
1839 |
|
|
1840 |
pHwInit->uTxnIndex++;
|
|
1841 |
|
|
1842 |
if (pHwInit->uRegSeqStage == 0)
|
|
1843 |
{
|
|
1844 |
if (pHwInit->uRegData == FUNC7_SEL)
|
|
1845 |
value = (val | 0x600);
|
|
1846 |
else
|
|
1847 |
value = (val | 0x1000);
|
|
1848 |
}
|
|
1849 |
else
|
|
1850 |
{
|
|
1851 |
if (pHwInit->uRegData == FUNC7_SEL)
|
|
1852 |
value = (val & 0xF8FF);
|
|
1853 |
else
|
|
1854 |
value = (val & 0xCFFF);
|
|
1855 |
|
|
1856 |
}
|
|
1857 |
|
|
1858 |
value &= 0xFFFF;
|
|
1859 |
|
|
1860 |
BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, OCP_POR_WDATA, value,
|
|
1861 |
REGISTER_SIZE, TXN_DIRECTION_WRITE, NULL, NULL)
|
|
1862 |
twIf_Transact(pHwInit->hTwIf, pTxn);
|
|
1863 |
|
|
1864 |
pHwInit->uTxnIndex++;
|
|
1865 |
|
|
1866 |
BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, OCP_CMD, 0x1,
|
|
1867 |
REGISTER_SIZE, TXN_DIRECTION_WRITE, (TTxnDoneCb)hwInit_ReadRadioParamsSm, hHwInit)
|
|
1868 |
status = twIf_Transact(pHwInit->hTwIf, pTxn);
|
|
1869 |
|
|
1870 |
pHwInit->uTxnIndex++;
|
|
1871 |
|
|
1872 |
if ((pHwInit->uRegData == FUNC7_SEL)&& (pHwInit->uRegSeqStage == 0))
|
|
1873 |
{
|
|
1874 |
pHwInit->uRegData = FUNC7_PULL;
|
|
1875 |
pHwInit->uRegStage = 2;
|
|
1876 |
}
|
|
1877 |
else
|
|
1878 |
{
|
|
1879 |
if ((pHwInit->uRegData == FUNC7_PULL)&& (pHwInit->uRegSeqStage == 1))
|
|
1880 |
{
|
|
1881 |
pHwInit->uRegData = FUNC7_SEL;
|
|
1882 |
pHwInit->uRegStage = 2;
|
|
1883 |
}
|
|
1884 |
}
|
|
1885 |
|
|
1886 |
EXCEPT (pHwInit, status)
|
|
1887 |
continue;
|
|
1888 |
|
|
1889 |
case 6:
|
|
1890 |
|
|
1891 |
if (pHwInit->uRegSeqStage == 1)
|
|
1892 |
{
|
|
1893 |
pHwInit->uRegStage = 8;
|
|
1894 |
}
|
|
1895 |
else
|
|
1896 |
{
|
|
1897 |
pHwInit->uRegStage ++;
|
|
1898 |
pHwInit->uTxnIndex++;
|
|
1899 |
|
|
1900 |
BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, GPIO_OE_RADIO, 0,
|
|
1901 |
REGISTER_SIZE, TXN_DIRECTION_READ, (TTxnDoneCb)hwInit_ReadRadioParamsSm, hHwInit)
|
|
1902 |
status = twIf_Transact(pHwInit->hTwIf, pTxn);
|
|
1903 |
|
|
1904 |
EXCEPT (pHwInit, status)
|
|
1905 |
}
|
|
1906 |
continue;
|
|
1907 |
|
|
1908 |
case 7:
|
|
1909 |
|
|
1910 |
pHwInit->uRegStage ++;
|
|
1911 |
|
|
1912 |
/* We don't zero pHwInit->uTxnIndex at the begining because we need it's value to the next transaction */
|
|
1913 |
val = *((TI_UINT32*)(pHwInit->aHwInitTxn[pHwInit->uTxnIndex].pData));
|
|
1914 |
val |= 0x00020000;
|
|
1915 |
|
|
1916 |
pHwInit->uTxnIndex = 0;
|
|
1917 |
BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, GPIO_OE_RADIO, val,
|
|
1918 |
REGISTER_SIZE, TXN_DIRECTION_WRITE, NULL, NULL)
|
|
1919 |
twIf_Transact(pHwInit->hTwIf, pTxn);
|
|
1920 |
|
|
1921 |
pHwInit->uTxnIndex++;
|
|
1922 |
|
|
1923 |
BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, GPIO_IN, 0,
|
|
1924 |
REGISTER_SIZE, TXN_DIRECTION_READ, (TTxnDoneCb)hwInit_ReadRadioParamsSm, hHwInit)
|
|
1925 |
status = twIf_Transact(pHwInit->hTwIf, pTxn);
|
|
1926 |
|
|
1927 |
EXCEPT (pHwInit, status)
|
|
1928 |
|
|
1929 |
|
|
1930 |
case 8:
|
|
1931 |
|
|
1932 |
if (pHwInit->uRegSeqStage == 0)
|
|
1933 |
{
|
|
1934 |
val = *((TI_UINT32*)(pHwInit->aHwInitTxn[pHwInit->uTxnIndex].pData));
|
|
1935 |
val &= 0x20000;
|
|
1936 |
if(val)
|
|
1937 |
{
|
|
1938 |
pGenParams->TXBiPFEMManufacturer = FEM_TRIQUINT_TYPE_E;
|
|
1939 |
}
|
|
1940 |
else
|
|
1941 |
{
|
|
1942 |
pGenParams->TXBiPFEMManufacturer = FEM_RFMD_TYPE_E;
|
|
1943 |
}
|
|
1944 |
WLAN_OS_REPORT (("hwInit_ReadRadioParamsSm FEM Type %d \n",pGenParams->TXBiPFEMManufacturer));
|
|
1945 |
pHwInit->uTxnIndex = 0;
|
|
1946 |
pHwInit->uRegSeqStage = 1;
|
|
1947 |
pHwInit->uRegStage = 2;
|
|
1948 |
pHwInit->uRegData = FUNC7_PULL;
|
|
1949 |
continue;
|
|
1950 |
}
|
|
1951 |
else
|
|
1952 |
{
|
|
1953 |
|
|
1954 |
WLAN_OS_REPORT (("hwInit_ReadRadioParamsSm Ended Successfully\n"));
|
|
1955 |
|
|
1956 |
TWD_FinalizeFEMRead(pHwInit->hTWD);
|
|
1957 |
|
|
1958 |
return TI_OK;
|
|
1959 |
|
|
1960 |
}
|
|
1961 |
|
|
1962 |
} /* End switch */
|
|
1963 |
|
|
1964 |
} /* End while */
|
|
1965 |
|
|
1966 |
}
|
|
1967 |
|
|
1968 |
|
|
1969 |
/****************************************************************************
|
|
1970 |
* hwInit_ReadRadioParams()
|
|
1971 |
****************************************************************************
|
|
1972 |
* DESCRIPTION: hwInit_ReadRadioParamsSm
|
|
1973 |
* initalizie hwInit_ReadRadioParamsSm parmaeters
|
|
1974 |
****************************************************************************/
|
|
1975 |
|
|
1976 |
TI_STATUS hwInit_ReadRadioParams (TI_HANDLE hHwInit)
|
|
1977 |
{
|
|
1978 |
THwInit *pHwInit = (THwInit *)hHwInit;
|
|
1979 |
|
|
1980 |
pHwInit->uRegStage = 0;
|
|
1981 |
pHwInit->uRegSeqStage = 0;
|
|
1982 |
|
|
1983 |
return hwInit_ReadRadioParamsSm (hHwInit);
|
|
1984 |
}
|
|
1985 |
|
|
1986 |
/****************************************************************************
|
|
1987 |
* hwInit_InitPoalrity()
|
|
1988 |
****************************************************************************
|
|
1989 |
* DESCRIPTION: hwInit_ReadRadioParamsSm
|
|
1990 |
* initalizie hwInit_ReadRadioParamsSm parmaeters
|
|
1991 |
****************************************************************************/
|
|
1992 |
|
|
1993 |
TI_STATUS hwInit_InitPolarity(TI_HANDLE hHwInit)
|
|
1994 |
{
|
|
1995 |
THwInit *pHwInit = (THwInit *)hHwInit;
|
|
1996 |
|
|
1997 |
pHwInit->uRegStage = 0;
|
|
1998 |
pHwInit->uRegSeqStage = 0;
|
|
1999 |
|
|
2000 |
return hwInit_WriteIRQPolarity (hHwInit);
|
|
2001 |
}
|
|
2002 |
|
|
2003 |
|
|
2004 |
|
|
2005 |
/****************************************************************************
|
|
2006 |
* hwInit_WriteIRQPolarity ()
|
|
2007 |
****************************************************************************
|
|
2008 |
* DESCRIPTION: hwInit_WriteIRQPolarity
|
|
2009 |
* INPUTS: None
|
|
2010 |
*
|
|
2011 |
* OUTPUT: None
|
|
2012 |
*
|
|
2013 |
* RETURNS: TI_OK or TI_NOK
|
|
2014 |
****************************************************************************/
|
|
2015 |
TI_STATUS hwInit_WriteIRQPolarity(TI_HANDLE hHwInit)
|
|
2016 |
{
|
|
2017 |
THwInit *pHwInit = (THwInit *)hHwInit;
|
|
2018 |
TI_UINT32 Address = 0,val = 0,value = 0;
|
|
2019 |
TTxnStruct *pTxn;
|
|
2020 |
TI_STATUS status = 0;
|
|
2021 |
|
|
2022 |
/* To write to a top level address from the WLAN IP:
|
|
2023 |
Write the top level address to the OCP_POR_CTR register.
|
|
2024 |
Divide the top address by 2, and add 0x30000 to the result – for example for top address 0xC00, write to the OCP_POR_CTR 0x30600
|
|
2025 |
Write the data to the OCP_POR_WDATA register
|
|
2026 |
Write 0x1 to the OCP_CMD register.
|
|
2027 |
|
|
2028 |
To read from a top level address:
|
|
2029 |
Write the top level address to the OCP_POR_CTR register.
|
|
2030 |
Divide the top address by 2, and add 0x30000 to the result – for example for top address 0xC00, write to the OCP_POR_CTR 0x30600
|
|
2031 |
Write 0x2 to the OCP_CMD register.
|
|
2032 |
Poll bit [18] of OCP_DATA_RD for data valid indication
|
|
2033 |
Check bits 17:16 of OCP_DATA_RD:
|
|
2034 |
00 – no response
|
|
2035 |
01 – data valid / accept
|
|
2036 |
10 – request failed
|
|
2037 |
11 – response error
|
|
2038 |
Read the data from the OCP_DATA_RD register
|
|
2039 |
*/
|
|
2040 |
|
|
2041 |
while (TI_TRUE)
|
|
2042 |
{
|
|
2043 |
switch (pHwInit->uRegStage)
|
|
2044 |
{
|
|
2045 |
case 0:
|
|
2046 |
pHwInit->uRegStage = 1;
|
|
2047 |
pHwInit->uTxnIndex++;
|
|
2048 |
pHwInit->uRegLoop = 0;
|
|
2049 |
|
|
2050 |
/* first read the IRQ Polarity register*/
|
|
2051 |
Address = (TI_UINT32)(FN0_CCCR_REG_32 / 2);
|
|
2052 |
val = (Address & 0x7FF);
|
|
2053 |
val |= BIT_16 | BIT_17;
|
|
2054 |
|
|
2055 |
/* Write IRQ Polarity address register to OCP_POR_CTR*/
|
|
2056 |
BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, OCP_POR_CTR, val,
|
|
2057 |
REGISTER_SIZE, TXN_DIRECTION_WRITE, NULL, NULL)
|
|
2058 |
|
|
2059 |
twIf_Transact(pHwInit->hTwIf, pTxn);
|
|
2060 |
|
|
2061 |
pHwInit->uTxnIndex++;
|
|
2062 |
|
|
2063 |
/* Write read (2)command to the OCP_CMD register. */
|
|
2064 |
|
|
2065 |
BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, OCP_CMD, 0x2,
|
|
2066 |
REGISTER_SIZE, TXN_DIRECTION_WRITE, NULL, NULL)
|
|
2067 |
twIf_Transact(pHwInit->hTwIf, pTxn);
|
|
2068 |
|
|
2069 |
continue;
|
|
2070 |
|
|
2071 |
case 1:
|
|
2072 |
pHwInit->uRegStage ++;
|
|
2073 |
pHwInit->uTxnIndex++;
|
|
2074 |
|
|
2075 |
BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, OCP_DATA_RD, 0,
|
|
2076 |
REGISTER_SIZE, TXN_DIRECTION_READ, (TTxnDoneCb)hwInit_WriteIRQPolarity, hHwInit)
|
|
2077 |
status = twIf_Transact(pHwInit->hTwIf, pTxn);
|
|
2078 |
|
|
2079 |
EXCEPT (pHwInit, status)
|
|
2080 |
|
|
2081 |
|
|
2082 |
case 2:
|
|
2083 |
/* get the value from IRQ Polarity register*/
|
|
2084 |
val = *((TI_UINT32*)(pHwInit->aHwInitTxn[pHwInit->uTxnIndex].pData));
|
|
2085 |
|
|
2086 |
pHwInit->uTxnIndex = 0;
|
|
2087 |
|
|
2088 |
/*Poll bit 18 of OCP_DATA_RD for data valid indication*/
|
|
2089 |
if (val & BIT_18)
|
|
2090 |
{
|
|
2091 |
if ((val & BIT_16) && (!(val & BIT_17)))
|
|
2092 |
{
|
|
2093 |
pHwInit->uRegStage ++;
|
|
2094 |
pHwInit->uRegLoop = 0;
|
|
2095 |
|
|
2096 |
}
|
|
2097 |
else
|
|
2098 |
{
|
|
2099 |
TRACE0(pHwInit->hReport, REPORT_SEVERITY_ERROR , "can't writing bt_func7_sel\n");
|
|
2100 |
TWD_FinalizePolarityRead(pHwInit->hTWD);
|
|
2101 |
|
|
2102 |
return TI_NOK;
|
|
2103 |
}
|
|
2104 |
}
|
|
2105 |
else
|
|
2106 |
{
|
|
2107 |
if (pHwInit->uRegLoop < READ_TOP_REG_LOOP)
|
|
2108 |
{
|
|
2109 |
pHwInit->uRegStage = 1;
|
|
2110 |
pHwInit->uRegLoop++;
|
|
2111 |
}
|
|
2112 |
else
|
|
2113 |
{
|
|
2114 |
|
|
2115 |
TRACE0(pHwInit->hReport, REPORT_SEVERITY_ERROR , "Timeout waiting for writing bt_func7_sel\n");
|
|
2116 |
TWD_FinalizePolarityRead(pHwInit->hTWD);
|
|
2117 |
|
|
2118 |
return TI_NOK;
|
|
2119 |
|
|
2120 |
}
|
|
2121 |
}
|
|
2122 |
|
|
2123 |
continue;
|
|
2124 |
|
|
2125 |
|
|
2126 |
case 3:
|
|
2127 |
/* second, write new value of IRQ polarity due to complation flag 1 - active low, 0 - active high*/
|
|
2128 |
pHwInit->uRegStage ++;
|
|
2129 |
Address = (TI_UINT32)(FN0_CCCR_REG_32 / 2);
|
|
2130 |
value = (Address & 0x7FF);
|
|
2131 |
value |= BIT_16 | BIT_17;
|
|
2132 |
|
|
2133 |
/* Write IRQ Polarity address register to OCP_POR_CTR*/
|
|
2134 |
|
|
2135 |
BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, OCP_POR_CTR, value,
|
|
2136 |
REGISTER_SIZE, TXN_DIRECTION_WRITE, NULL, NULL)
|
|
2137 |
|
|
2138 |
twIf_Transact(pHwInit->hTwIf, pTxn);
|
|
2139 |
|
|
2140 |
pHwInit->uTxnIndex++;
|
|
2141 |
|
|
2142 |
#ifdef USE_IRQ_ACTIVE_HIGH
|
|
2143 |
val |= 0x0<<1;
|
|
2144 |
|
|
2145 |
#else
|
|
2146 |
val |= 0x01<<1;
|
|
2147 |
#endif
|
|
2148 |
|
|
2149 |
/* Write the new IRQ polarity value to the OCP_POR_WDATA register */
|
|
2150 |
BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, OCP_POR_WDATA, val,
|
|
2151 |
REGISTER_SIZE, TXN_DIRECTION_WRITE, NULL, NULL)
|
|
2152 |
twIf_Transact(pHwInit->hTwIf, pTxn);
|
|
2153 |
|
|
2154 |
pHwInit->uTxnIndex++;
|
|
2155 |
|
|
2156 |
/* Write write (1)command to the OCP_CMD register. */
|
|
2157 |
BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, OCP_CMD, 0x1,
|
|
2158 |
REGISTER_SIZE, TXN_DIRECTION_WRITE, (TTxnDoneCb)hwInit_WriteIRQPolarity, hHwInit)
|
|
2159 |
status = twIf_Transact(pHwInit->hTwIf, pTxn);
|
|
2160 |
|
|
2161 |
pHwInit->uTxnIndex++;
|
|
2162 |
|
|
2163 |
EXCEPT (pHwInit, status)
|
|
2164 |
continue;
|
|
2165 |
|
|
2166 |
case 4:
|
|
2167 |
|
|
2168 |
TWD_FinalizePolarityRead(pHwInit->hTWD);
|
|
2169 |
|
|
2170 |
return TI_OK;
|
|
2171 |
|
|
2172 |
|
|
2173 |
|
|
2174 |
} /* End switch */
|
|
2175 |
|
|
2176 |
} /* End while */
|
|
2177 |
|
|
2178 |
}
|
|
2179 |
|
|
2180 |
|
|
2181 |
/****************************************************************************
|
|
2182 |
* hwInit_InitTopRegisterWrite()
|
|
2183 |
****************************************************************************
|
|
2184 |
* DESCRIPTION: hwInit_InitTopRegisterWrite
|
|
2185 |
* initalizie hwInit_TopRegisterWrite SM parmaeters
|
|
2186 |
****************************************************************************/
|
|
2187 |
|
|
2188 |
TI_STATUS hwInit_InitTopRegisterWrite(TI_HANDLE hHwInit, TI_UINT32 uAddress, TI_UINT32 uValue)
|
|
2189 |
{
|
|
2190 |
THwInit *pHwInit = (THwInit *)hHwInit;
|
|
2191 |
|
|
2192 |
pHwInit->uTopStage = 0;
|
|
2193 |
uAddress = (TI_UINT32)(uAddress / 2);
|
|
2194 |
uAddress = (uAddress & 0x7FF);
|
|
2195 |
uAddress|= BIT_16 | BIT_17;
|
|
2196 |
pHwInit->uTopRegAddr = uAddress;
|
|
2197 |
pHwInit->uTopRegValue = uValue & 0xffff;
|
|
2198 |
|
|
2199 |
return hwInit_TopRegisterWrite (hHwInit);
|
|
2200 |
}
|
|
2201 |
|
|
2202 |
|
|
2203 |
/****************************************************************************
|
|
2204 |
* hwInit_WriteTopRegister ()
|
|
2205 |
****************************************************************************
|
|
2206 |
* DESCRIPTION: Generic function that writes to the top registers area
|
|
2207 |
* INPUTS: None
|
|
2208 |
*
|
|
2209 |
* OUTPUT: None
|
|
2210 |
*
|
|
2211 |
* RETURNS: TI_OK or TI_NOK
|
|
2212 |
****************************************************************************/
|
|
2213 |
TI_STATUS hwInit_TopRegisterWrite(TI_HANDLE hHwInit)
|
|
2214 |
{
|
|
2215 |
/* To write to a top level address from the WLAN IP:
|
|
2216 |
Write the top level address to the OCP_POR_CTR register.
|
|
2217 |
Divide the top address by 2, and add 0x30000 to the result – for example for top address 0xC00, write to the OCP_POR_CTR 0x30600
|
|
2218 |
Write the data to the OCP_POR_WDATA register
|
|
2219 |
Write 0x1 to the OCP_CMD register.
|
|
2220 |
*/
|
|
2221 |
THwInit *pHwInit = (THwInit *)hHwInit;
|
|
2222 |
TTxnStruct *pTxn;
|
|
2223 |
|
|
2224 |
while (TI_TRUE)
|
|
2225 |
{
|
|
2226 |
switch (pHwInit->uTopStage)
|
|
2227 |
{
|
|
2228 |
case 0:
|
|
2229 |
pHwInit->uTopStage = 1;
|
|
2230 |
|
|
2231 |
pHwInit->uTxnIndex++;
|
|
2232 |
/* Write the address to OCP_POR_CTR*/
|
|
2233 |
BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, OCP_POR_CTR, pHwInit->uTopRegAddr,
|
|
2234 |
REGISTER_SIZE, TXN_DIRECTION_WRITE, NULL, NULL)
|
|
2235 |
twIf_Transact(pHwInit->hTwIf, pTxn);
|
|
2236 |
|
|
2237 |
pHwInit->uTxnIndex++;
|
|
2238 |
/* Write the new value to the OCP_POR_WDATA register */
|
|
2239 |
BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, OCP_POR_WDATA, pHwInit->uTopRegValue,
|
|
2240 |
REGISTER_SIZE, TXN_DIRECTION_WRITE, NULL, NULL)
|
|
2241 |
twIf_Transact(pHwInit->hTwIf, pTxn);
|
|
2242 |
|
|
2243 |
pHwInit->uTxnIndex++;
|
|
2244 |
/* Write write (1)command to the OCP_CMD register. */
|
|
2245 |
BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, OCP_CMD, 0x1,
|
|
2246 |
REGISTER_SIZE, TXN_DIRECTION_WRITE, (TTxnDoneCb)hwInit_TopRegisterWrite, hHwInit)
|
|
2247 |
pHwInit->uTopStatus = twIf_Transact(pHwInit->hTwIf, pTxn);
|
|
2248 |
|
|
2249 |
pHwInit->uTxnIndex++;
|
|
2250 |
|
|
2251 |
EXCEPT (pHwInit, pHwInit->uTopStatus)
|
|
2252 |
continue;
|
|
2253 |
|
|
2254 |
case 1:
|
|
2255 |
|
|
2256 |
pHwInit->uTxnIndex = 0;
|
|
2257 |
|
|
2258 |
if (pHwInit->uTopStatus == TXN_STATUS_PENDING) {
|
|
2259 |
hwInit_BootSm (hHwInit);
|
|
2260 |
}
|
|
2261 |
|
|
2262 |
return TI_OK;
|
|
2263 |
|
|
2264 |
} /* End switch */
|
|
2265 |
|
|
2266 |
} /* End while */
|
|
2267 |
|
|
2268 |
}
|
|
2269 |
|
|
2270 |
|
|
2271 |
/****************************************************************************
|
|
2272 |
* hwInit_InitTopRegisterRead()
|
|
2273 |
****************************************************************************
|
|
2274 |
* DESCRIPTION: hwInit_InitTopRegisterRead
|
|
2275 |
* initalizie hwInit_InitTopRegisterRead SM parmaeters
|
|
2276 |
****************************************************************************/
|
|
2277 |
|
|
2278 |
TI_STATUS hwInit_InitTopRegisterRead(TI_HANDLE hHwInit, TI_UINT32 uAddress)
|
|
2279 |
{
|
|
2280 |
THwInit *pHwInit = (THwInit *)hHwInit;
|
|
2281 |
|
|
2282 |
pHwInit->uTopStage = 0;
|
|
2283 |
uAddress = (TI_UINT32)(uAddress / 2);
|
|
2284 |
uAddress = (uAddress & 0x7FF);
|
|
2285 |
uAddress|= BIT_16 | BIT_17;
|
|
2286 |
pHwInit->uTopRegAddr = uAddress;
|
|
2287 |
|
|
2288 |
return hwInit_TopRegisterRead (hHwInit);
|
|
2289 |
}
|
|
2290 |
|
|
2291 |
|
|
2292 |
/****************************************************************************
|
|
2293 |
* hwInit_TopRegisterRead ()
|
|
2294 |
****************************************************************************
|
|
2295 |
* DESCRIPTION: Generic function that reads to the top registers area
|
|
2296 |
* INPUTS: None
|
|
2297 |
*
|
|
2298 |
* OUTPUT: None
|
|
2299 |
*
|
|
2300 |
* RETURNS: TI_OK or TI_NOK
|
|
2301 |
****************************************************************************/
|
|
2302 |
TI_STATUS hwInit_TopRegisterRead(TI_HANDLE hHwInit)
|
|
2303 |
{
|
|
2304 |
/*
|
|
2305 |
To read from a top level address:
|
|
2306 |
Write the top level address to the OCP_POR_CTR register.
|
|
2307 |
Divide the top address by 2, and add 0x30000 to the result – for example for top address 0xC00, write to the OCP_POR_CTR 0x30600
|
|
2308 |
Write 0x2 to the OCP_CMD register.
|
|
2309 |
Poll bit [18] of OCP_DATA_RD for data valid indication
|
|
2310 |
Check bits 17:16 of OCP_DATA_RD:
|
|
2311 |
00 – no response
|
|
2312 |
01 – data valid / accept
|
|
2313 |
10 – request failed
|
|
2314 |
11 – response error
|
|
2315 |
Read the data from the OCP_DATA_RD register
|
|
2316 |
*/
|
|
2317 |
|
|
2318 |
THwInit *pHwInit = (THwInit *)hHwInit;
|
|
2319 |
TTxnStruct *pTxn;
|
|
2320 |
|
|
2321 |
while (TI_TRUE)
|
|
2322 |
{
|
|
2323 |
switch (pHwInit->uTopStage)
|
|
2324 |
{
|
|
2325 |
case 0:
|
|
2326 |
pHwInit->uTopStage = 1;
|
|
2327 |
pHwInit->uTxnIndex++;
|
|
2328 |
pHwInit->uRegLoop = 0;
|
|
2329 |
|
|
2330 |
/* Write the address to OCP_POR_CTR*/
|
|
2331 |
BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, OCP_POR_CTR, pHwInit->uTopRegAddr,
|
|
2332 |
REGISTER_SIZE, TXN_DIRECTION_WRITE, NULL, NULL)
|
|
2333 |
twIf_Transact(pHwInit->hTwIf, pTxn);
|
|
2334 |
|
|
2335 |
pHwInit->uTxnIndex++;
|
|
2336 |
BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, OCP_CMD, 0x2,
|
|
2337 |
REGISTER_SIZE, TXN_DIRECTION_WRITE, NULL, NULL)
|
|
2338 |
twIf_Transact(pHwInit->hTwIf, pTxn);
|
|
2339 |
|
|
2340 |
continue;
|
|
2341 |
|
|
2342 |
case 1:
|
|
2343 |
pHwInit->uTopStage ++;
|
|
2344 |
pHwInit->uTxnIndex++;
|
|
2345 |
|
|
2346 |
BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, OCP_DATA_RD, 0,
|
|
2347 |
REGISTER_SIZE, TXN_DIRECTION_READ, (TTxnDoneCb)hwInit_TopRegisterRead, hHwInit)
|
|
2348 |
pHwInit->uTopStatus = twIf_Transact(pHwInit->hTwIf, pTxn);
|
|
2349 |
|
|
2350 |
EXCEPT (pHwInit, pHwInit->uTopStatus)
|
|
2351 |
|
|
2352 |
case 2:
|
|
2353 |
/* get the value from IRQ Polarity register*/
|
|
2354 |
pHwInit->uTopRegValue = *((TI_UINT32*)(pHwInit->aHwInitTxn[pHwInit->uTxnIndex].pData));
|
|
2355 |
|
|
2356 |
pHwInit->uTxnIndex = 0;
|
|
2357 |
|
|
2358 |
/*Poll bit 18 of OCP_DATA_RD for data valid indication*/
|
|
2359 |
if (pHwInit->uTopRegValue & BIT_18)
|
|
2360 |
{
|
|
2361 |
if ((pHwInit->uTopRegValue & BIT_16) && (!(pHwInit->uTopRegValue & BIT_17)))
|
|
2362 |
{
|
|
2363 |
pHwInit->uTopRegValue &= 0xffff;
|
|
2364 |
|
|
2365 |
pHwInit->uTxnIndex = 0;
|
|
2366 |
pHwInit->uRegLoop = 0;
|
|
2367 |
if (pHwInit->uTopStatus == TXN_STATUS_PENDING) {
|
|
2368 |
hwInit_BootSm (hHwInit);
|
|
2369 |
}
|
|
2370 |
return TI_OK;
|
|
2371 |
}
|
|
2372 |
else
|
|
2373 |
{
|
|
2374 |
TRACE0(pHwInit->hReport, REPORT_SEVERITY_ERROR , "can't writing bt_func7_sel\n");
|
|
2375 |
if (pHwInit->uTopStatus == TXN_STATUS_PENDING) {
|
|
2376 |
hwInit_BootSm (hHwInit);
|
|
2377 |
}
|
|
2378 |
return TI_NOK;
|
|
2379 |
}
|
|
2380 |
}
|
|
2381 |
else
|
|
2382 |
{
|
|
2383 |
if (pHwInit->uRegLoop < READ_TOP_REG_LOOP)
|
|
2384 |
{
|
|
2385 |
pHwInit->uTopStage = 1;
|
|
2386 |
pHwInit->uRegLoop++;
|
|
2387 |
}
|
|
2388 |
else
|
|
2389 |
{
|
|
2390 |
TRACE0(pHwInit->hReport, REPORT_SEVERITY_ERROR , "Timeout waiting for writing bt_func7_sel\n");
|
|
2391 |
if (pHwInit->uTopStatus == TXN_STATUS_PENDING) {
|
|
2392 |
hwInit_BootSm (hHwInit);
|
|
2393 |
}
|
|
2394 |
return TI_NOK;
|
|
2395 |
}
|
|
2396 |
}
|
|
2397 |
|
|
2398 |
continue;
|
|
2399 |
|
|
2400 |
} /* End switch */
|
|
2401 |
|
|
2402 |
} /* End while */
|
|
2403 |
|
|
2404 |
}
|
|
2405 |
|
|
2406 |
|
|
2407 |
#ifndef _VLCT_
|
|
2408 |
/****************************************************************************
|
|
2409 |
* hwInit_StallTimerCb ()
|
|
2410 |
****************************************************************************
|
|
2411 |
* DESCRIPTION: CB timer function in fTimerFunction format that calls hwInit_StallTimerCb
|
|
2412 |
* INPUTS: TI_HANDLE hHwInit
|
|
2413 |
*
|
|
2414 |
* OUTPUT: None
|
|
2415 |
*
|
|
2416 |
* RETURNS: None
|
|
2417 |
****************************************************************************/
|
|
2418 |
static void hwInit_StallTimerCb (TI_HANDLE hHwInit)
|
|
2419 |
{
|
|
2420 |
hwInit_FinalizeDownloadSm(hHwInit);
|
|
2421 |
}
|
|
2422 |
#endif
|