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1 /* |
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2 * public_host_int.h |
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3 * |
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4 * Copyright(c) 1998 - 2010 Texas Instruments. All rights reserved. |
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5 * All rights reserved. |
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6 * |
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7 * This program and the accompanying materials are made available under the |
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8 * terms of the Eclipse Public License v1.0 or BSD License which accompanies |
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9 * this distribution. The Eclipse Public License is available at |
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10 * http://www.eclipse.org/legal/epl-v10.html and the BSD License is as below. |
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11 * |
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12 * Redistribution and use in source and binary forms, with or without |
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13 * modification, are permitted provided that the following conditions |
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14 * are met: |
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15 * |
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16 * * Redistributions of source code must retain the above copyright |
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17 * notice, this list of conditions and the following disclaimer. |
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18 * * Redistributions in binary form must reproduce the above copyright |
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19 * notice, this list of conditions and the following disclaimer in |
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20 * the documentation and/or other materials provided with the |
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21 * distribution. |
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22 * * Neither the name Texas Instruments nor the names of its |
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23 * contributors may be used to endorse or promote products derived |
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24 * from this software without specific prior written permission. |
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25 * |
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26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
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27 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
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28 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
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29 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
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30 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
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31 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
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32 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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33 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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34 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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35 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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36 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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37 */ |
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38 |
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39 /********************************************************************************************************************** |
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40 |
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41 FILENAME: public_host_int.h |
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42 |
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43 DESCRIPTION: Contains the host interface fw interrupt structure in use. |
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44 |
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45 |
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46 |
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47 ***********************************************************************************************************************/ |
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48 #ifndef PUBLIC_HOST_INT_H |
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49 #define PUBLIC_HOST_INT_H |
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50 |
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51 #include "public_types.h" |
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52 |
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53 |
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54 /************************************************************************* |
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55 |
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56 Host Interrupt Register (WiLink -> Host) |
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57 |
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58 **************************************************************************/ |
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59 #define ACX_INTR_WATCHDOG BIT_0 /* HW Initiated interrupt Watchdog timer expiration */ |
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60 #define ACX_INTR_INIT_COMPLETE BIT_1 /* Init sequence is done (masked interrupt, detection through polling only ) */ |
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61 #define ACX_INTR_EVENT_A BIT_2 /* Event was entered to Event MBOX #A*/ |
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62 #define ACX_INTR_EVENT_B BIT_3 /* Event was entered to Event MBOX #B*/ |
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63 #define ACX_INTR_CMD_COMPLETE BIT_4 /* Command processing completion*/ |
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64 #define ACX_INTR_HW_AVAILABLE BIT_5 /* Signaling the host on HW wakeup */ |
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65 #define ACX_INTR_DATA BIT_6 /* The MISC bit is used for aggregation of RX, TxComplete and TX rate update */ |
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66 #define ACX_INTR_TRACE_A BIT_7 /* Trace meassge on MBOX #A */ |
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67 #define ACX_INTR_TRACE_B BIT_8 /* Trace meassge on MBOX #B */ |
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68 |
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69 #define ACX_INTR_ALL 0xFFFFFFFF |
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70 |
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71 |
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72 /************************************************************************* |
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73 |
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74 Interrupt Trigger Register (Host -> WiLink) |
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75 |
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76 **************************************************************************/ |
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77 |
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78 /******** Hardware to Embedded CPU Interrupts - first 32-bit register set ********/ |
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79 |
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80 #define INTR_TRIG_CMD BIT_0 /* Host Command Interrupt. Setting this bit masks*/ |
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81 /* the interrupt that the host issues to inform*/ |
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82 /* the FW that it has sent a command*/ |
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83 /* to the Wlan hardware Command Mailbox.*/ |
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84 |
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85 #define INTR_TRIG_EVENT_ACK BIT_1 /* Host Event Acknowlegde Interrupt. The host */ |
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86 /* sets this bit to acknowledge that it received*/ |
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87 /* the unsolicited information from the event*/ |
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88 /* mailbox.*/ |
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89 |
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90 #define INTR_TRIG_TX_PROC0 BIT_2 /* OBSOLETE (automatic end-of-transaction interrupt is used instead) */ |
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91 |
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92 #define INTR_TRIG_RX_PROC BIT_3 /* The host sets this bit to inform the FW that */ |
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93 /* it read a packet from the RX cyclic buffer */ |
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94 |
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95 #define INTR_TRIG_DEBUG_ACK BIT_4 |
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96 |
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97 #define INTR_TRIG_STATE_CHANGED BIT_5 |
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98 |
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99 |
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100 /******** Hardware to Embedded CPU Interrupts - second 32-bit register set ********/ |
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101 |
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102 #define INTR_TRIG_RX_PROC1 BIT_17 /* OBSOLETE */ |
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103 |
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104 #define INTR_TRIG_TX_PROC1 BIT_18 /* OBSOLETE */ |
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105 |
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106 |
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107 /************************************************************************* |
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108 |
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109 FW status registers (Host reads from FW upon interrupt from FW) |
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110 |
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111 **************************************************************************/ |
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112 #define NUM_TX_QUEUES 4 /* Number of Tx HW Queues (same as ACs). */ |
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113 #define NUM_RX_PKT_DESC 8 /* Number of Rx packets short descriptors in the W status */ |
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114 |
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115 /* Get field from FwStatus_t->rxPktsDesc[i] */ |
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116 #define RX_DESC_GET_MEM_BLK(desc) ( (desc & 0x000000FF) >> 0 ) /* The first mem-block of the Rx packet */ |
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117 #define RX_DESC_GET_LENGTH(desc) ( (desc & 0x000FFF00) >> 8 ) /* The length of the packet in words */ |
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118 #define RX_DESC_GET_UNALIGNED(desc) ( (desc & 0x00100000) >> 20 ) /* If set, the payload is not 4 bytes aligned */ |
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119 #define RX_DESC_GET_SECURITY(desc) ( (desc & 0x00E00000) >> 21 ) /* Security flag */ |
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120 #define RX_DESC_GET_PACKET_CLASS_TAG(desc) ( (desc & 0xFF000000) >> 24 ) /* Get the RX packet class tag */ |
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121 |
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122 |
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123 /* Set field in FwStatus_t->rxPktsDesc[i] */ |
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124 #define RX_DESC_SET_MEM_BLK(desc, value) ( desc = (desc & ~0x000000FF) | (value << 0 ) ) |
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125 #define RX_DESC_SET_LENGTH(desc, value) ( desc = (desc & ~0x000FFF00) | (value << 8 ) ) |
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126 #define RX_DESC_SET_UNALIGNED(desc, value) ( desc = (desc & ~0x00100000) | (value << 20 ) ) |
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127 |
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128 /* The content of the "counters" field in FwStatus_t - see below */ |
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129 typedef struct |
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130 { |
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131 uint8 fwRxCntr; /* Incremented by FW upon adding pending Rx entry to aRxPktsDesc */ |
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132 uint8 drvRxCntr; /* Incremented by FW upon RX host slave interrupt (for debug) */ |
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133 uint8 reserved; |
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134 uint8 txResultsCntr; /* Incremented by FW upon adding Tx-Result to the TxResultQueue */ |
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135 } FwStatCntrs_t; |
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136 |
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137 /* The FW status registers structure read by the host upon interrupt from the FW */ |
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138 typedef struct |
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139 { |
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140 uint32 intrStatus; /* HINT register content (will be cleared upon the read) */ |
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141 uint32 counters; /* The counters defined in FwStatCntrs_t - see above */ |
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142 uint32 rxPktsDesc[NUM_RX_PKT_DESC]; /* Array of Rx packets short descriptors (see RX_DESC_SET/GET...) */ |
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143 uint32 txReleasedBlks[NUM_TX_QUEUES]; /* Per queue released blocks count since FW-reset */ |
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144 uint32 fwLocalTime; /* FW time in usec, used for clock synchronization with the host */ |
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145 uint32 spare[2]; /* Total structure size is 68 bytes */ |
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146 } FwStatus_t; |
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147 |
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148 #endif |
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149 |
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150 |