|
1 /* |
|
2 * Device.h |
|
3 * |
|
4 * Copyright(c) 1998 - 2010 Texas Instruments. All rights reserved. |
|
5 * All rights reserved. |
|
6 * |
|
7 * This program and the accompanying materials are made available under the |
|
8 * terms of the Eclipse Public License v1.0 or BSD License which accompanies |
|
9 * this distribution. The Eclipse Public License is available at |
|
10 * http://www.eclipse.org/legal/epl-v10.html and the BSD License is as below. |
|
11 * |
|
12 * Redistribution and use in source and binary forms, with or without |
|
13 * modification, are permitted provided that the following conditions |
|
14 * are met: |
|
15 * |
|
16 * * Redistributions of source code must retain the above copyright |
|
17 * notice, this list of conditions and the following disclaimer. |
|
18 * * Redistributions in binary form must reproduce the above copyright |
|
19 * notice, this list of conditions and the following disclaimer in |
|
20 * the documentation and/or other materials provided with the |
|
21 * distribution. |
|
22 * * Neither the name Texas Instruments nor the names of its |
|
23 * contributors may be used to endorse or promote products derived |
|
24 * from this software without specific prior written permission. |
|
25 * |
|
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
|
27 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
|
28 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
|
29 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
|
30 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
|
31 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
|
32 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
|
33 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
|
34 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
|
35 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
|
36 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
|
37 */ |
|
38 |
|
39 |
|
40 /**************************************************************************** |
|
41 * |
|
42 * MODULE: Device.h |
|
43 * PURPOSE: Contains Wlan hardware registers defines/structures |
|
44 * |
|
45 ****************************************************************************/ |
|
46 |
|
47 #ifndef DEVICE_H |
|
48 #define DEVICE_H |
|
49 |
|
50 #include "Device1273.h" |
|
51 |
|
52 |
|
53 #define ACX_PHI_CCA_THRSH_ENABLE_ENERGY_D 0x140A |
|
54 #define ACX_PHI_CCA_THRSH_DISABLE_ENERGY_D 0xFFEF |
|
55 |
|
56 /* |
|
57 * Wlan hardware Registers. |
|
58 */ |
|
59 |
|
60 /*====================================================================== |
|
61 Interrupt Registers |
|
62 =======================================================================*/ |
|
63 |
|
64 #define ACX_REG_INTERRUPT_TRIG ( INT_TRIG ) |
|
65 |
|
66 #define ACX_REG_INTERRUPT_TRIG_H ( INT_TRIG_H ) |
|
67 |
|
68 /*============================================= |
|
69 Host Interrupt Mask Register - 32bit (RW) |
|
70 ------------------------------------------ |
|
71 Setting a bit in this register masks the |
|
72 corresponding interrupt to the host. |
|
73 0 - RX0 - Rx first dubble buffer Data Interrupt |
|
74 1 - TXD - Tx Data Interrupt |
|
75 2 - TXXFR - Tx Transfer Interrupt |
|
76 3 - RX1 - Rx second dubble buffer Data Interrupt |
|
77 4 - RXXFR - Rx Transfer Interrupt |
|
78 5 - EVENT_A - Event Mailbox interrupt |
|
79 6 - EVENT_B - Event Mailbox interrupt |
|
80 7 - WNONHST - Wake On Host Interrupt |
|
81 8 - TRACE_A - Debug Trace interrupt |
|
82 9 - TRACE_B - Debug Trace interrupt |
|
83 10 - CDCMP - Command Complete Interrupt |
|
84 11 - |
|
85 12 - |
|
86 13 - |
|
87 14 - ICOMP - Initialization Complete Interrupt |
|
88 16 - SG SE - Soft Gemini - Sense enable interrupt |
|
89 17 - SG SD - Soft Gemini - Sense disable interrupt |
|
90 18 - - |
|
91 19 - - |
|
92 20 - - |
|
93 21- - |
|
94 Default: 0x0001 |
|
95 *==============================================*/ |
|
96 #define ACX_REG_INTERRUPT_MASK ( HINT_MASK ) |
|
97 |
|
98 /*============================================= |
|
99 Host Interrupt Mask Set 16bit, (Write only) |
|
100 ------------------------------------------ |
|
101 Setting a bit in this register sets |
|
102 the corresponding bin in ACX_HINT_MASK register |
|
103 without effecting the mask |
|
104 state of other bits (0 = no effect). |
|
105 ==============================================*/ |
|
106 #define ACX_HINT_MASK_SET_REG HINT_MASK_SET |
|
107 |
|
108 /*============================================= |
|
109 Host Interrupt Mask Clear 16bit,(Write only) |
|
110 ------------------------------------------ |
|
111 Setting a bit in this register clears |
|
112 the corresponding bin in ACX_HINT_MASK register |
|
113 without effecting the mask |
|
114 state of other bits (0 = no effect). |
|
115 =============================================*/ |
|
116 #define ACX_HINT_MASK_CLR_REG HINT_MASK_CLR |
|
117 |
|
118 /*============================================= |
|
119 Host Interrupt Status Nondestructive Read |
|
120 16bit,(Read only) |
|
121 ------------------------------------------ |
|
122 The host can read this register to determine |
|
123 which interrupts are active. |
|
124 Reading this register doesn't |
|
125 effect its content. |
|
126 =============================================*/ |
|
127 #define ACX_REG_INTERRUPT_NO_CLEAR ( HINT_STS_ND ) |
|
128 |
|
129 /*============================================= |
|
130 Host Interrupt Status Clear on Read Register |
|
131 16bit,(Read only) |
|
132 ------------------------------------------ |
|
133 The host can read this register to determine |
|
134 which interrupts are active. |
|
135 Reading this register clears it, |
|
136 thus making all interrupts inactive. |
|
137 ==============================================*/ |
|
138 #define ACX_REG_INTERRUPT_CLEAR ( HINT_STS_CLR ) |
|
139 |
|
140 /*============================================= |
|
141 Host Interrupt Acknowledge Register |
|
142 16bit,(Write only) |
|
143 ------------------------------------------ |
|
144 The host can set individual bits in this |
|
145 register to clear (acknowledge) the corresp. |
|
146 interrupt status bits in the HINT_STS_CLR and |
|
147 HINT_STS_ND registers, thus making the |
|
148 assotiated interrupt inactive. (0-no effect) |
|
149 ==============================================*/ |
|
150 #define ACX_REG_INTERRUPT_ACK ( HINT_ACK ) |
|
151 |
|
152 |
|
153 /*=============================================== |
|
154 Host Software Reset - 32bit RW |
|
155 ------------------------------------------ |
|
156 [31:1] Reserved |
|
157 0 SOFT_RESET Soft Reset - When this bit is set, |
|
158 it holds the Wlan hardware in a soft reset state. |
|
159 This reset disables all MAC and baseband processor |
|
160 clocks except the CardBus/PCI interface clock. |
|
161 It also initializes all MAC state machines except |
|
162 the host interface. It does not reload the |
|
163 contents of the EEPROM. When this bit is cleared |
|
164 (not self-clearing), the Wlan hardware |
|
165 exits the software reset state. |
|
166 ===============================================*/ |
|
167 #define ACX_REG_SLV_SOFT_RESET ( SLV_SOFT_RESET ) |
|
168 #define SLV_SOFT_RESET_BIT 0x00000001 |
|
169 |
|
170 /*=============================================== |
|
171 EEPROM Burst Read Start - 32bit RW |
|
172 ------------------------------------------ |
|
173 [31:1] Reserved |
|
174 0 ACX_EE_START - EEPROM Burst Read Start 0 |
|
175 Setting this bit starts a burst read from |
|
176 the external EEPROM. |
|
177 If this bit is set (after reset) before an EEPROM read/write, |
|
178 the burst read starts at EEPROM address 0. |
|
179 Otherwise, it starts at the address |
|
180 following the address of the previous access. |
|
181 TheWlan hardware hardware clears this bit automatically. |
|
182 |
|
183 Default: 0x00000000 |
|
184 *================================================*/ |
|
185 #define ACX_REG_EE_START ( EE_START ) |
|
186 #define START_EEPROM_MGR 0x00000001 |
|
187 |
|
188 /*======================================================================= |
|
189 Embedded ARM CPU Control |
|
190 ========================================================================*/ |
|
191 /*=============================================== |
|
192 Halt eCPU - 32bit RW |
|
193 ------------------------------------------ |
|
194 0 HALT_ECPU Halt Embedded CPU - This bit is the |
|
195 compliment of bit 1 (MDATA2) in the SOR_CFG register. |
|
196 During a hardware reset, this bit holds |
|
197 the inverse of MDATA2. |
|
198 When downloading firmware from the host, |
|
199 set this bit (pull down MDATA2). |
|
200 The host clears this bit after downloading the firmware into |
|
201 zero-wait-state SSRAM. |
|
202 When loading firmware from Flash, clear this bit (pull up MDATA2) |
|
203 so that the eCPU can run the bootloader code in Flash |
|
204 HALT_ECPU eCPU State |
|
205 -------------------- |
|
206 1 halt eCPU |
|
207 0 enable eCPU |
|
208 ===============================================*/ |
|
209 #define ACX_REG_ECPU_CONTROL ( ECPU_CTRL ) |
|
210 |
|
211 |
|
212 /*======================================================================= |
|
213 Command/Information Mailbox Pointers |
|
214 ========================================================================*/ |
|
215 |
|
216 /*=============================================== |
|
217 Command Mailbox Pointer - 32bit RW |
|
218 ------------------------------------------ |
|
219 This register holds the start address of |
|
220 the command mailbox located in the Wlan hardware memory. |
|
221 The host must read this pointer after a reset to |
|
222 find the location of the command mailbox. |
|
223 The Wlan hardware initializes the command mailbox |
|
224 pointer with the default address of the command mailbox. |
|
225 The command mailbox pointer is not valid until after |
|
226 the host receives the Init Complete interrupt from |
|
227 the Wlan hardware. |
|
228 ===============================================*/ |
|
229 #define REG_COMMAND_MAILBOX_PTR ( SCR_PAD0 ) |
|
230 |
|
231 /*=============================================== |
|
232 Information Mailbox Pointer - 32bit RW |
|
233 ------------------------------------------ |
|
234 This register holds the start address of |
|
235 the information mailbox located in the Wlan hardware memory. |
|
236 The host must read this pointer after a reset to find |
|
237 the location of the information mailbox. |
|
238 The Wlan hardware initializes the information mailbox pointer |
|
239 with the default address of the information mailbox. |
|
240 The information mailbox pointer is not valid |
|
241 until after the host receives the Init Complete interrupt from |
|
242 the Wlan hardware. |
|
243 ===============================================*/ |
|
244 #define REG_EVENT_MAILBOX_PTR ( SCR_PAD1 ) |
|
245 |
|
246 |
|
247 /*======================================================================= |
|
248 Misc |
|
249 ========================================================================*/ |
|
250 |
|
251 |
|
252 #define REG_ENABLE_TX_RX ( IO_CONTROL_ENABLE ) |
|
253 /* |
|
254 * Rx configuration (filter) information element |
|
255 * --------------------------------------------- |
|
256 */ |
|
257 #define REG_RX_CONFIG ( RX_CFG ) |
|
258 #define REG_RX_FILTER ( RX_FILTER_CFG ) |
|
259 |
|
260 #define RX_CFG_ENABLE_PHY_HEADER_PLCP 0x0002 |
|
261 #define RX_CFG_PROMISCUOUS 0x0008 /* promiscuous - receives all valid frames */ |
|
262 #define RX_CFG_BSSID 0x0020 /* receives frames from any BSSID */ |
|
263 #define RX_CFG_MAC 0x0010 /* receives frames destined to any MAC address */ |
|
264 #define RX_CFG_ENABLE_ONLY_MY_DEST_MAC 0x0010 |
|
265 #define RX_CFG_ENABLE_ANY_DEST_MAC 0x0000 |
|
266 #define RX_CFG_ENABLE_ONLY_MY_BSSID 0x0020 |
|
267 #define RX_CFG_ENABLE_ANY_BSSID 0x0000 |
|
268 #define RX_CFG_DISABLE_BCAST 0x0200 /* discards all broadcast frames */ |
|
269 #define RX_CFG_ENABLE_ONLY_MY_SSID 0x0400 |
|
270 #define RX_CFG_ENABLE_RX_CMPLT_FCS_ERROR 0x0800 |
|
271 #define RX_CFG_COPY_RX_STATUS 0x2000 |
|
272 #define RX_CFG_TSF 0x10000 |
|
273 |
|
274 #define RX_CONFIG_OPTION_ANY_DST_MY_BSS ( RX_CFG_ENABLE_ANY_DEST_MAC | RX_CFG_ENABLE_ONLY_MY_BSSID) |
|
275 #define RX_CONFIG_OPTION_MY_DST_ANY_BSS ( RX_CFG_ENABLE_ONLY_MY_DEST_MAC | RX_CFG_ENABLE_ANY_BSSID) |
|
276 #define RX_CONFIG_OPTION_ANY_DST_ANY_BSS ( RX_CFG_ENABLE_ANY_DEST_MAC | RX_CFG_ENABLE_ANY_BSSID) |
|
277 #define RX_CONFIG_OPTION_MY_DST_MY_BSS ( RX_CFG_ENABLE_ONLY_MY_DEST_MAC | RX_CFG_ENABLE_ONLY_MY_BSSID) |
|
278 |
|
279 #define RX_CONFIG_OPTION_FOR_SCAN ( RX_CFG_ENABLE_PHY_HEADER_PLCP | RX_CFG_ENABLE_RX_CMPLT_FCS_ERROR | RX_CFG_COPY_RX_STATUS | RX_CFG_TSF) |
|
280 #define RX_CONFIG_OPTION_FOR_MEASUREMENT ( RX_CFG_ENABLE_ANY_DEST_MAC ) |
|
281 #define RX_CONFIG_OPTION_FOR_JOIN ( RX_CFG_ENABLE_ONLY_MY_BSSID | RX_CFG_ENABLE_ONLY_MY_DEST_MAC ) |
|
282 #define RX_CONFIG_OPTION_FOR_IBSS_JOIN ( RX_CFG_ENABLE_ONLY_MY_SSID | RX_CFG_ENABLE_ONLY_MY_DEST_MAC ) |
|
283 |
|
284 #define RX_FILTER_OPTION_DEF ( CFG_RX_MGMT_EN | CFG_RX_DATA_EN | CFG_RX_CTL_EN | CFG_RX_RCTS_ACK | CFG_RX_BCN_EN | CFG_RX_AUTH_EN | CFG_RX_ASSOC_EN) |
|
285 #define RX_FILTER_OPTION_FILTER_ALL 0 |
|
286 #define RX_FILTER_OPTION_DEF_PRSP_BCN ( CFG_RX_PRSP_EN | CFG_RX_MGMT_EN | CFG_RX_CTL_EN | CFG_RX_RCTS_ACK | CFG_RX_BCN_EN) |
|
287 #define RX_FILTER_OPTION_JOIN ( CFG_RX_MGMT_EN | CFG_RX_DATA_EN | CFG_RX_CTL_EN | CFG_RX_BCN_EN | CFG_RX_AUTH_EN | CFG_RX_ASSOC_EN | CFG_RX_RCTS_ACK | CFG_RX_PRSP_EN) |
|
288 |
|
289 |
|
290 /*=============================================== |
|
291 Phy regs |
|
292 ===============================================*/ |
|
293 #define ACX_PHY_ADDR_REG SBB_ADDR |
|
294 #define ACX_PHY_DATA_REG SBB_DATA |
|
295 #define ACX_PHY_CTRL_REG SBB_CTL |
|
296 #define ACX_PHY_REG_WR_MASK 0x00000001ul |
|
297 #define ACX_PHY_REG_RD_MASK 0x00000002ul |
|
298 |
|
299 |
|
300 /*=============================================== |
|
301 EEPROM Read/Write Request 32bit RW |
|
302 ------------------------------------------ |
|
303 1 EE_READ - EEPROM Read Request 1 - Setting this bit |
|
304 loads a single byte of data into the EE_DATA |
|
305 register from the EEPROM location specified in |
|
306 the EE_ADDR register. |
|
307 The Wlan hardware hardware clears this bit automatically. |
|
308 EE_DATA is valid when this bit is cleared. |
|
309 0 EE_WRITE - EEPROM Write Request - Setting this bit |
|
310 writes a single byte of data from the EE_DATA register into the |
|
311 EEPROM location specified in the EE_ADDR register. |
|
312 The Wlan hardware hardware clears this bit automatically. |
|
313 *===============================================*/ |
|
314 #define ACX_EE_CTL_REG EE_CTL |
|
315 #define EE_WRITE 0x00000001ul |
|
316 #define EE_READ 0x00000002ul |
|
317 |
|
318 /*=============================================== |
|
319 EEPROM Address - 32bit RW |
|
320 ------------------------------------------ |
|
321 This register specifies the address |
|
322 within the EEPROM from/to which to read/write data. |
|
323 ===============================================*/ |
|
324 #define ACX_EE_ADDR_REG EE_ADDR |
|
325 |
|
326 /*=============================================== |
|
327 EEPROM Data - 32bit RW |
|
328 ------------------------------------------ |
|
329 This register either holds the read 8 bits of |
|
330 data from the EEPROM or the write data |
|
331 to be written to the EEPROM. |
|
332 ===============================================*/ |
|
333 #define ACX_EE_DATA_REG EE_DATA |
|
334 |
|
335 /*=============================================== |
|
336 EEPROM Base Address - 32bit RW |
|
337 ------------------------------------------ |
|
338 This register holds the upper nine bits |
|
339 [23:15] of the 24-bit Wlan hardware memory |
|
340 address for burst reads from EEPROM accesses. |
|
341 The EEPROM provides the lower 15 bits of this address. |
|
342 The MSB of the address from the EEPROM is ignored. |
|
343 ===============================================*/ |
|
344 #define ACX_EE_CFG EE_CFG |
|
345 |
|
346 /*=============================================== |
|
347 GPIO Output Values -32bit, RW |
|
348 ------------------------------------------ |
|
349 [31:16] Reserved |
|
350 [15: 0] Specify the output values (at the output driver inputs) for |
|
351 GPIO[15:0], respectively. |
|
352 ===============================================*/ |
|
353 #define ACX_GPIO_OUT_REG GPIO_OUT |
|
354 #define ACX_MAX_GPIO_LINES 15 |
|
355 |
|
356 /*=============================================== |
|
357 Contention window -32bit, RW |
|
358 ------------------------------------------ |
|
359 [31:26] Reserved |
|
360 [25:16] Max (0x3ff) |
|
361 [15:07] Reserved |
|
362 [06:00] Current contention window value - default is 0x1F |
|
363 ===============================================*/ |
|
364 #define ACX_CONT_WIND_CFG_REG CONT_WIND_CFG |
|
365 #define ACX_CONT_WIND_MIN_MASK 0x0000007f |
|
366 #define ACX_CONT_WIND_MAX 0x03ff0000 |
|
367 |
|
368 /* |
|
369 * Indirect slave register/memory registers |
|
370 * ---------------------------------------- |
|
371 */ |
|
372 #define HW_SLAVE_REG_ADDR_REG 0x00000004 |
|
373 #define HW_SLAVE_REG_DATA_REG 0x00000008 |
|
374 #define HW_SLAVE_REG_CTRL_REG 0x0000000c |
|
375 |
|
376 #define SLAVE_AUTO_INC 0x00010000 |
|
377 #define SLAVE_NO_AUTO_INC 0x00000000 |
|
378 #define SLAVE_HOST_LITTLE_ENDIAN 0x00000000 |
|
379 |
|
380 #define HW_SLAVE_MEM_ADDR_REG SLV_MEM_ADDR |
|
381 #define HW_SLAVE_MEM_DATA_REG SLV_MEM_DATA |
|
382 #define HW_SLAVE_MEM_CTRL_REG SLV_MEM_CTL |
|
383 #define HW_SLAVE_MEM_ENDIAN_REG SLV_END_CTL |
|
384 |
|
385 #define HW_FUNC_EVENT_INT_EN 0x8000 |
|
386 #define HW_FUNC_EVENT_MASK_REG 0x00000034 |
|
387 |
|
388 #define ACX_MAC_TIMESTAMP_REG (MAC_TIMESTAMP) |
|
389 |
|
390 /*=============================================== |
|
391 HI_CFG Interface Configuration Register Values |
|
392 ------------------------------------------ |
|
393 ===============================================*/ |
|
394 #define HI_CFG_UART_ENABLE 0x00000004 |
|
395 #define HI_CFG_RST232_ENABLE 0x00000008 |
|
396 #define HI_CFG_CLOCK_REQ_SELECT 0x00000010 |
|
397 #define HI_CFG_HOST_INT_ENABLE 0x00000020 |
|
398 #define HI_CFG_VLYNQ_OUTPUT_ENABLE 0x00000040 |
|
399 #define HI_CFG_HOST_INT_ACTIVE_LOW 0x00000080 |
|
400 #define HI_CFG_UART_TX_OUT_GPIO_15 0x00000100 |
|
401 #define HI_CFG_UART_TX_OUT_GPIO_14 0x00000200 |
|
402 #define HI_CFG_UART_TX_OUT_GPIO_7 0x00000400 |
|
403 |
|
404 /* |
|
405 * NOTE: USE_ACTIVE_HIGH compilation flag should be defined in makefile |
|
406 * for platforms using active high interrupt level |
|
407 */ |
|
408 #ifdef USE_IRQ_ACTIVE_HIGH |
|
409 #define HI_CFG_DEF_VAL \ |
|
410 HI_CFG_UART_ENABLE | \ |
|
411 HI_CFG_RST232_ENABLE | \ |
|
412 HI_CFG_CLOCK_REQ_SELECT | \ |
|
413 HI_CFG_HOST_INT_ENABLE |
|
414 #else |
|
415 #define HI_CFG_DEF_VAL \ |
|
416 HI_CFG_UART_ENABLE | \ |
|
417 HI_CFG_RST232_ENABLE | \ |
|
418 HI_CFG_CLOCK_REQ_SELECT | \ |
|
419 HI_CFG_HOST_INT_ENABLE | \ |
|
420 HI_CFG_HOST_INT_ACTIVE_LOW |
|
421 #endif |
|
422 |
|
423 #endif /* DEVICE_H */ |
|
424 |