|
1 /* |
|
2 * BusDrv.h |
|
3 * |
|
4 * Copyright(c) 1998 - 2010 Texas Instruments. All rights reserved. |
|
5 * All rights reserved. |
|
6 * |
|
7 * This program and the accompanying materials are made available under the |
|
8 * terms of the Eclipse Public License v1.0 or BSD License which accompanies |
|
9 * this distribution. The Eclipse Public License is available at |
|
10 * http://www.eclipse.org/legal/epl-v10.html and the BSD License is as below. |
|
11 * |
|
12 * Redistribution and use in source and binary forms, with or without |
|
13 * modification, are permitted provided that the following conditions |
|
14 * are met: |
|
15 * |
|
16 * * Redistributions of source code must retain the above copyright |
|
17 * notice, this list of conditions and the following disclaimer. |
|
18 * * Redistributions in binary form must reproduce the above copyright |
|
19 * notice, this list of conditions and the following disclaimer in |
|
20 * the documentation and/or other materials provided with the |
|
21 * distribution. |
|
22 * * Neither the name Texas Instruments nor the names of its |
|
23 * contributors may be used to endorse or promote products derived |
|
24 * from this software without specific prior written permission. |
|
25 * |
|
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
|
27 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
|
28 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
|
29 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
|
30 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
|
31 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
|
32 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
|
33 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
|
34 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
|
35 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
|
36 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
|
37 */ |
|
38 |
|
39 |
|
40 /** \file BusDrv.h |
|
41 * \brief Bus-Driver module API definition |
|
42 * |
|
43 * \see SdioBusDrv.c, WspiBusDrv.c |
|
44 */ |
|
45 |
|
46 #ifndef __BUS_DRV_API_H__ |
|
47 #define __BUS_DRV_API_H__ |
|
48 |
|
49 |
|
50 #include "TxnDefs.h" |
|
51 #include "queue.h" |
|
52 |
|
53 |
|
54 /************************************************************************ |
|
55 * Defines |
|
56 ************************************************************************/ |
|
57 |
|
58 |
|
59 /* In SDIO block-mode: BlkSize = 1 << BlkSizeShift (current block size is: 1<<9 = 512 bytes) */ |
|
60 #define SDIO_BLK_SIZE_SHIFT_MIN 0 |
|
61 #define SDIO_BLK_SIZE_SHIFT_MAX 16 |
|
62 #define SDIO_BLK_SIZE_SHIFT_DEF 9 |
|
63 |
|
64 #define WSPI_PAD_LEN_WRITE 4 |
|
65 #define WSPI_PAD_LEN_READ 8 |
|
66 #define MAX_XFER_BUFS 4 |
|
67 |
|
68 #define TXN_PARAM_STATUS_OK 0 |
|
69 #define TXN_PARAM_STATUS_ERROR 1 |
|
70 #define TXN_PARAM_STATUS_RECOVERY 2 |
|
71 |
|
72 #define TXN_DIRECTION_WRITE 0 |
|
73 #define TXN_DIRECTION_READ 1 |
|
74 |
|
75 #define TXN_FUNC_ID_CTRL 0 |
|
76 #define TXN_FUNC_ID_BT 1 |
|
77 #define TXN_FUNC_ID_WLAN 2 |
|
78 |
|
79 #define TXN_HIGH_PRIORITY 0 |
|
80 #define TXN_LOW_PRIORITY 1 |
|
81 #define TXN_NUM_PRIORITYS 2 |
|
82 |
|
83 #define TXN_INC_ADDR 0 |
|
84 #define TXN_FIXED_ADDR 1 |
|
85 #define TXN_NON_SLEEP_ELP 1 |
|
86 #define TXN_SLEEP_ELP 0 |
|
87 |
|
88 #define TXN_AGGREGATE_OFF 0 |
|
89 #define TXN_AGGREGATE_ON 1 |
|
90 |
|
91 #define NUM_OF_PARTITION 4 |
|
92 |
|
93 /************************************************************************ |
|
94 * Macros |
|
95 ************************************************************************/ |
|
96 /* Get field from TTxnStruct->uTxnParams */ |
|
97 #define TXN_PARAM_GET_PRIORITY(pTxn) ( (pTxn->uTxnParams & 0x00000003) >> 0 ) |
|
98 #define TXN_PARAM_GET_FUNC_ID(pTxn) ( (pTxn->uTxnParams & 0x0000000C) >> 2 ) |
|
99 #define TXN_PARAM_GET_DIRECTION(pTxn) ( (pTxn->uTxnParams & 0x00000010) >> 4 ) |
|
100 #define TXN_PARAM_GET_FIXED_ADDR(pTxn) ( (pTxn->uTxnParams & 0x00000020) >> 5 ) |
|
101 #define TXN_PARAM_GET_MORE(pTxn) ( (pTxn->uTxnParams & 0x00000040) >> 6 ) |
|
102 #define TXN_PARAM_GET_SINGLE_STEP(pTxn) ( (pTxn->uTxnParams & 0x00000080) >> 7 ) |
|
103 #define TXN_PARAM_GET_STATUS(pTxn) ( (pTxn->uTxnParams & 0x00000F00) >> 8 ) |
|
104 #define TXN_PARAM_GET_AGGREGATE(pTxn) ( (pTxn->uTxnParams & 0x00001000) >> 12 ) |
|
105 |
|
106 /* Set field in TTxnStruct->uTxnParams */ |
|
107 #define TXN_PARAM_SET_PRIORITY(pTxn, uValue) ( pTxn->uTxnParams = (pTxn->uTxnParams & ~0x00000003) | (uValue << 0 ) ) |
|
108 #define TXN_PARAM_SET_FUNC_ID(pTxn, uValue) ( pTxn->uTxnParams = (pTxn->uTxnParams & ~0x0000000C) | (uValue << 2 ) ) |
|
109 #define TXN_PARAM_SET_DIRECTION(pTxn, uValue) ( pTxn->uTxnParams = (pTxn->uTxnParams & ~0x00000010) | (uValue << 4 ) ) |
|
110 #define TXN_PARAM_SET_FIXED_ADDR(pTxn, uValue) ( pTxn->uTxnParams = (pTxn->uTxnParams & ~0x00000020) | (uValue << 5 ) ) |
|
111 #define TXN_PARAM_SET_MORE(pTxn, uValue) ( pTxn->uTxnParams = (pTxn->uTxnParams & ~0x00000040) | (uValue << 6 ) ) |
|
112 #define TXN_PARAM_SET_SINGLE_STEP(pTxn, uValue) ( pTxn->uTxnParams = (pTxn->uTxnParams & ~0x00000080) | (uValue << 7 ) ) |
|
113 #define TXN_PARAM_SET_STATUS(pTxn, uValue) ( pTxn->uTxnParams = (pTxn->uTxnParams & ~0x00000F00) | (uValue << 8 ) ) |
|
114 #define TXN_PARAM_SET_AGGREGATE(pTxn, uValue) ( pTxn->uTxnParams = (pTxn->uTxnParams & ~0x00001000) | (uValue << 12 ) ) |
|
115 |
|
116 |
|
117 #define TXN_PARAM_SET(pTxn, uPriority, uId, uDirection, uAddr) \ |
|
118 TXN_PARAM_SET_PRIORITY(pTxn, uPriority); \ |
|
119 TXN_PARAM_SET_FUNC_ID(pTxn, uId); \ |
|
120 TXN_PARAM_SET_DIRECTION(pTxn, uDirection); \ |
|
121 TXN_PARAM_SET_FIXED_ADDR(pTxn, uAddr); |
|
122 |
|
123 #define BUILD_TTxnStruct(pTxn, uAddr, pBuf, uLen, fCB, hCB) \ |
|
124 pTxn->aBuf[0] = (TI_UINT8*)(pBuf); \ |
|
125 pTxn->aLen[0] = (TI_UINT16)(uLen); \ |
|
126 pTxn->aLen[1] = 0; \ |
|
127 pTxn->uHwAddr = uAddr; \ |
|
128 pTxn->hCbHandle = (void*)hCB; \ |
|
129 pTxn->fTxnDoneCb = fCB; |
|
130 |
|
131 |
|
132 /************************************************************************ |
|
133 * Types |
|
134 ************************************************************************/ |
|
135 /* The TxnDone CB called by the bus driver upon Async Txn completion */ |
|
136 typedef void (*TBusDrvTxnDoneCb)(TI_HANDLE hCbHandle, void *pTxn); |
|
137 |
|
138 /* The TxnDone CB called by the TxnQueue upon Async Txn completion */ |
|
139 typedef void (*TTxnQueueDoneCb)(TI_HANDLE hCbHandle, void *pTxn); |
|
140 |
|
141 /* The TxnDone CB of the specific Txn originator (Xfer layer) called upon Async Txn completion */ |
|
142 typedef void (*TTxnDoneCb)(TI_HANDLE hCbHandle, void *pTxn); |
|
143 |
|
144 /* The transactions structure */ |
|
145 typedef struct |
|
146 { |
|
147 TQueNodeHdr tTxnQNode; /* Header for queueing */ |
|
148 TI_UINT32 uTxnParams; /* Txn attributes (bit fields) - see macros above */ |
|
149 TI_UINT32 uHwAddr; /* Physical (32 bits) HW Address */ |
|
150 TTxnDoneCb fTxnDoneCb; /* CB called by TwIf upon Async Txn completion (may be NULL) */ |
|
151 TI_HANDLE hCbHandle; /* The handle to use when calling fTxnDoneCb */ |
|
152 TI_UINT16 aLen[MAX_XFER_BUFS]; /* Lengths of the following aBuf data buffers respectively. |
|
153 Zero length marks last used buffer, or MAX_XFER_BUFS of all are used. */ |
|
154 TI_UINT8* aBuf[MAX_XFER_BUFS]; /* Host data buffers to be written to or read from the device */ |
|
155 } TTxnStruct; |
|
156 |
|
157 /* Parameters for all bus types configuration in ConnectBus process */ |
|
158 |
|
159 typedef struct |
|
160 { |
|
161 TI_UINT32 uBlkSizeShift; |
|
162 } TSdioCfg; |
|
163 |
|
164 typedef struct |
|
165 { |
|
166 TI_UINT32 uDummy; |
|
167 } TWspiCfg; |
|
168 |
|
169 typedef struct |
|
170 { |
|
171 TI_UINT32 uBaudRate; |
|
172 } TUartCfg; |
|
173 |
|
174 typedef union |
|
175 { |
|
176 TSdioCfg tSdioCfg; |
|
177 TWspiCfg tWspiCfg; |
|
178 TUartCfg tUartCfg; |
|
179 |
|
180 } TBusDrvCfg; |
|
181 |
|
182 |
|
183 typedef struct |
|
184 { |
|
185 TI_UINT32 uMemAdrr; |
|
186 TI_UINT32 uMemSize; |
|
187 } TPartition; |
|
188 |
|
189 |
|
190 /************************************************************************ |
|
191 * Functions |
|
192 ************************************************************************/ |
|
193 TI_HANDLE busDrv_Create (TI_HANDLE hOs); |
|
194 TI_STATUS busDrv_Destroy (TI_HANDLE hBusDrv); |
|
195 void busDrv_Init (TI_HANDLE hBusDrv, TI_HANDLE hReport); |
|
196 TI_STATUS busDrv_ConnectBus (TI_HANDLE hBusDrv, |
|
197 TBusDrvCfg *pBusDrvCfg, |
|
198 TBusDrvTxnDoneCb fCbFunc, |
|
199 TI_HANDLE hCbArg, |
|
200 TBusDrvTxnDoneCb fConnectCbFunc); |
|
201 TI_STATUS busDrv_DisconnectBus (TI_HANDLE hBusDrv); |
|
202 ETxnStatus busDrv_Transact (TI_HANDLE hBusDrv, TTxnStruct *pTxn); |
|
203 TI_HANDLE busDrv_Cfg (TI_HANDLE hOs); |
|
204 |
|
205 |
|
206 |
|
207 #endif /*__BUS_DRV_API_H__*/ |
|
208 |