/*

 * Copyright (C) 2008 Apple Inc.

 * Copyright (C) 2009, 2010 University of Szeged

 * All rights reserved.

 *

 * Redistribution and use in source and binary forms, with or without

 * modification, are permitted provided that the following conditions

 * are met:

 * 1. Redistributions of source code must retain the above copyright

 *    notice, this list of conditions and the following disclaimer.

 * 2. Redistributions in binary form must reproduce the above copyright

 *    notice, this list of conditions and the following disclaimer in the

 *    documentation and/or other materials provided with the distribution.

 *

 * THIS SOFTWARE IS PROVIDED BY APPLE INC. ``AS IS'' AND ANY

 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR

 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL APPLE INC. OR

 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,

 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,

 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR

 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY

 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT

 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE

 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 */

#ifndef MacroAssemblerARM_h

#define MacroAssemblerARM_h

#if ENABLE(ASSEMBLER) && CPU(ARM_TRADITIONAL)

#include "ARMAssembler.h"

#include "AbstractMacroAssembler.h"

namespace JSC {

class MacroAssemblerARM : public AbstractMacroAssembler<ARMAssembler> {

    static const int DoubleConditionMask = 0x0f;

    static const int DoubleConditionBitSpecial = 0x10;

    COMPILE_ASSERT(!(DoubleConditionBitSpecial & DoubleConditionMask), DoubleConditionBitSpecial_should_not_interfere_with_ARMAssembler_Condition_codes);

public:

    typedef ARMRegisters::FPRegisterID FPRegisterID;

    enum Condition {

        Equal = ARMAssembler::EQ,

        NotEqual = ARMAssembler::NE,

        Above = ARMAssembler::HI,

        AboveOrEqual = ARMAssembler::CS,

        Below = ARMAssembler::CC,

        BelowOrEqual = ARMAssembler::LS,

        GreaterThan = ARMAssembler::GT,

        GreaterThanOrEqual = ARMAssembler::GE,

        LessThan = ARMAssembler::LT,

        LessThanOrEqual = ARMAssembler::LE,

        Overflow = ARMAssembler::VS,

        Signed = ARMAssembler::MI,

        Zero = ARMAssembler::EQ,

        NonZero = ARMAssembler::NE

    };

    enum DoubleCondition {

        // These conditions will only evaluate to true if the comparison is ordered - i.e. neither operand is NaN.

        DoubleEqual = ARMAssembler::EQ,

        DoubleNotEqual = ARMAssembler::NE | DoubleConditionBitSpecial,

        DoubleGreaterThan = ARMAssembler::GT,

        DoubleGreaterThanOrEqual = ARMAssembler::GE,

        DoubleLessThan = ARMAssembler::CC,

        DoubleLessThanOrEqual = ARMAssembler::LS,

        // If either operand is NaN, these conditions always evaluate to true.

        DoubleEqualOrUnordered = ARMAssembler::EQ | DoubleConditionBitSpecial,

        DoubleNotEqualOrUnordered = ARMAssembler::NE,

        DoubleGreaterThanOrUnordered = ARMAssembler::HI,

        DoubleGreaterThanOrEqualOrUnordered = ARMAssembler::CS,

        DoubleLessThanOrUnordered = ARMAssembler::LT,

        DoubleLessThanOrEqualOrUnordered = ARMAssembler::LE,

    };

    static const RegisterID stackPointerRegister = ARMRegisters::sp;

    static const RegisterID linkRegister = ARMRegisters::lr;

    static const Scale ScalePtr = TimesFour;

    void add32(RegisterID src, RegisterID dest)

    {

        m_assembler.adds_r(dest, dest, src);

    }

    void add32(Imm32 imm, Address address)

    {

        load32(address, ARMRegisters::S1);

        add32(imm, ARMRegisters::S1);

        store32(ARMRegisters::S1, address);

    }

    void add32(Imm32 imm, RegisterID dest)

    {

        m_assembler.adds_r(dest, dest, m_assembler.getImm(imm.m_value, ARMRegisters::S0));

    }

    void add32(Address src, RegisterID dest)

    {

        load32(src, ARMRegisters::S1);

        add32(ARMRegisters::S1, dest);

    }

    void and32(RegisterID src, RegisterID dest)

    {

        m_assembler.ands_r(dest, dest, src);

    }

    void and32(Imm32 imm, RegisterID dest)

    {

        ARMWord w = m_assembler.getImm(imm.m_value, ARMRegisters::S0, true);

        if (w & ARMAssembler::OP2_INV_IMM)

            m_assembler.bics_r(dest, dest, w & ~ARMAssembler::OP2_INV_IMM);

        else

            m_assembler.ands_r(dest, dest, w);

    }

    void lshift32(RegisterID shift_amount, RegisterID dest)

    {

        ARMWord w = ARMAssembler::getOp2(0x1f);

        ASSERT(w != ARMAssembler::INVALID_IMM);

        m_assembler.and_r(ARMRegisters::S0, shift_amount, w);

        m_assembler.movs_r(dest, m_assembler.lsl_r(dest, ARMRegisters::S0));

    }

    void lshift32(Imm32 imm, RegisterID dest)

    {

        m_assembler.movs_r(dest, m_assembler.lsl(dest, imm.m_value & 0x1f));

    }

    void mul32(RegisterID src, RegisterID dest)

    {

        if (src == dest) {

            move(src, ARMRegisters::S0);

            src = ARMRegisters::S0;

        }

        m_assembler.muls_r(dest, dest, src);

    }

    void mul32(Imm32 imm, RegisterID src, RegisterID dest)

    {

        move(imm, ARMRegisters::S0);

        m_assembler.muls_r(dest, src, ARMRegisters::S0);

    }

    void neg32(RegisterID srcDest)

    {

        m_assembler.rsbs_r(srcDest, srcDest, ARMAssembler::getOp2(0));

    }

    void not32(RegisterID dest)

    {

        m_assembler.mvns_r(dest, dest);

    }

    void or32(RegisterID src, RegisterID dest)

    {

        m_assembler.orrs_r(dest, dest, src);

    }

    void or32(Imm32 imm, RegisterID dest)

    {

        m_assembler.orrs_r(dest, dest, m_assembler.getImm(imm.m_value, ARMRegisters::S0));

    }

    void rshift32(RegisterID shift_amount, RegisterID dest)

    {

        ARMWord w = ARMAssembler::getOp2(0x1f);

        ASSERT(w != ARMAssembler::INVALID_IMM);

        m_assembler.and_r(ARMRegisters::S0, shift_amount, w);

        m_assembler.movs_r(dest, m_assembler.asr_r(dest, ARMRegisters::S0));

    }

    void rshift32(Imm32 imm, RegisterID dest)

    {

        m_assembler.movs_r(dest, m_assembler.asr(dest, imm.m_value & 0x1f));

    }

    void urshift32(RegisterID shift_amount, RegisterID dest)

    {

        ARMWord w = ARMAssembler::getOp2(0x1f);

        ASSERT(w != ARMAssembler::INVALID_IMM);

        m_assembler.and_r(ARMRegisters::S0, shift_amount, w);

        m_assembler.movs_r(dest, m_assembler.lsr_r(dest, ARMRegisters::S0));

    }

    void urshift32(Imm32 imm, RegisterID dest)

    {

        m_assembler.movs_r(dest, m_assembler.lsr(dest, imm.m_value & 0x1f));

    }

    void sub32(RegisterID src, RegisterID dest)

    {

        m_assembler.subs_r(dest, dest, src);

    }

    void sub32(Imm32 imm, RegisterID dest)

    {

        m_assembler.subs_r(dest, dest, m_assembler.getImm(imm.m_value, ARMRegisters::S0));

    }

    void sub32(Imm32 imm, Address address)

    {

        load32(address, ARMRegisters::S1);

        sub32(imm, ARMRegisters::S1);

        store32(ARMRegisters::S1, address);

    }

    void sub32(Address src, RegisterID dest)

    {

        load32(src, ARMRegisters::S1);

        sub32(ARMRegisters::S1, dest);

    }

    void xor32(RegisterID src, RegisterID dest)

    {

        m_assembler.eors_r(dest, dest, src);

    }

    void xor32(Imm32 imm, RegisterID dest)

    {

        m_assembler.eors_r(dest, dest, m_assembler.getImm(imm.m_value, ARMRegisters::S0));

    }

    void load8(ImplicitAddress address, RegisterID dest)

    {

        m_assembler.dataTransfer32(true, dest, address.base, address.offset, true);

    }

    void load32(ImplicitAddress address, RegisterID dest)

    {

        m_assembler.dataTransfer32(true, dest, address.base, address.offset);

    }

    void load32(BaseIndex address, RegisterID dest)

    {

        m_assembler.baseIndexTransfer32(true, dest, address.base, address.index, static_cast<int>(address.scale), address.offset);

    }

#if CPU(ARMV5_OR_LOWER)

    void load32WithUnalignedHalfWords(BaseIndex address, RegisterID dest);

#else

    void load32WithUnalignedHalfWords(BaseIndex address, RegisterID dest)

    {

        load32(address, dest);

    }

#endif

    DataLabel32 load32WithAddressOffsetPatch(Address address, RegisterID dest)

    {

        DataLabel32 dataLabel(this);

        m_assembler.ldr_un_imm(ARMRegisters::S0, 0);

        m_assembler.dtr_ur(true, dest, address.base, ARMRegisters::S0);

        return dataLabel;

    }

    Label loadPtrWithPatchToLEA(Address address, RegisterID dest)

    {

        Label label(this);

        load32(address, dest);

        return label;

    }

    void load16(BaseIndex address, RegisterID dest)

    {

        m_assembler.add_r(ARMRegisters::S1, address.base, m_assembler.lsl(address.index, address.scale));

        load16(Address(ARMRegisters::S1, address.offset), dest);

    }

    void load16(ImplicitAddress address, RegisterID dest)

    {

        if (address.offset >= 0)

            m_assembler.ldrh_u(dest, address.base, m_assembler.getOffsetForHalfwordDataTransfer(address.offset, ARMRegisters::S0));

        else

            m_assembler.ldrh_d(dest, address.base, m_assembler.getOffsetForHalfwordDataTransfer(-address.offset, ARMRegisters::S0));

    }

    DataLabel32 store32WithAddressOffsetPatch(RegisterID src, Address address)

    {

        DataLabel32 dataLabel(this);

        m_assembler.ldr_un_imm(ARMRegisters::S0, 0);

        m_assembler.dtr_ur(false, src, address.base, ARMRegisters::S0);

        return dataLabel;

    }

    void store32(RegisterID src, ImplicitAddress address)

    {

        m_assembler.dataTransfer32(false, src, address.base, address.offset);

    }

    void store32(RegisterID src, BaseIndex address)

    {

        m_assembler.baseIndexTransfer32(false, src, address.base, address.index, static_cast<int>(address.scale), address.offset);

    }

    void store32(Imm32 imm, ImplicitAddress address)

    {

        if (imm.m_isPointer)

            m_assembler.ldr_un_imm(ARMRegisters::S1, imm.m_value);

        else

            move(imm, ARMRegisters::S1);

        store32(ARMRegisters::S1, address);

    }

    void store32(RegisterID src, void* address)

    {

        m_assembler.ldr_un_imm(ARMRegisters::S0, reinterpret_cast<ARMWord>(address));

        m_assembler.dtr_u(false, src, ARMRegisters::S0, 0);

    }

    void store32(Imm32 imm, void* address)

    {

        m_assembler.ldr_un_imm(ARMRegisters::S0, reinterpret_cast<ARMWord>(address));

        if (imm.m_isPointer)

            m_assembler.ldr_un_imm(ARMRegisters::S1, imm.m_value);

        else

            m_assembler.moveImm(imm.m_value, ARMRegisters::S1);

        m_assembler.dtr_u(false, ARMRegisters::S1, ARMRegisters::S0, 0);

    }

    void pop(RegisterID dest)

    {

        m_assembler.pop_r(dest);

    }

    void push(RegisterID src)

    {

        m_assembler.push_r(src);

    }

    void push(Address address)

    {

        load32(address, ARMRegisters::S1);

        push(ARMRegisters::S1);

    }

    void push(Imm32 imm)

    {

        move(imm, ARMRegisters::S0);

        push(ARMRegisters::S0);

    }

    void move(Imm32 imm, RegisterID dest)

    {

        if (imm.m_isPointer)

            m_assembler.ldr_un_imm(dest, imm.m_value);

        else

            m_assembler.moveImm(imm.m_value, dest);

    }

    void move(RegisterID src, RegisterID dest)

    {

        m_assembler.mov_r(dest, src);

    }

    void move(ImmPtr imm, RegisterID dest)

    {

        move(Imm32(imm), dest);

    }

    void swap(RegisterID reg1, RegisterID reg2)

    {

        m_assembler.mov_r(ARMRegisters::S0, reg1);

        m_assembler.mov_r(reg1, reg2);

        m_assembler.mov_r(reg2, ARMRegisters::S0);

    }

    void signExtend32ToPtr(RegisterID src, RegisterID dest)

    {

        if (src != dest)

            move(src, dest);

    }

    void zeroExtend32ToPtr(RegisterID src, RegisterID dest)

    {

        if (src != dest)

            move(src, dest);

    }

    Jump branch8(Condition cond, Address left, Imm32 right)

    {

        load8(left, ARMRegisters::S1);

        return branch32(cond, ARMRegisters::S1, right);

    }

    Jump branch32(Condition cond, RegisterID left, RegisterID right, int useConstantPool = 0)

    {

        m_assembler.cmp_r(left, right);

        return Jump(m_assembler.jmp(ARMCondition(cond), useConstantPool));

    }

    Jump branch32(Condition cond, RegisterID left, Imm32 right, int useConstantPool = 0)

    {

        if (right.m_isPointer) {

            m_assembler.ldr_un_imm(ARMRegisters::S0, right.m_value);

            m_assembler.cmp_r(left, ARMRegisters::S0);

        } else

            m_assembler.cmp_r(left, m_assembler.getImm(right.m_value, ARMRegisters::S0));

        return Jump(m_assembler.jmp(ARMCondition(cond), useConstantPool));

    }

    Jump branch32(Condition cond, RegisterID left, Address right)

    {

        load32(right, ARMRegisters::S1);

        return branch32(cond, left, ARMRegisters::S1);

    }

    Jump branch32(Condition cond, Address left, RegisterID right)

    {

        load32(left, ARMRegisters::S1);

        return branch32(cond, ARMRegisters::S1, right);

    }

    Jump branch32(Condition cond, Address left, Imm32 right)

    {

        load32(left, ARMRegisters::S1);

        return branch32(cond, ARMRegisters::S1, right);

    }

    Jump branch32(Condition cond, BaseIndex left, Imm32 right)

    {

        load32(left, ARMRegisters::S1);

        return branch32(cond, ARMRegisters::S1, right);

    }

    Jump branch32WithUnalignedHalfWords(Condition cond, BaseIndex left, Imm32 right)

    {

        load32WithUnalignedHalfWords(left, ARMRegisters::S1);

        return branch32(cond, ARMRegisters::S1, right);

    }

    Jump branch16(Condition cond, BaseIndex left, RegisterID right)

    {

        UNUSED_PARAM(cond);

        UNUSED_PARAM(left);

        UNUSED_PARAM(right);

        ASSERT_NOT_REACHED();

        return jump();

    }

    Jump branch16(Condition cond, BaseIndex left, Imm32 right)

    {

        load16(left, ARMRegisters::S0);

        move(right, ARMRegisters::S1);

        m_assembler.cmp_r(ARMRegisters::S0, ARMRegisters::S1);

        return m_assembler.jmp(ARMCondition(cond));

    }

    Jump branchTest8(Condition cond, Address address, Imm32 mask = Imm32(-1))

    {

        load8(address, ARMRegisters::S1);

        return branchTest32(cond, ARMRegisters::S1, mask);

    }

    Jump branchTest32(Condition cond, RegisterID reg, RegisterID mask)

    {

        ASSERT((cond == Zero) || (cond == NonZero));

        m_assembler.tst_r(reg, mask);

        return Jump(m_assembler.jmp(ARMCondition(cond)));

    }

    Jump branchTest32(Condition cond, RegisterID reg, Imm32 mask = Imm32(-1))

    {

        ASSERT((cond == Zero) || (cond == NonZero));

        ARMWord w = m_assembler.getImm(mask.m_value, ARMRegisters::S0, true);

        if (w & ARMAssembler::OP2_INV_IMM)

            m_assembler.bics_r(ARMRegisters::S0, reg, w & ~ARMAssembler::OP2_INV_IMM);

        else

            m_assembler.tst_r(reg, w);

        return Jump(m_assembler.jmp(ARMCondition(cond)));

    }

    Jump branchTest32(Condition cond, Address address, Imm32 mask = Imm32(-1))

    {

        load32(address, ARMRegisters::S1);

        return branchTest32(cond, ARMRegisters::S1, mask);

    }

    Jump branchTest32(Condition cond, BaseIndex address, Imm32 mask = Imm32(-1))

    {

        load32(address, ARMRegisters::S1);

        return branchTest32(cond, ARMRegisters::S1, mask);

    }

    Jump jump()

    {

        return Jump(m_assembler.jmp());

    }

    void jump(RegisterID target)

    {

        m_assembler.bx(target);

    }

    void jump(Address address)

    {

        load32(address, ARMRegisters::pc);

    }

    Jump branchAdd32(Condition cond, RegisterID src, RegisterID dest)

    {

        ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));

        add32(src, dest);

        return Jump(m_assembler.jmp(ARMCondition(cond)));

    }

    Jump branchAdd32(Condition cond, Imm32 imm, RegisterID dest)

    {

        ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));

        add32(imm, dest);

        return Jump(m_assembler.jmp(ARMCondition(cond)));

    }

    void mull32(RegisterID src1, RegisterID src2, RegisterID dest)

    {

        if (src1 == dest) {

            move(src1, ARMRegisters::S0);

            src1 = ARMRegisters::S0;

        }

        m_assembler.mull_r(ARMRegisters::S1, dest, src2, src1);

        m_assembler.cmp_r(ARMRegisters::S1, m_assembler.asr(dest, 31));

    }