/*

 * Copyright (C) 2009 Apple Inc. All rights reserved.

 * Copyright (C) 2010 University of Szeged

 *

 * Redistribution and use in source and binary forms, with or without

 * modification, are permitted provided that the following conditions

 * are met:

 * 1. Redistributions of source code must retain the above copyright

 *    notice, this list of conditions and the following disclaimer.

 * 2. Redistributions in binary form must reproduce the above copyright

 *    notice, this list of conditions and the following disclaimer in the

 *    documentation and/or other materials provided with the distribution.

 *

 * THIS SOFTWARE IS PROVIDED BY APPLE INC. ``AS IS'' AND ANY

 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR

 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL APPLE INC. OR

 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,

 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,

 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR

 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY

 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT

 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE

 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 

 */

#ifndef MacroAssemblerARMv7_h

#define MacroAssemblerARMv7_h

#if ENABLE(ASSEMBLER)

#include "ARMv7Assembler.h"

#include "AbstractMacroAssembler.h"

namespace JSC {

class MacroAssemblerARMv7 : public AbstractMacroAssembler<ARMv7Assembler> {

    // FIXME: switch dataTempRegister & addressTempRegister, or possibly use r7?

    //        - dTR is likely used more than aTR, and we'll get better instruction

    //        encoding if it's in the low 8 registers.

    static const RegisterID dataTempRegister = ARMRegisters::ip;

    static const RegisterID addressTempRegister = ARMRegisters::r3;

    static const ARMRegisters::FPDoubleRegisterID fpTempRegister = ARMRegisters::d7;

    inline ARMRegisters::FPSingleRegisterID fpTempRegisterAsSingle() { return ARMRegisters::asSingle(fpTempRegister); }

public:

    struct ArmAddress {

        enum AddressType {

            HasOffset,

            HasIndex,

        } type;

        RegisterID base;

        union {

            int32_t offset;

            struct {

                RegisterID index;

                Scale scale;

            };

        } u;

        explicit ArmAddress(RegisterID base, int32_t offset = 0)

            : type(HasOffset)

            , base(base)

        {

            u.offset = offset;

        }

        explicit ArmAddress(RegisterID base, RegisterID index, Scale scale = TimesOne)

            : type(HasIndex)

            , base(base)

        {

            u.index = index;

            u.scale = scale;

        }

    };

public:

    typedef ARMRegisters::FPDoubleRegisterID FPRegisterID;

    static const Scale ScalePtr = TimesFour;

    enum Condition {

        Equal = ARMv7Assembler::ConditionEQ,

        NotEqual = ARMv7Assembler::ConditionNE,

        Above = ARMv7Assembler::ConditionHI,

        AboveOrEqual = ARMv7Assembler::ConditionHS,

        Below = ARMv7Assembler::ConditionLO,

        BelowOrEqual = ARMv7Assembler::ConditionLS,

        GreaterThan = ARMv7Assembler::ConditionGT,

        GreaterThanOrEqual = ARMv7Assembler::ConditionGE,

        LessThan = ARMv7Assembler::ConditionLT,

        LessThanOrEqual = ARMv7Assembler::ConditionLE,

        Overflow = ARMv7Assembler::ConditionVS,

        Signed = ARMv7Assembler::ConditionMI,

        Zero = ARMv7Assembler::ConditionEQ,

        NonZero = ARMv7Assembler::ConditionNE

    };

    enum DoubleCondition {

        // These conditions will only evaluate to true if the comparison is ordered - i.e. neither operand is NaN.

        DoubleEqual = ARMv7Assembler::ConditionEQ,

        DoubleNotEqual = ARMv7Assembler::ConditionVC, // Not the right flag! check for this & handle differently.

        DoubleGreaterThan = ARMv7Assembler::ConditionGT,

        DoubleGreaterThanOrEqual = ARMv7Assembler::ConditionGE,

        DoubleLessThan = ARMv7Assembler::ConditionLO,

        DoubleLessThanOrEqual = ARMv7Assembler::ConditionLS,

        // If either operand is NaN, these conditions always evaluate to true.

        DoubleEqualOrUnordered = ARMv7Assembler::ConditionVS, // Not the right flag! check for this & handle differently.

        DoubleNotEqualOrUnordered = ARMv7Assembler::ConditionNE,

        DoubleGreaterThanOrUnordered = ARMv7Assembler::ConditionHI,

        DoubleGreaterThanOrEqualOrUnordered = ARMv7Assembler::ConditionHS,

        DoubleLessThanOrUnordered = ARMv7Assembler::ConditionLT,

        DoubleLessThanOrEqualOrUnordered = ARMv7Assembler::ConditionLE,

    };

    static const RegisterID stackPointerRegister = ARMRegisters::sp;

    static const RegisterID linkRegister = ARMRegisters::lr;

    // Integer arithmetic operations:

    //

    // Operations are typically two operand - operation(source, srcDst)

    // For many operations the source may be an Imm32, the srcDst operand

    // may often be a memory location (explictly described using an Address

    // object).

    void add32(RegisterID src, RegisterID dest)

    {

        m_assembler.add(dest, dest, src);

    }

    void add32(Imm32 imm, RegisterID dest)

    {

        add32(imm, dest, dest);

    }

    void add32(Imm32 imm, RegisterID src, RegisterID dest)

    {

        ARMThumbImmediate armImm = ARMThumbImmediate::makeUInt12OrEncodedImm(imm.m_value);

        if (armImm.isValid())

            m_assembler.add(dest, src, armImm);

        else {

            move(imm, dataTempRegister);

            m_assembler.add(dest, src, dataTempRegister);

        }

    }

    void add32(Imm32 imm, Address address)

    {

        load32(address, dataTempRegister);

        ARMThumbImmediate armImm = ARMThumbImmediate::makeUInt12OrEncodedImm(imm.m_value);

        if (armImm.isValid())

            m_assembler.add(dataTempRegister, dataTempRegister, armImm);

        else {

            // Hrrrm, since dataTempRegister holds the data loaded,

            // use addressTempRegister to hold the immediate.

            move(imm, addressTempRegister);

            m_assembler.add(dataTempRegister, dataTempRegister, addressTempRegister);

        }

        store32(dataTempRegister, address);

    }

    void add32(Address src, RegisterID dest)

    {

        load32(src, dataTempRegister);

        add32(dataTempRegister, dest);

    }

    void add32(Imm32 imm, AbsoluteAddress address)

    {

        load32(address.m_ptr, dataTempRegister);

        ARMThumbImmediate armImm = ARMThumbImmediate::makeUInt12OrEncodedImm(imm.m_value);

        if (armImm.isValid())

            m_assembler.add(dataTempRegister, dataTempRegister, armImm);

        else {

            // Hrrrm, since dataTempRegister holds the data loaded,

            // use addressTempRegister to hold the immediate.

            move(imm, addressTempRegister);

            m_assembler.add(dataTempRegister, dataTempRegister, addressTempRegister);

        }

        store32(dataTempRegister, address.m_ptr);

    }

    void and32(RegisterID src, RegisterID dest)

    {

        m_assembler.ARM_and(dest, dest, src);

    }

    void and32(Imm32 imm, RegisterID dest)

    {

        ARMThumbImmediate armImm = ARMThumbImmediate::makeEncodedImm(imm.m_value);

        if (armImm.isValid())

            m_assembler.ARM_and(dest, dest, armImm);

        else {

            move(imm, dataTempRegister);

            m_assembler.ARM_and(dest, dest, dataTempRegister);

        }

    }

    void lshift32(RegisterID shift_amount, RegisterID dest)

    {

        // Clamp the shift to the range 0..31

        ARMThumbImmediate armImm = ARMThumbImmediate::makeEncodedImm(0x1f);

        ASSERT(armImm.isValid());

        m_assembler.ARM_and(dataTempRegister, shift_amount, armImm);

        m_assembler.lsl(dest, dest, dataTempRegister);

    }

    void lshift32(Imm32 imm, RegisterID dest)

    {

        m_assembler.lsl(dest, dest, imm.m_value & 0x1f);

    }

    void mul32(RegisterID src, RegisterID dest)

    {

        m_assembler.smull(dest, dataTempRegister, dest, src);

    }

    void mul32(Imm32 imm, RegisterID src, RegisterID dest)

    {

        move(imm, dataTempRegister);

        m_assembler.smull(dest, dataTempRegister, src, dataTempRegister);

    }

    void neg32(RegisterID srcDest)

    {

        m_assembler.neg(srcDest, srcDest);

    }

    void not32(RegisterID srcDest)

    {

        m_assembler.mvn(srcDest, srcDest);

    }

    void or32(RegisterID src, RegisterID dest)

    {

        m_assembler.orr(dest, dest, src);

    }

    void or32(Imm32 imm, RegisterID dest)

    {

        ARMThumbImmediate armImm = ARMThumbImmediate::makeEncodedImm(imm.m_value);

        if (armImm.isValid())

            m_assembler.orr(dest, dest, armImm);

        else {

            move(imm, dataTempRegister);

            m_assembler.orr(dest, dest, dataTempRegister);

        }

    }

    void rshift32(RegisterID shift_amount, RegisterID dest)

    {

        // Clamp the shift to the range 0..31

        ARMThumbImmediate armImm = ARMThumbImmediate::makeEncodedImm(0x1f);

        ASSERT(armImm.isValid());

        m_assembler.ARM_and(dataTempRegister, shift_amount, armImm);

        m_assembler.asr(dest, dest, dataTempRegister);

    }

    void rshift32(Imm32 imm, RegisterID dest)

    {

        m_assembler.asr(dest, dest, imm.m_value & 0x1f);

    }

    void urshift32(RegisterID shift_amount, RegisterID dest)

    {

        // Clamp the shift to the range 0..31

        ARMThumbImmediate armImm = ARMThumbImmediate::makeEncodedImm(0x1f);

        ASSERT(armImm.isValid());

        m_assembler.ARM_and(dataTempRegister, shift_amount, armImm);

        m_assembler.lsr(dest, dest, dataTempRegister);

    }

    void urshift32(Imm32 imm, RegisterID dest)

    {

        m_assembler.lsr(dest, dest, imm.m_value & 0x1f);

    }

    void sub32(RegisterID src, RegisterID dest)

    {

        m_assembler.sub(dest, dest, src);

    }

    void sub32(Imm32 imm, RegisterID dest)

    {

        ARMThumbImmediate armImm = ARMThumbImmediate::makeUInt12OrEncodedImm(imm.m_value);

        if (armImm.isValid())

            m_assembler.sub(dest, dest, armImm);

        else {

            move(imm, dataTempRegister);

            m_assembler.sub(dest, dest, dataTempRegister);

        }

    }

    void sub32(Imm32 imm, Address address)

    {

        load32(address, dataTempRegister);

        ARMThumbImmediate armImm = ARMThumbImmediate::makeUInt12OrEncodedImm(imm.m_value);

        if (armImm.isValid())

            m_assembler.sub(dataTempRegister, dataTempRegister, armImm);

        else {

            // Hrrrm, since dataTempRegister holds the data loaded,

            // use addressTempRegister to hold the immediate.

            move(imm, addressTempRegister);

            m_assembler.sub(dataTempRegister, dataTempRegister, addressTempRegister);

        }

        store32(dataTempRegister, address);

    }

    void sub32(Address src, RegisterID dest)

    {

        load32(src, dataTempRegister);

        sub32(dataTempRegister, dest);

    }

    void sub32(Imm32 imm, AbsoluteAddress address)

    {

        load32(address.m_ptr, dataTempRegister);

        ARMThumbImmediate armImm = ARMThumbImmediate::makeUInt12OrEncodedImm(imm.m_value);

        if (armImm.isValid())

            m_assembler.sub(dataTempRegister, dataTempRegister, armImm);

        else {

            // Hrrrm, since dataTempRegister holds the data loaded,

            // use addressTempRegister to hold the immediate.

            move(imm, addressTempRegister);

            m_assembler.sub(dataTempRegister, dataTempRegister, addressTempRegister);

        }

        store32(dataTempRegister, address.m_ptr);

    }

    void xor32(RegisterID src, RegisterID dest)

    {

        m_assembler.eor(dest, dest, src);

    }

    void xor32(Imm32 imm, RegisterID dest)

    {

        ARMThumbImmediate armImm = ARMThumbImmediate::makeEncodedImm(imm.m_value);

        if (armImm.isValid())

            m_assembler.eor(dest, dest, armImm);

        else {

            move(imm, dataTempRegister);

            m_assembler.eor(dest, dest, dataTempRegister);

        }

    }

    // Memory access operations:

    //

    // Loads are of the form load(address, destination) and stores of the form

    // store(source, address).  The source for a store may be an Imm32.  Address

    // operand objects to loads and store will be implicitly constructed if a

    // register is passed.

private:

    void load32(ArmAddress address, RegisterID dest)

    {

        if (address.type == ArmAddress::HasIndex)

            m_assembler.ldr(dest, address.base, address.u.index, address.u.scale);

        else if (address.u.offset >= 0) {

            ARMThumbImmediate armImm = ARMThumbImmediate::makeUInt12(address.u.offset);

            ASSERT(armImm.isValid());

            m_assembler.ldr(dest, address.base, armImm);

        } else {

            ASSERT(address.u.offset >= -255);

            m_assembler.ldr(dest, address.base, address.u.offset, true, false);

        }

    }

    void load16(ArmAddress address, RegisterID dest)

    {

        if (address.type == ArmAddress::HasIndex)

            m_assembler.ldrh(dest, address.base, address.u.index, address.u.scale);

        else if (address.u.offset >= 0) {

            ARMThumbImmediate armImm = ARMThumbImmediate::makeUInt12(address.u.offset);

            ASSERT(armImm.isValid());

            m_assembler.ldrh(dest, address.base, armImm);

        } else {

            ASSERT(address.u.offset >= -255);

            m_assembler.ldrh(dest, address.base, address.u.offset, true, false);

        }

    }

    void load8(ArmAddress address, RegisterID dest)

    {

        if (address.type == ArmAddress::HasIndex)

            m_assembler.ldrb(dest, address.base, address.u.index, address.u.scale);

        else if (address.u.offset >= 0) {

            ARMThumbImmediate armImm = ARMThumbImmediate::makeUInt12(address.u.offset);

            ASSERT(armImm.isValid());

            m_assembler.ldrb(dest, address.base, armImm);

        } else {

            ASSERT(address.u.offset >= -255);

            m_assembler.ldrb(dest, address.base, address.u.offset, true, false);

        }

    }

    void store32(RegisterID src, ArmAddress address)

    {

        if (address.type == ArmAddress::HasIndex)

            m_assembler.str(src, address.base, address.u.index, address.u.scale);

        else if (address.u.offset >= 0) {

            ARMThumbImmediate armImm = ARMThumbImmediate::makeUInt12(address.u.offset);

            ASSERT(armImm.isValid());

            m_assembler.str(src, address.base, armImm);

        } else {

            ASSERT(address.u.offset >= -255);

            m_assembler.str(src, address.base, address.u.offset, true, false);

        }

    }

public:

    void load32(ImplicitAddress address, RegisterID dest)

    {

        load32(setupArmAddress(address), dest);

    }

    void load32(BaseIndex address, RegisterID dest)

    {

        load32(setupArmAddress(address), dest);

    }

    void load32WithUnalignedHalfWords(BaseIndex address, RegisterID dest)

    {

        load32(setupArmAddress(address), dest);

    }

    void load32(void* address, RegisterID dest)

    {

        move(ImmPtr(address), addressTempRegister);

        m_assembler.ldr(dest, addressTempRegister, ARMThumbImmediate::makeUInt16(0));

    }

    void load8(ImplicitAddress address, RegisterID dest)

    {

        load8(setupArmAddress(address), dest);

    }

    DataLabel32 load32WithAddressOffsetPatch(Address address, RegisterID dest)

    {

        DataLabel32 label = moveWithPatch(Imm32(address.offset), dataTempRegister);

        load32(ArmAddress(address.base, dataTempRegister), dest);

        return label;

    }

    Label loadPtrWithPatchToLEA(Address address, RegisterID dest)

    {

        Label label(this);

        moveFixedWidthEncoding(Imm32(address.offset), dataTempRegister);

        load32(ArmAddress(address.base, dataTempRegister), dest);

        return label;

    }

    void load16(BaseIndex address, RegisterID dest)

    {

        m_assembler.ldrh(dest, makeBaseIndexBase(address), address.index, address.scale);

    }

    void load16(ImplicitAddress address, RegisterID dest)

    {

        ARMThumbImmediate armImm = ARMThumbImmediate::makeUInt12(address.offset);

        if (armImm.isValid())

            m_assembler.ldrh(dest, address.base, armImm);

        else {

            move(Imm32(address.offset), dataTempRegister);

            m_assembler.ldrh(dest, address.base, dataTempRegister);

        }

    }

    DataLabel32 store32WithAddressOffsetPatch(RegisterID src, Address address)

    {

        DataLabel32 label = moveWithPatch(Imm32(address.offset), dataTempRegister);

        store32(src, ArmAddress(address.base, dataTempRegister));

        return label;

    }

    void store32(RegisterID src, ImplicitAddress address)

    {

        store32(src, setupArmAddress(address));

    }

    void store32(RegisterID src, BaseIndex address)

    {

        store32(src, setupArmAddress(address));

    }

    void store32(Imm32 imm, ImplicitAddress address)

    {

        move(imm, dataTempRegister);

        store32(dataTempRegister, setupArmAddress(address));

    }

    void store32(RegisterID src, void* address)

    {

        move(ImmPtr(address), addressTempRegister);

        m_assembler.str(src, addressTempRegister, ARMThumbImmediate::makeUInt16(0));

    }

    void store32(Imm32 imm, void* address)

    {

        move(imm, dataTempRegister);

        store32(dataTempRegister, address);

    }

    // Floating-point operations:

    bool supportsFloatingPoint() const { return true; }

    // On x86(_64) the MacroAssembler provides an interface to truncate a double to an integer.

    // If a value is not representable as an integer, and possibly for some values that are,

    // (on x86 INT_MIN, since this is indistinguishable from results for out-of-range/NaN input)

    // a branch will  be taken.  It is not clear whether this interface will be well suited to

    // other platforms.  On ARMv7 the hardware truncation operation produces multiple possible

    // failure values (saturates to INT_MIN & INT_MAX, NaN reulsts in a value of 0).  This is a

    // temporary solution while we work out what this interface should be.  Either we need to

    // decide to make this interface work on all platforms, rework the interface to make it more

    // generic, or decide that the MacroAssembler cannot practically be used to abstracted these

    // operations, and make clients go directly to the m_assembler to plant truncation instructions.