/*

 * Copyright (C) 2008 Apple Inc. All rights reserved.

 *

 * Redistribution and use in source and binary forms, with or without

 * modification, are permitted provided that the following conditions

 * are met:

 * 1. Redistributions of source code must retain the above copyright

 *    notice, this list of conditions and the following disclaimer.

 * 2. Redistributions in binary form must reproduce the above copyright

 *    notice, this list of conditions and the following disclaimer in the

 *    documentation and/or other materials provided with the distribution.

 *

 * THIS SOFTWARE IS PROVIDED BY APPLE INC. ``AS IS'' AND ANY

 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR

 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL APPLE INC. OR

 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,

 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,

 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR

 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY

 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT

 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE

 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 

 */

#ifndef MacroAssemblerX86Common_h

#define MacroAssemblerX86Common_h

#if ENABLE(ASSEMBLER)

#include "X86Assembler.h"

#include "AbstractMacroAssembler.h"

namespace JSC {

class MacroAssemblerX86Common : public AbstractMacroAssembler<X86Assembler> {

    static const int DoubleConditionBitInvert = 0x10;

    static const int DoubleConditionBitSpecial = 0x20;

    static const int DoubleConditionBits = DoubleConditionBitInvert | DoubleConditionBitSpecial;

public:

    typedef X86Assembler::FPRegisterID FPRegisterID;

    enum Condition {

        Equal = X86Assembler::ConditionE,

        NotEqual = X86Assembler::ConditionNE,

        Above = X86Assembler::ConditionA,

        AboveOrEqual = X86Assembler::ConditionAE,

        Below = X86Assembler::ConditionB,

        BelowOrEqual = X86Assembler::ConditionBE,

        GreaterThan = X86Assembler::ConditionG,

        GreaterThanOrEqual = X86Assembler::ConditionGE,

        LessThan = X86Assembler::ConditionL,

        LessThanOrEqual = X86Assembler::ConditionLE,

        Overflow = X86Assembler::ConditionO,

        Signed = X86Assembler::ConditionS,

        Zero = X86Assembler::ConditionE,

        NonZero = X86Assembler::ConditionNE

    };

    enum DoubleCondition {

        // These conditions will only evaluate to true if the comparison is ordered - i.e. neither operand is NaN.

        DoubleEqual = X86Assembler::ConditionE | DoubleConditionBitSpecial,

        DoubleNotEqual = X86Assembler::ConditionNE,

        DoubleGreaterThan = X86Assembler::ConditionA,

        DoubleGreaterThanOrEqual = X86Assembler::ConditionAE,

        DoubleLessThan = X86Assembler::ConditionA | DoubleConditionBitInvert,

        DoubleLessThanOrEqual = X86Assembler::ConditionAE | DoubleConditionBitInvert,

        // If either operand is NaN, these conditions always evaluate to true.

        DoubleEqualOrUnordered = X86Assembler::ConditionE,

        DoubleNotEqualOrUnordered = X86Assembler::ConditionNE | DoubleConditionBitSpecial,

        DoubleGreaterThanOrUnordered = X86Assembler::ConditionB | DoubleConditionBitInvert,

        DoubleGreaterThanOrEqualOrUnordered = X86Assembler::ConditionBE | DoubleConditionBitInvert,

        DoubleLessThanOrUnordered = X86Assembler::ConditionB,

        DoubleLessThanOrEqualOrUnordered = X86Assembler::ConditionBE,

    };

    COMPILE_ASSERT(

        !((X86Assembler::ConditionE | X86Assembler::ConditionNE | X86Assembler::ConditionA | X86Assembler::ConditionAE | X86Assembler::ConditionB | X86Assembler::ConditionBE) & DoubleConditionBits),

        DoubleConditionBits_should_not_interfere_with_X86Assembler_Condition_codes);

    static const RegisterID stackPointerRegister = X86Registers::esp;

    // Integer arithmetic operations:

    //

    // Operations are typically two operand - operation(source, srcDst)

    // For many operations the source may be an Imm32, the srcDst operand

    // may often be a memory location (explictly described using an Address

    // object).

    void add32(RegisterID src, RegisterID dest)

    {

        m_assembler.addl_rr(src, dest);

    }

    void add32(Imm32 imm, Address address)

    {

        m_assembler.addl_im(imm.m_value, address.offset, address.base);

    }

    void add32(Imm32 imm, RegisterID dest)

    {

        m_assembler.addl_ir(imm.m_value, dest);

    }

    void add32(Address src, RegisterID dest)

    {

        m_assembler.addl_mr(src.offset, src.base, dest);

    }

    void add32(RegisterID src, Address dest)

    {

        m_assembler.addl_rm(src, dest.offset, dest.base);

    }

    void and32(RegisterID src, RegisterID dest)

    {

        m_assembler.andl_rr(src, dest);

    }

    void and32(Imm32 imm, RegisterID dest)

    {

        m_assembler.andl_ir(imm.m_value, dest);

    }

    void and32(RegisterID src, Address dest)

    {

        m_assembler.andl_rm(src, dest.offset, dest.base);

    }

    void and32(Address src, RegisterID dest)

    {

        m_assembler.andl_mr(src.offset, src.base, dest);

    }

    void and32(Imm32 imm, Address address)

    {

        m_assembler.andl_im(imm.m_value, address.offset, address.base);

    }

    void lshift32(Imm32 imm, RegisterID dest)

    {

        m_assembler.shll_i8r(imm.m_value, dest);

    }

    void lshift32(RegisterID shift_amount, RegisterID dest)

    {

        // On x86 we can only shift by ecx; if asked to shift by another register we'll

        // need rejig the shift amount into ecx first, and restore the registers afterwards.

        if (shift_amount != X86Registers::ecx) {

            swap(shift_amount, X86Registers::ecx);

            // E.g. transform "shll %eax, %eax" -> "xchgl %eax, %ecx; shll %ecx, %ecx; xchgl %eax, %ecx"

            if (dest == shift_amount)

                m_assembler.shll_CLr(X86Registers::ecx);

            // E.g. transform "shll %eax, %ecx" -> "xchgl %eax, %ecx; shll %ecx, %eax; xchgl %eax, %ecx"

            else if (dest == X86Registers::ecx)

                m_assembler.shll_CLr(shift_amount);

            // E.g. transform "shll %eax, %ebx" -> "xchgl %eax, %ecx; shll %ecx, %ebx; xchgl %eax, %ecx"

            else

                m_assembler.shll_CLr(dest);

            swap(shift_amount, X86Registers::ecx);

        } else

            m_assembler.shll_CLr(dest);

    }

    void mul32(RegisterID src, RegisterID dest)

    {

        m_assembler.imull_rr(src, dest);

    }

    void mul32(Address src, RegisterID dest)

    {

        m_assembler.imull_mr(src.offset, src.base, dest);

    }

    void mul32(Imm32 imm, RegisterID src, RegisterID dest)

    {

        m_assembler.imull_i32r(src, imm.m_value, dest);

    }

    void neg32(RegisterID srcDest)

    {

        m_assembler.negl_r(srcDest);

    }

    void neg32(Address srcDest)

    {

        m_assembler.negl_m(srcDest.offset, srcDest.base);

    }

    void not32(RegisterID srcDest)

    {

        m_assembler.notl_r(srcDest);

    }

    void not32(Address srcDest)

    {

        m_assembler.notl_m(srcDest.offset, srcDest.base);

    }

    void or32(RegisterID src, RegisterID dest)

    {

        m_assembler.orl_rr(src, dest);

    }

    void or32(Imm32 imm, RegisterID dest)

    {

        m_assembler.orl_ir(imm.m_value, dest);

    }

    void or32(RegisterID src, Address dest)

    {

        m_assembler.orl_rm(src, dest.offset, dest.base);

    }

    void or32(Address src, RegisterID dest)

    {

        m_assembler.orl_mr(src.offset, src.base, dest);

    }

    void or32(Imm32 imm, Address address)

    {

        m_assembler.orl_im(imm.m_value, address.offset, address.base);

    }

    void rshift32(RegisterID shift_amount, RegisterID dest)

    {

        // On x86 we can only shift by ecx; if asked to shift by another register we'll

        // need rejig the shift amount into ecx first, and restore the registers afterwards.

        if (shift_amount != X86Registers::ecx) {

            swap(shift_amount, X86Registers::ecx);

            // E.g. transform "shll %eax, %eax" -> "xchgl %eax, %ecx; shll %ecx, %ecx; xchgl %eax, %ecx"

            if (dest == shift_amount)

                m_assembler.sarl_CLr(X86Registers::ecx);

            // E.g. transform "shll %eax, %ecx" -> "xchgl %eax, %ecx; shll %ecx, %eax; xchgl %eax, %ecx"

            else if (dest == X86Registers::ecx)

                m_assembler.sarl_CLr(shift_amount);

            // E.g. transform "shll %eax, %ebx" -> "xchgl %eax, %ecx; shll %ecx, %ebx; xchgl %eax, %ecx"

            else

                m_assembler.sarl_CLr(dest);

            swap(shift_amount, X86Registers::ecx);

        } else

            m_assembler.sarl_CLr(dest);

    }

    void rshift32(Imm32 imm, RegisterID dest)

    {

        m_assembler.sarl_i8r(imm.m_value, dest);

    }

    void urshift32(RegisterID shift_amount, RegisterID dest)

    {

        // On x86 we can only shift by ecx; if asked to shift by another register we'll

        // need rejig the shift amount into ecx first, and restore the registers afterwards.

        if (shift_amount != X86Registers::ecx) {

            swap(shift_amount, X86Registers::ecx);

            // E.g. transform "shrl %eax, %eax" -> "xchgl %eax, %ecx; shrl %ecx, %ecx; xchgl %eax, %ecx"

            if (dest == shift_amount)

                m_assembler.shrl_CLr(X86Registers::ecx);

            // E.g. transform "shrl %eax, %ecx" -> "xchgl %eax, %ecx; shrl %ecx, %eax; xchgl %eax, %ecx"

            else if (dest == X86Registers::ecx)

                m_assembler.shrl_CLr(shift_amount);

            // E.g. transform "shrl %eax, %ebx" -> "xchgl %eax, %ecx; shrl %ecx, %ebx; xchgl %eax, %ecx"

            else

                m_assembler.shrl_CLr(dest);

            swap(shift_amount, X86Registers::ecx);

        } else

            m_assembler.shrl_CLr(dest);

    }

    void urshift32(Imm32 imm, RegisterID dest)

    {

        m_assembler.shrl_i8r(imm.m_value, dest);

    }

    void sub32(RegisterID src, RegisterID dest)

    {

        m_assembler.subl_rr(src, dest);

    }

    void sub32(Imm32 imm, RegisterID dest)

    {

        m_assembler.subl_ir(imm.m_value, dest);

    }

    void sub32(Imm32 imm, Address address)

    {

        m_assembler.subl_im(imm.m_value, address.offset, address.base);

    }

    void sub32(Address src, RegisterID dest)

    {

        m_assembler.subl_mr(src.offset, src.base, dest);

    }

    void sub32(RegisterID src, Address dest)

    {

        m_assembler.subl_rm(src, dest.offset, dest.base);

    }

    void xor32(RegisterID src, RegisterID dest)

    {

        m_assembler.xorl_rr(src, dest);

    }

    void xor32(Imm32 imm, Address dest)

    {

        m_assembler.xorl_im(imm.m_value, dest.offset, dest.base);

    }

    void xor32(Imm32 imm, RegisterID dest)

    {

        m_assembler.xorl_ir(imm.m_value, dest);

    }

    void xor32(RegisterID src, Address dest)

    {

        m_assembler.xorl_rm(src, dest.offset, dest.base);

    }

    void xor32(Address src, RegisterID dest)

    {

        m_assembler.xorl_mr(src.offset, src.base, dest);

    }

    void sqrtDouble(FPRegisterID src, FPRegisterID dst)

    {

        m_assembler.sqrtsd_rr(src, dst);

    }

    // Memory access operations:

    //

    // Loads are of the form load(address, destination) and stores of the form

    // store(source, address).  The source for a store may be an Imm32.  Address

    // operand objects to loads and store will be implicitly constructed if a

    // register is passed.

    void load32(ImplicitAddress address, RegisterID dest)

    {

        m_assembler.movl_mr(address.offset, address.base, dest);

    }

    void load32(BaseIndex address, RegisterID dest)

    {

        m_assembler.movl_mr(address.offset, address.base, address.index, address.scale, dest);

    }

    void load32WithUnalignedHalfWords(BaseIndex address, RegisterID dest)

    {

        load32(address, dest);

    }

    DataLabel32 load32WithAddressOffsetPatch(Address address, RegisterID dest)

    {

        m_assembler.movl_mr_disp32(address.offset, address.base, dest);

        return DataLabel32(this);

    }

    void load16(BaseIndex address, RegisterID dest)

    {

        m_assembler.movzwl_mr(address.offset, address.base, address.index, address.scale, dest);

    }

    void load16(Address address, RegisterID dest)

    {

        m_assembler.movzwl_mr(address.offset, address.base, dest);

    }

    DataLabel32 store32WithAddressOffsetPatch(RegisterID src, Address address)

    {

        m_assembler.movl_rm_disp32(src, address.offset, address.base);

        return DataLabel32(this);

    }

    void store32(RegisterID src, ImplicitAddress address)

    {

        m_assembler.movl_rm(src, address.offset, address.base);

    }

    void store32(RegisterID src, BaseIndex address)

    {

        m_assembler.movl_rm(src, address.offset, address.base, address.index, address.scale);

    }

    void store32(Imm32 imm, ImplicitAddress address)

    {

        m_assembler.movl_i32m(imm.m_value, address.offset, address.base);

    }

    // Floating-point operation:

    //

    // Presently only supports SSE, not x87 floating point.

    void loadDouble(ImplicitAddress address, FPRegisterID dest)

    {

        ASSERT(isSSE2Present());

        m_assembler.movsd_mr(address.offset, address.base, dest);

    }

    void storeDouble(FPRegisterID src, ImplicitAddress address)

    {

        ASSERT(isSSE2Present());

        m_assembler.movsd_rm(src, address.offset, address.base);

    }

    void addDouble(FPRegisterID src, FPRegisterID dest)

    {

        ASSERT(isSSE2Present());

        m_assembler.addsd_rr(src, dest);

    }

    void addDouble(Address src, FPRegisterID dest)

    {

        ASSERT(isSSE2Present());

        m_assembler.addsd_mr(src.offset, src.base, dest);

    }

    void divDouble(FPRegisterID src, FPRegisterID dest)

    {

        ASSERT(isSSE2Present());

        m_assembler.divsd_rr(src, dest);

    }

    void divDouble(Address src, FPRegisterID dest)

    {

        ASSERT(isSSE2Present());

        m_assembler.divsd_mr(src.offset, src.base, dest);

    }

    void subDouble(FPRegisterID src, FPRegisterID dest)

    {

        ASSERT(isSSE2Present());

        m_assembler.subsd_rr(src, dest);

    }

    void subDouble(Address src, FPRegisterID dest)

    {

        ASSERT(isSSE2Present());

        m_assembler.subsd_mr(src.offset, src.base, dest);

    }

    void mulDouble(FPRegisterID src, FPRegisterID dest)

    {

        ASSERT(isSSE2Present());

        m_assembler.mulsd_rr(src, dest);

    }

    void mulDouble(Address src, FPRegisterID dest)

    {

        ASSERT(isSSE2Present());

        m_assembler.mulsd_mr(src.offset, src.base, dest);

    }

    void convertInt32ToDouble(RegisterID src, FPRegisterID dest)

    {

        ASSERT(isSSE2Present());

        m_assembler.cvtsi2sd_rr(src, dest);

    }

    void convertInt32ToDouble(Address src, FPRegisterID dest)

    {

        ASSERT(isSSE2Present());

        m_assembler.cvtsi2sd_mr(src.offset, src.base, dest);

    }

    Jump branchDouble(DoubleCondition cond, FPRegisterID left, FPRegisterID right)

    {

        ASSERT(isSSE2Present());

        if (cond & DoubleConditionBitInvert)

            m_assembler.ucomisd_rr(left, right);

        else

            m_assembler.ucomisd_rr(right, left);

        if (cond == DoubleEqual) {

            Jump isUnordered(m_assembler.jp());

            Jump result = Jump(m_assembler.je());

            isUnordered.link(this);

            return result;

        } else if (cond == DoubleNotEqualOrUnordered) {

            Jump isUnordered(m_assembler.jp());

            Jump isEqual(m_assembler.je());

            isUnordered.link(this);

            Jump result = jump();

            isEqual.link(this);

            return result;

        }

        ASSERT(!(cond & DoubleConditionBitSpecial));

        return Jump(m_assembler.jCC(static_cast<X86Assembler::Condition>(cond & ~DoubleConditionBits)));

    }

    // Truncates 'src' to an integer, and places the resulting 'dest'.

    // If the result is not representable as a 32 bit value, branch.

    // May also branch for some values that are representable in 32 bits

    // (specifically, in this case, INT_MIN).

    Jump branchTruncateDoubleToInt32(FPRegisterID src, RegisterID dest)

    {

        ASSERT(isSSE2Present());

        m_assembler.cvttsd2si_rr(src, dest);

        return branch32(Equal, dest, Imm32(0x80000000));

    }

    // Convert 'src' to an integer, and places the resulting 'dest'.

    // If the result is not representable as a 32 bit value, branch.

    // May also branch for some values that are representable in 32 bits

    // (specifically, in this case, 0).

    void branchConvertDoubleToInt32(FPRegisterID src, RegisterID dest, JumpList& failureCases, FPRegisterID fpTemp)

    {

        ASSERT(isSSE2Present());

        m_assembler.cvttsd2si_rr(src, dest);

        // If the result is zero, it might have been -0.0, and the double comparison won't catch this!

        failureCases.append(branchTest32(Zero, dest));

        // Convert the integer result back to float & compare to the original value - if not equal or unordered (NaN) then jump.

        convertInt32ToDouble(dest, fpTemp);

        m_assembler.ucomisd_rr(fpTemp, src);

        failureCases.append(m_assembler.jp());

        failureCases.append(m_assembler.jne());

    }