|
1 // TrkNextInstructionAfterPC.cpp |
|
2 // |
|
3 // Copyright (c) 2010 Accenture. All rights reserved. |
|
4 // This component and the accompanying materials are made available |
|
5 // under the terms of the "Eclipse Public License v1.0" |
|
6 // which accompanies this distribution, and is available |
|
7 // at the URL "http://www.eclipse.org/legal/epl-v10.html". |
|
8 // |
|
9 // Initial Contributors: |
|
10 // Accenture - Initial contribution |
|
11 // |
|
12 #include "fdebuggerkernel.h" |
|
13 |
|
14 //BEGIN TOMSCI |
|
15 #include <kernel/arm/arm.h> |
|
16 |
|
17 #define LOG_MSG(x) |
|
18 #define LOG_MSG2(x,y) |
|
19 #define LOG_MSG3(x,y,z) |
|
20 #define iChannel this // Saves rewriting a whole load |
|
21 #define ReturnIfError(x) { TInt y = (x); if (KErrNone != y) return y; } |
|
22 |
|
23 #ifdef ASSERT |
|
24 #undef ASSERT |
|
25 #endif |
|
26 #ifdef __WINS__ |
|
27 #define ASSERT(x) __ASSERT_ALWAYS((x), Kern::Fault("TRKNIAPC Assertion failed: " #x, __LINE__)) |
|
28 #else |
|
29 #define ASSERT(x) if (!(x)) { Kern::Printf("TRKNIAPC Assertion failed @ %d: " #x, __LINE__); NKern::Sleep(NKern::TimerTicks(5000)); } |
|
30 #endif |
|
31 |
|
32 TInt DDebuggerEventHandler::ReadKernelRegisterValue(DThread* aThread, TInt aRegister, TUint32& aResult) |
|
33 { |
|
34 TUint32 regs[32]; |
|
35 TUint32 valid = 0; |
|
36 NKern::ThreadGetUserContext(&aThread->iNThread, ®s[0], valid); |
|
37 if (valid & (1<<aRegister)) |
|
38 { |
|
39 aResult = regs[aRegister]; |
|
40 return KErrNone; |
|
41 } |
|
42 else |
|
43 { |
|
44 return KErrNotSupported; |
|
45 } |
|
46 } |
|
47 |
|
48 TInt DDebuggerEventHandler::DoReadMemory(DThread* aThread, TLinAddr aAddress, TInt aLength, TDes8& aResult) |
|
49 { |
|
50 // First check if this address is something we've overwritten with a software breakpoint - if so, return the stored value instead |
|
51 ASSERT(aLength == 4 || aLength == 2); |
|
52 if (aResult.MaxLength() < aLength) return KErrArgument; |
|
53 |
|
54 // Check for a breakpoint covering this region |
|
55 SBreakpoint* b = FindBreakpointByAddress(aAddress & ~1); |
|
56 if (b && b->iOrigInstruction.Length() > 0) |
|
57 { |
|
58 ASSERT(b->iOrigInstruction.Length() == aLength); // Otherwise we've trying to read an ARM instruction from somewhere we have a thumb breakpoint (or vice versa) |
|
59 aResult.Copy(b->iOrigInstruction); |
|
60 return KErrNone; |
|
61 } |
|
62 |
|
63 TInt err = Kern::ThreadRawRead(aThread, (void*)aAddress, (void*)aResult.Ptr(), aLength); |
|
64 if (err == KErrNone) aResult.SetLength(aLength); |
|
65 return err; |
|
66 } |
|
67 |
|
68 namespace Debug { |
|
69 enum TArchitectureMode |
|
70 { |
|
71 /** Represents the ARM CPU architecture. */ |
|
72 EArmMode = 1, |
|
73 /** Represents the Thumb CPU architecture. */ |
|
74 EThumbMode = 2, |
|
75 /** |
|
76 Represents the Thumb2 CPU architecture. |
|
77 @prototype |
|
78 */ |
|
79 EThumb2EEMode = 3 |
|
80 }; |
|
81 } |
|
82 using namespace Debug; |
|
83 typedef TUint32 T4ByteRegisterValue; |
|
84 |
|
85 //END TOMSCI |
|
86 |
|
87 |
|
88 // Register definitions |
|
89 #define SP_REGISTER 13 |
|
90 #define LINK_REGISTER 14 |
|
91 #define PC_REGISTER 15 |
|
92 #define STATUS_REGISTER 16 |
|
93 |
|
94 /* |
|
95 // ARM instruction bitmasks |
|
96 #define ARM_OPCODE(x) (((TUint32)(x) & 0x0E000000) >> 25) |
|
97 |
|
98 // Generic instruction defines |
|
99 #define ARM_RM(x) ((TUint32)(x) & 0x0000000F) // bit 0- 4 |
|
100 #define ARM_RS(x) (((TUint32)(x) & 0x00000F00) >> 8) // bit 8-11 |
|
101 #define ARM_RD(x) (((TUint32)(x) & 0x0000F000) >> 12) // bit 12-15 |
|
102 #define ARM_RN(x) (((TUint32)(x) & 0x000F0000) >> 16) // bit 16-19 |
|
103 #define ARM_LOAD(x) (((TUint32)(x) & 0x00100000) >> 20) // bit 20 |
|
104 |
|
105 // Data processing instruction defines |
|
106 #define ARM_DATA_SHIFT(x) (((TUint32)(x) & 0x00000060) >> 5) // bit 5- 6 |
|
107 #define ARM_DATA_C(x) (((TUint32)(x) & 0x00000F80) >> 7) // bit 7-11 |
|
108 #define ARM_DATA_IMM(x) ((TUint32)(x) & 0x000000FF) // bit 0-7 |
|
109 #define ARM_DATA_ROT(x) (((TUint32)(x) & 0x00000F00) >> 8) // bit 8-11 |
|
110 |
|
111 // Single date transfer instruction defines |
|
112 #define ARM_SINGLE_IMM(x) ((TUint32)(x) & 0x00000FFF) // bit 0-11 |
|
113 #define ARM_SINGLE_BYTE(x) (((TUint32)(x) & 0x00400000) >> 22) // bit 22 |
|
114 #define ARM_SINGLE_U(x) (((TUint32)(x) & 0x00800000) >> 23) // bit 23 |
|
115 #define ARM_SINGLE_PRE(x) (((TUint32)(x) & 0x01000000) >> 24) // bit 24 |
|
116 |
|
117 // Block data transfer instruction defines |
|
118 #define ARM_BLOCK_REGLIST(x) ((TUint32)(x) & 0x0000FFFF) // bit 0-15 |
|
119 #define ARM_BLOCK_U(x) (((TUint32)(x) & 0x00800000) >> 23) // bit 23 |
|
120 #define ARM_BLOCK_PRE(x) (((TUint32)(x) & 0x01000000) >> 24) // bit 24 |
|
121 |
|
122 // Branch instruction defines |
|
123 #define ARM_B_ADDR(x) ((x & 0x00800000) ? ((TUint32)(x) & 0x00FFFFFF | 0xFF000000) : (TUint32)(x) & 0x00FFFFFF) |
|
124 #define ARM_INSTR_B_DEST(x,a) (ARM_B_ADDR(x) << 2) + ((TUint32)(a) + 8) |
|
125 |
|
126 #define ARM_CARRY_BIT 0x20000000 // bit 30 |
|
127 |
|
128 |
|
129 // Thumb instruction bitmasks |
|
130 #define THUMB_OPCODE(x) (((TUint16)(x) & 0xF800) >> 11) |
|
131 #define THUMB_INST_7_15(x) (((TUint16)(x) & 0xFF80) >> 7) |
|
132 #define THUMB_INST_8_15(x) (((TUint16)(x) & 0xFF00) >> 8) |
|
133 */ |
|
134 |
|
135 TUint32 IsBitSet(const TUint32 aBitset, const TUint8 aNum) |
|
136 { |
|
137 return (aBitset & (1 << aNum) ); |
|
138 } |
|
139 |
|
140 // |
|
141 // BitCount |
|
142 // |
|
143 // Count number of bits in aVal |
|
144 TUint32 BitCount(const TUint32 aVal) |
|
145 { |
|
146 TUint32 num = 0; |
|
147 |
|
148 for(TInt i = 0; i < 32; i++) |
|
149 { |
|
150 if ((1 << i) & aVal) |
|
151 { |
|
152 num++; |
|
153 } |
|
154 } |
|
155 return num; |
|
156 } |
|
157 |
|
158 // |
|
159 // Thumb2 opcode decoding |
|
160 // |
|
161 // Special data instructions and branch and exchange. |
|
162 // |
|
163 // Returns Opcode as defined in ARM ARM DDI0406A, section A6.2.3 |
|
164 TUint16 t2opcode16special(const TUint16 aInst) |
|
165 { |
|
166 TUint8 aVal = (aInst & 0x03C0) >> 5; |
|
167 |
|
168 return aVal; |
|
169 } |
|
170 |
|
171 |
|
172 // Thumb2 opcode decoding instructions |
|
173 // |
|
174 // Returns Opcode as defined in ARM ARM DDI0406A, section A6.2 |
|
175 // 16-bit Thumb instruction encoding |
|
176 TUint16 t2opcode16(const TUint16 aInst) |
|
177 { |
|
178 TUint16 aVal = (aInst & 0xFC00) >> 9; |
|
179 |
|
180 return aVal; |
|
181 } |
|
182 |
|
183 // ARM opcode decoding functions |
|
184 TUint32 arm_opcode(const TUint32 aInst) |
|
185 { |
|
186 // #define ARM_OPCODE(x) (((TUint32)(x) & 0x0E000000) >> 25) |
|
187 |
|
188 TUint32 aVal = ((aInst) & 0x0E000000) >> 25; |
|
189 |
|
190 return aVal; |
|
191 } |
|
192 |
|
193 TUint32 arm_rm(const TUint32 aInst) |
|
194 { |
|
195 //#define ARM_RM(x) ((TUint32)(x) & 0x0000000F) // bit 0- 4 |
|
196 |
|
197 TUint32 aVal = (aInst) & 0x0000000F; |
|
198 |
|
199 return aVal; |
|
200 } |
|
201 |
|
202 TUint32 arm_rs(const TUint32 aInst) |
|
203 { |
|
204 //#define ARM_RS(x) (((TUint32)(x) & 0x00000F00) >> 8) // bit 8-11 |
|
205 |
|
206 TUint32 aVal = ((aInst) & 0x00000F00) >> 8; |
|
207 |
|
208 return aVal; |
|
209 } |
|
210 |
|
211 TUint32 arm_rd(const TUint32 aInst) |
|
212 { |
|
213 //#define ARM_RD(x) (((TUint32)(x) & 0x0000F000) >> 12) // bit 12-15 |
|
214 |
|
215 TUint32 aVal = ((aInst) & 0x0000F000) >> 12; |
|
216 |
|
217 return aVal; |
|
218 } |
|
219 |
|
220 TUint32 arm_rn(const TUint32 aInst) |
|
221 { |
|
222 //#define ARM_RN(x) (((TUint32)(x) & 0x000F0000) >> 16) // bit 16-19 |
|
223 |
|
224 TUint32 aVal = ((aInst) & 0x000F0000) >> 16; |
|
225 |
|
226 return aVal; |
|
227 } |
|
228 |
|
229 TUint32 arm_load(const TUint32 aInst) |
|
230 { |
|
231 //#define ARM_LOAD(x) (((TUint32)(x) & 0x00100000) >> 20) // bit 20 |
|
232 |
|
233 TUint32 aVal = ((aInst) & 0x00100000) >> 20; |
|
234 |
|
235 return aVal; |
|
236 } |
|
237 |
|
238 // Data processing instruction defines |
|
239 TUint32 arm_data_shift(const TUint32 aInst) |
|
240 { |
|
241 //#define ARM_DATA_SHIFT(x) (((TUint32)(x) & 0x00000060) >> 5) // bit 5- 6 |
|
242 |
|
243 TUint32 aVal = ((aInst) & 0x00000060) >> 5; |
|
244 |
|
245 return aVal; |
|
246 } |
|
247 |
|
248 TUint32 arm_data_c(const TUint32 aInst) |
|
249 { |
|
250 //#define ARM_DATA_C(x) (((TUint32)(x) & 0x00000F80) >> 7) // bit 7-11 |
|
251 |
|
252 TUint32 aVal = ((aInst) & 0x00000F80) >> 7; |
|
253 |
|
254 return aVal; |
|
255 } |
|
256 |
|
257 TUint32 arm_data_imm(const TUint32 aInst) |
|
258 { |
|
259 //#define ARM_DATA_IMM(x) ((TUint32)(x) & 0x000000FF) // bit 0-7 |
|
260 |
|
261 TUint32 aVal = (aInst) & 0x000000FF; |
|
262 |
|
263 return aVal; |
|
264 } |
|
265 |
|
266 TUint32 arm_data_rot(const TUint32 aInst) |
|
267 { |
|
268 //#define ARM_DATA_ROT(x) (((TUint32)(x) & 0x00000F00) >> 8) // bit 8-11 |
|
269 |
|
270 TUint32 aVal = ((aInst) & 0x00000F00) >> 8; |
|
271 |
|
272 return aVal; |
|
273 } |
|
274 |
|
275 // Single date transfer instruction defines |
|
276 TUint32 arm_single_imm(const TUint32 aInst) |
|
277 { |
|
278 //#define ARM_SINGLE_IMM(x) ((TUint32)(x) & 0x00000FFF) // bit 0-11 |
|
279 |
|
280 TUint32 aVal = (aInst) & 0x00000FFF; |
|
281 |
|
282 return aVal; |
|
283 } |
|
284 |
|
285 TUint32 arm_single_byte(const TUint32 aInst) |
|
286 { |
|
287 //#define ARM_SINGLE_BYTE(x) (((TUint32)(x) & 0x00400000) >> 22) // bit 22 |
|
288 |
|
289 TUint32 aVal = ((aInst) & 0x00400000) >> 22; |
|
290 |
|
291 return aVal; |
|
292 } |
|
293 |
|
294 TUint32 arm_single_u(const TUint32 aInst) |
|
295 { |
|
296 //#define ARM_SINGLE_U(x) (((TUint32)(x) & 0x00800000) >> 23) // bit 23 |
|
297 |
|
298 TUint32 aVal = ((aInst) & 0x00800000) >> 23; |
|
299 |
|
300 return aVal; |
|
301 } |
|
302 |
|
303 TUint32 arm_single_pre(const TUint32 aInst) |
|
304 { |
|
305 //#define ARM_SINGLE_PRE(x) (((TUint32)(x) & 0x01000000) >> 24) // bit 24 |
|
306 |
|
307 TUint32 aVal = ((aInst) & 0x01000000) >> 24; |
|
308 |
|
309 return aVal; |
|
310 } |
|
311 |
|
312 // Block data transfer instruction defines |
|
313 TUint32 arm_block_reglist(const TUint32 aInst) |
|
314 { |
|
315 //#define ARM_BLOCK_REGLIST(x) ((TUint32)(x) & 0x0000FFFF) // bit 0-15 |
|
316 |
|
317 TUint32 aVal = (aInst) & 0x0000FFFF; |
|
318 |
|
319 return aVal; |
|
320 } |
|
321 |
|
322 TUint32 arm_block_u(const TUint32 aInst) |
|
323 { |
|
324 //#define ARM_BLOCK_U(x) (((TUint32)(x) & 0x00800000) >> 23) // bit 23 |
|
325 |
|
326 TUint32 aVal = ((aInst) & 0x00800000) >> 23; |
|
327 |
|
328 return aVal; |
|
329 } |
|
330 |
|
331 TUint32 arm_block_pre(const TUint32 aInst) |
|
332 { |
|
333 //#define ARM_BLOCK_PRE(x) (((TUint32)(x) & 0x01000000) >> 24) // bit 24 |
|
334 |
|
335 TUint32 aVal = ((aInst) & 0x01000000) >> 24; |
|
336 |
|
337 return aVal; |
|
338 } |
|
339 |
|
340 // Branch instruction defines |
|
341 TUint32 arm_b_addr(const TUint32 aInst) |
|
342 { |
|
343 //#define ARM_B_ADDR(x) ((x & 0x00800000) ? ((TUint32)(x) & 0x00FFFFFF | 0xFF000000) : (TUint32)(x) & 0x00FFFFFF) |
|
344 |
|
345 TUint32 aVal = ((aInst & 0x00800000) ? ((TUint32)(aInst) & 0x00FFFFFF | 0xFF000000) : (TUint32)(aInst) & 0x00FFFFFF); |
|
346 |
|
347 return aVal; |
|
348 } |
|
349 |
|
350 TUint32 arm_instr_b_dest(const TUint32 aInst, TUint32& aAddress) |
|
351 { |
|
352 //#define ARM_INSTR_B_DEST(x,a) (ARM_B_ADDR(x) << 2) + ((TUint32)(a) + 8) |
|
353 |
|
354 TUint32 aVal = (arm_b_addr(aInst) << 2) + ((TUint32)(aAddress) + 8); |
|
355 |
|
356 return aVal; |
|
357 } |
|
358 |
|
359 TUint32 thumb_b_addr(const TUint32 aInst) |
|
360 { |
|
361 //#define THUMB_B_ADDR(x) ((x & 0x0400) ? ((((TUint32)(x) & 0x07FF)<<11) | (((TUint32)(x) & 0x07FF0000)>>16) | 0xFFC00000) :\ |
|
362 ((TUint32)(x) & 0x07FF)<<11) | (((TUint32)(x) & 0x07FF0000)>>16) |
|
363 |
|
364 TUint32 aVal = ((((TUint32)(aInst) & 0x07FF)<<11) | ((TUint32)(aInst) & 0x07FF0000)>>16); |
|
365 |
|
366 return ((aInst & 0x0400) ? (aVal | 0xFFC00000) : aVal); |
|
367 } |
|
368 |
|
369 TUint32 thumb_instr_b_dest(const TUint32 aInst, TUint32& aAddress) |
|
370 { |
|
371 //#define THUMB_INSTR_B_DEST(x,a) (THUMB_B_ADDR(x) << 1) + ((TUint32)(a) + 4) |
|
372 |
|
373 TUint32 aVal = (thumb_b_addr(aInst) << 1) + ((TUint32)(aAddress) + 4); |
|
374 |
|
375 return aVal; |
|
376 } |
|
377 |
|
378 TUint32 arm_carry_bit(void) |
|
379 { |
|
380 //#define ARM_CARRY_BIT 0x20000000 // bit 30 |
|
381 |
|
382 TUint32 aVal = 0x20000000; |
|
383 |
|
384 return aVal; |
|
385 } |
|
386 |
|
387 // Thumb instruction bitmasks |
|
388 TUint16 thumb_opcode(const TUint16 aInst) |
|
389 { |
|
390 // #define THUMB_OPCODE(x) (((TUint16)(x) & 0xF800) >> 11) |
|
391 |
|
392 TUint16 aVal = ((aInst) & 0xF800) >> 11; |
|
393 |
|
394 return aVal; |
|
395 } |
|
396 |
|
397 TUint16 thumb_inst_7_15(const TUint16 aInst) |
|
398 { |
|
399 // #define THUMB_INST_7_15(x) (((TUint16)(x) & 0xFF80) >> 7) |
|
400 |
|
401 TUint16 aVal = ((aInst) & 0xFF80) >> 7; |
|
402 |
|
403 return aVal; |
|
404 } |
|
405 |
|
406 TUint16 thumb_inst_8_15(const TUint16 aInst) |
|
407 { |
|
408 // #define THUMB_INST_8_15(x) (((TUint16)(x) & 0xFF00) >> 8) |
|
409 |
|
410 TUint16 aVal = ((aInst) & 0xFF00) >> 8; |
|
411 |
|
412 return aVal; |
|
413 } |
|
414 |
|
415 |
|
416 |
|
417 TBool IsExecuted(TUint8 aCondition ,TUint32 aStatusRegister) |
|
418 { |
|
419 LOG_MSG("DRMDStepping::IsExecuted()"); |
|
420 |
|
421 TBool N = ((aStatusRegister >> 28) & 0x0000000F) & 0x00000008; |
|
422 TBool Z = ((aStatusRegister >> 28) & 0x0000000F) & 0x00000004; |
|
423 TBool C = ((aStatusRegister >> 28) & 0x0000000F) & 0x00000002; |
|
424 TBool V = ((aStatusRegister >> 28) & 0x0000000F) & 0x00000001; |
|
425 |
|
426 switch(aCondition) |
|
427 { |
|
428 case 0: |
|
429 return Z; |
|
430 case 1: |
|
431 return !Z; |
|
432 case 2: |
|
433 return C; |
|
434 case 3: |
|
435 return !C; |
|
436 case 4: |
|
437 return N; |
|
438 case 5: |
|
439 return !N; |
|
440 case 6: |
|
441 return V; |
|
442 case 7: |
|
443 return !V; |
|
444 case 8: |
|
445 return (C && !Z); |
|
446 case 9: |
|
447 return (!C || Z); |
|
448 case 10: |
|
449 return (N == V); |
|
450 case 11: |
|
451 return (N != V); |
|
452 case 12: |
|
453 return ((N == V) && !Z); |
|
454 case 13: |
|
455 return (Z || (N != V)); |
|
456 case 14: |
|
457 case 15: |
|
458 return ETrue; |
|
459 } |
|
460 |
|
461 return EFalse; |
|
462 } |
|
463 |
|
464 TBool DDebuggerEventHandler::IsPreviousInstructionMovePCToLR(DThread *aThread) |
|
465 { |
|
466 TInt err = KErrNone; |
|
467 |
|
468 // there are several types of instructions that modify the PC that aren't |
|
469 // designated as linked or non linked branches. the way gcc generates the |
|
470 // code can tell us whether or not these instructions are to be treated as |
|
471 // linked branches. the main cases are bx and any type of mov or load or |
|
472 // arithmatic operation that changes the PC. if these are really just |
|
473 // function calls that will return, gcc will generate a mov lr, pc |
|
474 // instruction as the previous instruction. note that this is just for arm |
|
475 // and armi |
|
476 |
|
477 // get the address of the previous instruction |
|
478 TUint32 address = 0; |
|
479 //err = iChannel->ReadKernelRegisterValue(aThread, PC_REGISTER, address); |
|
480 err = ReadKernelRegisterValue(aThread, PC_REGISTER, address); |
|
481 if(err != KErrNone) |
|
482 { |
|
483 LOG_MSG2("Non-zero error code discarded: %d", err); |
|
484 } |
|
485 address -= 4; |
|
486 |
|
487 TBuf8<4> previousInstruction; |
|
488 err = DoReadMemory(aThread, address, 4, previousInstruction); |
|
489 if (KErrNone != err) |
|
490 { |
|
491 LOG_MSG2("Error %d reading memory at address %x", address); |
|
492 return EFalse; |
|
493 } |
|
494 |
|
495 const TUint32 movePCToLRIgnoringCondition = 0x01A0E00F; |
|
496 |
|
497 TUint32 inst = *(TUint32 *)previousInstruction.Ptr(); |
|
498 |
|
499 if ((inst & 0x0FFFFFFF) == movePCToLRIgnoringCondition) |
|
500 { |
|
501 return ETrue; |
|
502 } |
|
503 |
|
504 return EFalse; |
|
505 } |
|
506 |
|
507 void DecodeDataProcessingInstruction(TUint8 aOpcode, TUint32 aOp1, TUint32 aOp2, TUint32 aStatusRegister, TUint32 &aBreakAddress) |
|
508 { |
|
509 LOG_MSG("DRMDStepping::DecodeDataProcessingInstruction()"); |
|
510 |
|
511 switch(aOpcode) |
|
512 { |
|
513 case 0: |
|
514 { |
|
515 // AND |
|
516 aBreakAddress = aOp1 & aOp2; |
|
517 break; |
|
518 } |
|
519 case 1: |
|
520 { |
|
521 // EOR |
|
522 aBreakAddress = aOp1 ^ aOp2; |
|
523 break; |
|
524 } |
|
525 case 2: |
|
526 { |
|
527 // SUB |
|
528 aBreakAddress = aOp1 - aOp2; |
|
529 break; |
|
530 } |
|
531 case 3: |
|
532 { |
|
533 // RSB |
|
534 aBreakAddress = aOp2 - aOp1; |
|
535 break; |
|
536 } |
|
537 case 4: |
|
538 { |
|
539 // ADD |
|
540 aBreakAddress = aOp1 + aOp2; |
|
541 break; |
|
542 } |
|
543 case 5: |
|
544 { |
|
545 // ADC |
|
546 aBreakAddress = aOp1 + aOp2 + (aStatusRegister & arm_carry_bit()) ? 1 : 0; |
|
547 break; |
|
548 } |
|
549 case 6: |
|
550 { |
|
551 // SBC |
|
552 aBreakAddress = aOp1 - aOp2 - (aStatusRegister & arm_carry_bit()) ? 0 : 1; |
|
553 break; |
|
554 } |
|
555 case 7: |
|
556 { |
|
557 // RSC |
|
558 aBreakAddress = aOp2 - aOp1 - (aStatusRegister & arm_carry_bit()) ? 0 : 1; |
|
559 break; |
|
560 } |
|
561 case 12: |
|
562 { |
|
563 // ORR |
|
564 aBreakAddress = aOp1 | aOp2; |
|
565 break; |
|
566 } |
|
567 case 13: |
|
568 { |
|
569 // MOV |
|
570 aBreakAddress = aOp2; |
|
571 break; |
|
572 } |
|
573 case 14: |
|
574 { |
|
575 // BIC |
|
576 aBreakAddress = aOp1 & ~aOp2; |
|
577 break; |
|
578 } |
|
579 case 15: |
|
580 { |
|
581 // MVN |
|
582 aBreakAddress = ~aOp2; |
|
583 break; |
|
584 } |
|
585 } |
|
586 } |
|
587 |
|
588 |
|
589 // Returns the current instruction bitpattern (either 32-bits or 16-bits) if possible |
|
590 //BEGIN TOMSCI who was smoking crack while writing this? |
|
591 |
|
592 TInt DDebuggerEventHandler::CurrentInstructionArm(DThread* aThread, TUint32& aInstruction) |
|
593 { |
|
594 TUint32 pc; |
|
595 ReturnIfError(CurrentPC(aThread,pc)); |
|
596 TBuf8<4> buf; |
|
597 ReturnIfError(DoReadMemory(aThread, pc, 4, buf)); |
|
598 aInstruction = *(TUint32*)buf.Ptr(); |
|
599 return KErrNone; |
|
600 } |
|
601 |
|
602 TInt DDebuggerEventHandler::CurrentInstructionThumb(DThread* aThread, TUint32& aInstruction) |
|
603 { |
|
604 TUint32 pc; |
|
605 ReturnIfError(CurrentPC(aThread,pc)); |
|
606 TBuf8<2> buf; |
|
607 ReturnIfError(DoReadMemory(aThread, pc, 2, buf)); |
|
608 aInstruction = *(TUint16*)buf.Ptr(); |
|
609 return KErrNone; |
|
610 } |
|
611 |
|
612 /* |
|
613 TInt DDebuggerEventHandler::CurrentInstruction(DThread* aThread, TUint32& aInstruction) |
|
614 { |
|
615 LOG_MSG("DRMDStepping::CurrentInstruction"); |
|
616 |
|
617 // What is the current PC? |
|
618 TUint32 pc; |
|
619 ReturnIfError(CurrentPC(aThread,pc)); |
|
620 |
|
621 |
|
622 // Read it one byte at a time to ensure alignment doesn't matter |
|
623 TUint32 inst = 0; |
|
624 for(TInt i=3;i>=0;i--) |
|
625 { |
|
626 |
|
627 TBuf8<1> instruction; |
|
628 TInt err = iChannel->DoReadMemory(aThread, (pc+i), 1, instruction); |
|
629 if (KErrNone != err) |
|
630 { |
|
631 LOG_MSG2("DRMDStepping::CurrentInstruction : Failed to read memory at current PC: return 0x%08x",pc); |
|
632 return err; |
|
633 } |
|
634 |
|
635 inst = (inst << 8) | (*(TUint8 *)instruction.Ptr()); |
|
636 } |
|
637 |
|
638 aInstruction = inst; |
|
639 |
|
640 LOG_MSG2("DRMDStepping::CurrentInstruction 0x%08x", aInstruction); |
|
641 |
|
642 return KErrNone; |
|
643 } |
|
644 END TOMSCI*/ |
|
645 |
|
646 // Determines architecture mode from the supplied cpsr |
|
647 TInt CurrentArchMode(const TUint32 aCpsr, Debug::TArchitectureMode& aMode) |
|
648 { |
|
649 // Thumb2 work will depend on having a suitable cpu architecture to compile for... |
|
650 #ifdef ECpuJf |
|
651 // State table as per ARM ARM DDI0406A, section A.2.5.1 |
|
652 if(aCpsr & ECpuJf) |
|
653 { |
|
654 if (aCpsr & ECpuThumb) |
|
655 { |
|
656 // ThumbEE (Thumb2) |
|
657 aMode = Debug::EThumb2EEMode; |
|
658 } |
|
659 else |
|
660 { |
|
661 // Jazelle mode - not supported |
|
662 return KErrNotSupported; |
|
663 } |
|
664 } |
|
665 else |
|
666 #endif |
|
667 { |
|
668 if (aCpsr & ECpuThumb) |
|
669 { |
|
670 // Thumb mode |
|
671 aMode = Debug::EThumbMode; |
|
672 } |
|
673 else |
|
674 { |
|
675 // ARM mode |
|
676 aMode = Debug::EArmMode; |
|
677 } |
|
678 } |
|
679 |
|
680 return KErrNone; |
|
681 } |
|
682 |
|
683 // |
|
684 // DRMDStepping::PCAfterInstructionExecutes |
|
685 // |
|
686 // Note, this function pretty much ignores all the arguments except for aThread. |
|
687 // The arguments continue to exist so that the function has the same prototype as |
|
688 // the original from Nokia. In the long term this function will be re-factored |
|
689 // to remove obsolete parameters. |
|
690 // |
|
691 TUint32 DDebuggerEventHandler::PCAfterInstructionExecutes(DThread *aThread, TUint32 aCurrentPC, TUint32 aStatusRegister, TInt aInstSize, /*TBool aStepInto,*/ TUint32 &aNewRangeEnd, TBool &aChangingModes) |
|
692 { |
|
693 LOG_MSG("DRMDStepping::PCAfterInstructionExecutes()"); |
|
694 |
|
695 // by default we will set the breakpoint at the next instruction |
|
696 TUint32 breakAddress = aCurrentPC + aInstSize; |
|
697 |
|
698 TInt err = KErrNone; |
|
699 |
|
700 // determine the architecture |
|
701 TUint32 cpuid; |
|
702 asm("mrc p15, 0, cpuid, c0, c0, 0 "); |
|
703 LOG_MSG2("DRMDStepping::PCAfterInstructionExecutes() - cpuid = 0x%08x\n",cpuid); |
|
704 |
|
705 cpuid >>= 8; |
|
706 cpuid &= 0xFF; |
|
707 |
|
708 // determine the architecture mode for the current instruction |
|
709 TArchitectureMode mode = EArmMode; // Default assumption is ARM |
|
710 |
|
711 // Now we must examine the CPSR to read the T and J bits. See ARM ARM DDI0406A, section B1.3.3 |
|
712 TUint32 cpsr; |
|
713 |
|
714 ReturnIfError(CurrentCPSR(aThread,cpsr)); |
|
715 LOG_MSG2("DRMDStepping::PCAfterInstructionExecutes() - cpsr = 0x%08x\n",cpsr); |
|
716 |
|
717 aStatusRegister = cpsr; // The passed-in value of aStatusRegister is ignored, but I can't be bothered to change all the code below. -Tomsci |
|
718 |
|
719 // Determine the mode |
|
720 ReturnIfError(CurrentArchMode(cpsr,mode)); |
|
721 |
|
722 // Decode instruction based on current CPU mode |
|
723 switch(mode) |
|
724 { |
|
725 case Debug::EArmMode: |
|
726 { |
|
727 // Obtain the current instruction bit pattern |
|
728 TUint32 inst; |
|
729 ReturnIfError(CurrentInstructionArm(aThread,inst)); |
|
730 |
|
731 LOG_MSG2("Current instruction: %x", inst); |
|
732 |
|
733 // check the conditions to see if this will actually get executed |
|
734 if (IsExecuted(((inst>>28) & 0x0000000F), aStatusRegister)) |
|
735 { |
|
736 switch(arm_opcode(inst)) // bits 27-25 |
|
737 { |
|
738 case 0: |
|
739 { |
|
740 switch((inst & 0x00000010) >> 4) // bit 4 |
|
741 { |
|
742 case 0: |
|
743 { |
|
744 switch((inst & 0x01800000) >> 23) // bits 24-23 |
|
745 { |
|
746 case 2: |
|
747 { |
|
748 // move to/from status register. pc updates not allowed |
|
749 // or TST, TEQ, CMP, CMN which don't modify the PC |
|
750 break; |
|
751 } |
|
752 default: |
|
753 { |
|
754 // Data processing immediate shift |
|
755 if (arm_rd(inst) == PC_REGISTER) |
|
756 { |
|
757 TUint32 rn = aCurrentPC + 8; |
|
758 if (arm_rn(inst) != PC_REGISTER) // bits 19-16 |
|
759 { |
|
760 err = iChannel->ReadKernelRegisterValue(aThread, arm_rn(inst), rn); |
|
761 if(err != KErrNone) |
|
762 { |
|
763 LOG_MSG2("Non-zero error code discarded: %d", err); |
|
764 } |
|
765 } |
|
766 |
|
767 TUint32 shifter = ShiftedRegValue(aThread, inst, aCurrentPC, aStatusRegister); |
|
768 |
|
769 DecodeDataProcessingInstruction(((inst & 0x01E00000) >> 21), rn, shifter, aStatusRegister, breakAddress); |
|
770 } |
|
771 break; |
|
772 } |
|
773 } |
|
774 break; |
|
775 } |
|
776 case 1: |
|
777 { |
|
778 switch((inst & 0x00000080) >> 7) // bit 7 |
|
779 { |
|
780 case 0: |
|
781 { |
|
782 switch((inst & 0x01900000) >> 20) // bits 24-23 and bit 20 |
|
783 { |
|
784 case 0x10: |
|
785 { |
|
786 // from figure 3-3 |
|
787 switch((inst & 0x000000F0) >> 4) // bits 7-4 |
|
788 { |
|
789 case 1: |
|
790 { |
|
791 if (((inst & 0x00400000) >> 22) == 0) // bit 22 |
|
792 { |
|
793 // BX |
|
794 // this is a strange case. normally this is used in the epilogue to branch the the link |
|
795 // register. sometimes it is used to call a function, and the LR is stored in the previous |
|
796 // instruction. since what we want to do is different for the two cases when stepping over, |
|
797 // we need to read the previous instruction to see what we should do |
|
798 err = iChannel->ReadKernelRegisterValue(aThread, (inst & 0x0000000F), breakAddress); |
|
799 if(err != KErrNone) |
|
800 { |
|
801 LOG_MSG2("Non-zero error code discarded: %d", err); |
|
802 } |
|
803 |
|
804 if ((breakAddress & 0x00000001) == 1) |
|
805 { |
|
806 aChangingModes = ETrue; |
|
807 } |
|
808 |
|
809 breakAddress &= 0xFFFFFFFE; |
|
810 } |
|
811 break; |
|
812 } |
|
813 case 3: |
|
814 { |
|
815 // BLX |
|
816 { |
|
817 err = iChannel->ReadKernelRegisterValue(aThread, (inst & 0x0000000F), breakAddress); |
|
818 if(err != KErrNone) |
|
819 { |
|
820 LOG_MSG2("Non-zero error code discarded: %d", err); |
|
821 } |
|
822 |
|
823 if ((breakAddress & 0x00000001) == 1) |
|
824 { |
|
825 aChangingModes = ETrue; |
|
826 } |
|
827 |
|
828 breakAddress &= 0xFFFFFFFE; |
|
829 } |
|
830 break; |
|
831 } |
|
832 default: |
|
833 { |
|
834 // either doesn't modify the PC or it is illegal to |
|
835 break; |
|
836 } |
|
837 } |
|
838 break; |
|
839 } |
|
840 default: |
|
841 { |
|
842 // Data processing register shift |
|
843 if (((inst & 0x01800000) >> 23) == 2) // bits 24-23 |
|
844 { |
|
845 // TST, TEQ, CMP, CMN don't modify the PC |
|
846 } |
|
847 else if (arm_rd(inst) == PC_REGISTER) |
|
848 { |
|
849 // destination register is the PC |
|
850 TUint32 rn = aCurrentPC + 8; |
|
851 if (arm_rn(inst) != PC_REGISTER) // bits 19-16 |
|
852 { |
|
853 err = iChannel->ReadKernelRegisterValue(aThread, arm_rn(inst), rn); |
|
854 if(err != KErrNone) |
|
855 { |
|
856 LOG_MSG2("Non-zero error code discarded: %d", err); |
|
857 } |
|
858 } |
|
859 |
|
860 TUint32 shifter = ShiftedRegValue(aThread, inst, aCurrentPC, aStatusRegister); |
|
861 |
|
862 DecodeDataProcessingInstruction(((inst & 0x01E00000) >> 21), rn, shifter, aStatusRegister, breakAddress); |
|
863 } |
|
864 break; |
|
865 } |
|
866 } |
|
867 break; |
|
868 } |
|
869 default: |
|
870 { |
|
871 // from figure 3-2, updates to the PC illegal |
|
872 break; |
|
873 } |
|
874 } |
|
875 break; |
|
876 } |
|
877 } |
|
878 break; |
|
879 } |
|
880 case 1: |
|
881 { |
|
882 if (((inst & 0x01800000) >> 23) == 2) // bits 24-23 |
|
883 { |
|
884 // cannot modify the PC |
|
885 break; |
|
886 } |
|
887 else if (arm_rd(inst) == PC_REGISTER) |
|
888 { |
|
889 // destination register is the PC |
|
890 TUint32 rn; |
|
891 err = iChannel->ReadKernelRegisterValue(aThread, arm_rn(inst), rn); // bits 19-16 |
|
892 if(err != KErrNone) |
|
893 { |
|
894 LOG_MSG2("Non-zero error code discarded: %d", err); |
|
895 } |
|
896 TUint32 shifter = ((arm_data_imm(inst) >> arm_data_rot(inst)) | (arm_data_imm(inst) << (32 - arm_data_rot(inst)))) & 0xffffffff; |
|
897 |
|
898 DecodeDataProcessingInstruction(((inst & 0x01E00000) >> 21), rn, shifter, aStatusRegister, breakAddress); |
|
899 } |
|
900 break; |
|
901 } |
|
902 case 2: |
|
903 { |
|
904 // load/store immediate offset |
|
905 if (arm_load(inst)) // bit 20 |
|
906 { |
|
907 // loading a register from memory |
|
908 if (arm_rd(inst) == PC_REGISTER) |
|
909 { |
|
910 // loading the PC register |
|
911 TUint32 base; |
|
912 err = iChannel->ReadKernelRegisterValue(aThread, arm_rn(inst), base); |
|
913 if(err != KErrNone) |
|
914 { |
|
915 LOG_MSG2("Non-zero error code discarded: %d", err); |
|
916 } |
|
917 |
|
918 /* Note: At runtime the PC would be 8 further on |
|
919 */ |
|
920 if (arm_rn(inst) == PC_REGISTER) |
|
921 { |
|
922 base = aCurrentPC + 8; |
|
923 } |
|
924 |
|
925 TUint32 offset = 0; |
|
926 |
|
927 if (arm_single_pre(inst)) |
|
928 { |
|
929 // Pre-indexing |
|
930 offset = arm_single_imm(inst); |
|
931 |
|
932 if (arm_single_u(inst)) |
|
933 { |
|
934 base += offset; |
|
935 } |
|
936 else |
|
937 { |
|
938 base -= offset; |
|
939 } |
|
940 } |
|
941 |
|
942 TBuf8<4> destination; |
|
943 err = iChannel->DoReadMemory(aThread, base, 4, destination); |
|
944 |
|
945 if (KErrNone == err) |
|
946 { |
|
947 breakAddress = *(TUint32 *)destination.Ptr(); |
|
948 |
|
949 if ((breakAddress & 0x00000001) == 1) |
|
950 { |
|
951 aChangingModes = ETrue; |
|
952 } |
|
953 breakAddress &= 0xFFFFFFFE; |
|
954 } |
|
955 else |
|
956 { |
|
957 LOG_MSG("Error reading memory in decoding step instruction"); |
|
958 } |
|
959 } |
|
960 } |
|
961 break; |
|
962 } |
|
963 case 3: |
|
964 { |
|
965 if (((inst & 0xF0000000) != 0xF0000000) && ((inst & 0x00000010) == 0)) |
|
966 { |
|
967 // load/store register offset |
|
968 if (arm_load(inst)) // bit 20 |
|
969 { |
|
970 // loading a register from memory |
|
971 if (arm_rd(inst) == PC_REGISTER) |
|
972 { |
|
973 // loading the PC register |
|
974 TUint32 base = 0; |
|
975 if(arm_rn(inst) == PC_REGISTER) |
|
976 { |
|
977 base = aCurrentPC + 8; |
|
978 } |
|
979 else |
|
980 { |
|
981 err = iChannel->ReadKernelRegisterValue(aThread, arm_rn(inst), base); |
|
982 if(err != KErrNone) |
|
983 { |
|
984 LOG_MSG2("Non-zero error code discarded: %d", err); |
|
985 } |
|
986 } |
|
987 |
|
988 TUint32 offset = 0; |
|
989 |
|
990 if (arm_single_pre(inst)) |
|
991 { |
|
992 offset = ShiftedRegValue(aThread, inst, aCurrentPC, aStatusRegister); |
|
993 |
|
994 if (arm_single_u(inst)) |
|
995 { |
|
996 base += offset; |
|
997 } |
|
998 else |
|
999 { |
|
1000 base -= offset; |
|
1001 } |
|
1002 } |
|
1003 |
|
1004 TBuf8<4> destination; |
|
1005 err = iChannel->DoReadMemory(aThread, base, 4, destination); |
|
1006 |
|
1007 if (KErrNone == err) |
|
1008 { |
|
1009 breakAddress = *(TUint32 *)destination.Ptr(); |
|
1010 |
|
1011 if ((breakAddress & 0x00000001) == 1) |
|
1012 { |
|
1013 aChangingModes = ETrue; |
|
1014 } |
|
1015 breakAddress &= 0xFFFFFFFE; |
|
1016 } |
|
1017 else |
|
1018 { |
|
1019 LOG_MSG("Error reading memory in decoding step instruction"); |
|
1020 } |
|
1021 } |
|
1022 } |
|
1023 } |
|
1024 break; |
|
1025 } |
|
1026 case 4: |
|
1027 { |
|
1028 if ((inst & 0xF0000000) != 0xF0000000) |
|
1029 { |
|
1030 // load/store multiple |
|
1031 if (arm_load(inst)) // bit 20 |
|
1032 { |
|
1033 // loading a register from memory |
|
1034 if (((inst & 0x00008000) >> 15)) |
|
1035 { |
|
1036 // loading the PC register |
|
1037 TInt offset = 0; |
|
1038 if (arm_block_u(inst)) |
|
1039 { |
|
1040 TUint32 reglist = arm_block_reglist(inst); |
|
1041 offset = BitCount(reglist) * 4 - 4; |
|
1042 if (arm_block_pre(inst)) |
|
1043 offset += 4; |
|
1044 } |
|
1045 else if (arm_block_pre(inst)) |
|
1046 { |
|
1047 offset = -4; |
|
1048 } |
|
1049 |
|
1050 TUint32 temp = 0; |
|
1051 err = iChannel->ReadKernelRegisterValue(aThread, arm_rn(inst), temp); |
|
1052 if(err != KErrNone) |
|
1053 { |
|
1054 LOG_MSG2("Non-zero error code discarded: %d", err); |
|
1055 } |
|
1056 |
|
1057 temp += offset; |
|
1058 |
|
1059 TBuf8<4> destination; |
|
1060 err = iChannel->DoReadMemory(aThread, temp, 4, destination); |
|
1061 |
|
1062 if (KErrNone == err) |
|
1063 { |
|
1064 breakAddress = *(TUint32 *)destination.Ptr(); |
|
1065 if ((breakAddress & 0x00000001) == 1) |
|
1066 { |
|
1067 aChangingModes = ETrue; |
|
1068 } |
|
1069 breakAddress &= 0xFFFFFFFE; |
|
1070 } |
|
1071 else |
|
1072 { |
|
1073 LOG_MSG("Error reading memory in decoding step instruction"); |
|
1074 } |
|
1075 } |
|
1076 } |
|
1077 } |
|
1078 break; |
|
1079 } |
|
1080 case 5: |
|
1081 { |
|
1082 if ((inst & 0xF0000000) == 0xF0000000) |
|
1083 { |
|
1084 // BLX |
|
1085 { |
|
1086 breakAddress = (TUint32)arm_instr_b_dest(inst, aCurrentPC); |
|
1087 |
|
1088 // Unconditionally change into Thumb mode |
|
1089 aChangingModes = ETrue; |
|
1090 |
|
1091 breakAddress &= 0xFFFFFFFE; |
|
1092 } |
|
1093 } |
|
1094 else |
|
1095 { |
|
1096 if ((inst & 0x01000000)) // bit 24 |
|
1097 { |
|
1098 // BL |
|
1099 { |
|
1100 breakAddress = (TUint32)arm_instr_b_dest(inst, aCurrentPC); |
|
1101 } |
|
1102 } |
|
1103 else |
|
1104 { |
|
1105 // B |
|
1106 breakAddress = (TUint32)arm_instr_b_dest(inst, aCurrentPC); |
|
1107 } |
|
1108 } |
|
1109 break; |
|
1110 } |
|
1111 } |
|
1112 } |
|
1113 } |
|
1114 break; |
|
1115 |
|
1116 case Debug::EThumbMode: |
|
1117 { |
|
1118 // Thumb Mode |
|
1119 // |
|
1120 // Notes: This now includes the extra code |
|
1121 // required to decode V6T2 instructions |
|
1122 |
|
1123 LOG_MSG("DRMDStepping::PCAfterInstructionExecutes: Thumb Instruction"); |
|
1124 |
|
1125 TUint16 inst; |
|
1126 |
|
1127 // Obtain the current instruction bit pattern |
|
1128 TUint32 inst32; |
|
1129 ReturnIfError(CurrentInstructionThumb(aThread,inst32)); |
|
1130 |
|
1131 inst = static_cast<TUint16>(inst32 & 0xFFFF); |
|
1132 |
|
1133 LOG_MSG2("Current Thumb instruction: 0x%x", inst); |
|
1134 |
|
1135 // v6T2 instructions |
|
1136 |
|
1137 // Note: v6T2 decoding is only enabled for DEBUG builds or if using an |
|
1138 // an ARM_V6T2 supporting build system. At the time of writing, no |
|
1139 // ARM_V6T2 supporting build system exists, so the stepping code cannot |
|
1140 // be said to be known to work. Hence it is not run for release builds |
|
1141 |
|
1142 TBool use_v6t2_decodings = EFalse; |
|
1143 |
|
1144 #if defined(DEBUG) || defined(__ARMV6T2__) |
|
1145 use_v6t2_decodings = ETrue; |
|
1146 |
|
1147 #endif |
|
1148 // coverity[dead_error_line] |
|
1149 if (use_v6t2_decodings) |
|
1150 { |
|
1151 // 16-bit encodings |
|
1152 |
|
1153 // A6.2.5 Misc 16-bit instructions |
|
1154 // DONE Compare and branch on zero (page A8-66) |
|
1155 // If then hints |
|
1156 |
|
1157 // ARM ARM DDI0406A - section A8.6.27 CBNZ, CBZ |
|
1158 // |
|
1159 // Compare and branch on Nonzero and Compare and Branch on Zero. |
|
1160 if ((inst & 0xF500) == 0xB100) |
|
1161 { |
|
1162 LOG_MSG("ARM ARM DDI0406A - section A8.6.27 CBNZ, CBZ"); |
|
1163 |
|
1164 // Decoding as per ARM ARM description |
|
1165 TUint32 op = (inst & 0x0800) >> 11; |
|
1166 TUint32 i = (inst & 0x0200) >> 9; |
|
1167 TUint32 imm5 = (inst & 0x00F8) >> 3; |
|
1168 TUint32 Rn = inst & 0x0007; |
|
1169 |
|
1170 TUint32 imm32 = (i << 6) | (imm5 << 1); |
|
1171 |
|
1172 // Obtain value for register Rn |
|
1173 TUint32 RnVal = 0; |
|
1174 ReturnIfError(RegisterValue(aThread,Rn,RnVal)); |
|
1175 |
|
1176 if (op) |
|
1177 { |
|
1178 // nonzero |
|
1179 if (RnVal != 0x0) |
|
1180 { |
|
1181 // Branch |
|
1182 breakAddress = aCurrentPC + imm32; |
|
1183 } |
|
1184 } |
|
1185 else |
|
1186 { |
|
1187 // zero |
|
1188 if (RnVal == 0x0) |
|
1189 { |
|
1190 // Branch |
|
1191 breakAddress = aCurrentPC + imm32; |
|
1192 } |
|
1193 } |
|
1194 } |
|
1195 |
|
1196 // ARM ARM DDI0406A - section A8.6.50 IT |
|
1197 // |
|
1198 // If Then instruction |
|
1199 if ((inst & 0xFF00) == 0xBF00) |
|
1200 { |
|
1201 LOG_MSG("ARM ARM DDI0406A - section A8.6.50 IT"); |
|
1202 |
|
1203 // Decoding as per ARM ARM description |
|
1204 TUint32 firstcond = inst & 0x00F0 >> 4; |
|
1205 TUint32 mask = inst & 0x000F; |
|
1206 |
|
1207 if (firstcond == 0xF) |
|
1208 { |
|
1209 // unpredictable |
|
1210 LOG_MSG("ARM ARM DDI0406A - section A8.6.50 IT - Unpredictable"); |
|
1211 break; |
|
1212 } |
|
1213 |
|
1214 if ((firstcond == 0xE) && (BitCount(mask) != 1)) |
|
1215 { |
|
1216 // unpredictable |
|
1217 LOG_MSG("ARM ARM DDI0406A - section A8.6.50 IT - Unpredictable"); |
|
1218 break; |
|
1219 } |
|
1220 |
|
1221 // should check if 'in-it-block' |
|
1222 LOG_MSG("Cannot step IT instructions."); |
|
1223 |
|
1224 // all the conds are as per Table A8-1 (i.e. the usual 16 cases) |
|
1225 // no idea how to decode the it block 'after-the-fact' |
|
1226 // so probably need to treat instructions in the it block |
|
1227 // as 'may' be executed. So breakpoints at both possible locations |
|
1228 // depending on whether the instruction is executed or not. |
|
1229 |
|
1230 // also, how do we know if we have hit a breakpoint whilst 'in' an it block? |
|
1231 // can we check the status registers to find out? |
|
1232 // |
|
1233 // see arm arm page 390. |
|
1234 // |
|
1235 // seems to depend on the itstate field. this also says what the condition code |
|
1236 // actually is, and how many instructions are left in the itblock. |
|
1237 // perhaps we can just totally ignore this state, and always do the two-instruction |
|
1238 // breakpoint thing? Not if there is any possibility that the address target |
|
1239 // would be invalid for the non-taken branch address... |
|
1240 } |
|
1241 |
|
1242 |
|
1243 // 32-bit encodings. |
|
1244 // |
|
1245 |
|
1246 // Load word A6-23 |
|
1247 // Data processing instructions a6-28 |
|
1248 // |
|
1249 |
|
1250 // ARM ARM DDI0406A - section A8.6.26 |
|
1251 if (inst32 & 0xFFF0FFFF == 0xE3C08F00) |
|
1252 { |
|
1253 LOG_MSG("ARM ARM DDI0406A - section A8.6.26 - BXJ is not supported"); |
|
1254 |
|
1255 // Decoding as per ARM ARM description |
|
1256 // TUint32 Rm = inst32 & 0x000F0000; // not needed yet |
|
1257 } |
|
1258 |
|
1259 // return from exception... SUBS PC,LR. page b6-25 |
|
1260 // |
|
1261 // ARM ARM DDi046A - section B6.1.13 - SUBS PC,LR |
|
1262 // |
|
1263 // Encoding T1 |
|
1264 if (inst32 & 0xFFFFFF00 == 0xF3DE8F00) |
|
1265 { |
|
1266 LOG_MSG("ARM ARM DDI0406A - section B6.1.13 - SUBS PC,LR Encoding T1"); |
|
1267 |
|
1268 // Decoding as per ARM ARM description |
|
1269 TUint32 imm8 = inst32 & 0x000000FF; |
|
1270 TUint32 imm32 = imm8; |
|
1271 |
|
1272 // TUint32 register_form = EFalse; // not needed for this decoding |
|
1273 // TUint32 opcode = 0x2; // SUB // not needed for this decoding |
|
1274 TUint32 n = 14; |
|
1275 |
|
1276 // Obtain LR |
|
1277 TUint32 lrVal; |
|
1278 ReturnIfError(RegisterValue(aThread,n,lrVal)); |
|
1279 |
|
1280 TUint32 operand2 = imm32; // always for Encoding T1 |
|
1281 |
|
1282 TUint32 result = lrVal - operand2; |
|
1283 |
|
1284 breakAddress = result; |
|
1285 } |
|
1286 |
|
1287 // ARM ARM DDI0406A - section A8.6.16 - B |
|
1288 // |
|
1289 // Branch Encoding T3 |
|
1290 if (inst32 & 0xF800D000 == 0xF0008000) |
|
1291 { |
|
1292 LOG_MSG("ARM ARM DDI0406A - section A8.6.16 - B Encoding T3"); |
|
1293 |
|
1294 // Decoding as per ARM ARM description |
|
1295 TUint32 S = inst32 & 0x04000000 >> 26; |
|
1296 // TUint32 cond = inst32 & 0x03C00000 >> 22; // not needed for this decoding |
|
1297 TUint32 imm6 = inst32 & 0x003F0000 >> 16; |
|
1298 TUint32 J1 = inst32 & 0x00002000 >> 13; |
|
1299 TUint32 J2 = inst32 & 0x00000800 >> 11; |
|
1300 TUint32 imm11 = inst32 & 0x000007FF; |
|
1301 |
|
1302 TUint32 imm32 = S ? 0xFFFFFFFF : 0 ; |
|
1303 imm32 = (imm32 << 1) | J2; |
|
1304 imm32 = (imm32 << 1) | J1; |
|
1305 imm32 = (imm32 << 6) | imm6; |
|
1306 imm32 = (imm32 << 11) | imm11; |
|
1307 imm32 = (imm32 << 1) | 0; |
|
1308 |
|
1309 breakAddress = aCurrentPC + imm32; |
|
1310 } |
|
1311 |
|
1312 // ARM ARM DDI0406A - section A8.6.16 - B |
|
1313 // |
|
1314 // Branch Encoding T4 |
|
1315 if (inst32 & 0xF800D000 == 0xF0009000) |
|
1316 { |
|
1317 LOG_MSG("ARM ARM DDI0406A - section A8.6.16 - B"); |
|
1318 |
|
1319 // Decoding as per ARM ARM description |
|
1320 TUint32 S = inst32 & 0x04000000 >> 26; |
|
1321 TUint32 imm10 = inst32 & 0x03FF0000 >> 16; |
|
1322 TUint32 J1 = inst32 & 0x00002000 >> 12; |
|
1323 TUint32 J2 = inst32 & 0x00000800 >> 11; |
|
1324 TUint32 imm11 = inst32 & 0x000003FF; |
|
1325 |
|
1326 TUint32 I1 = !(J1 ^ S); |
|
1327 TUint32 I2 = !(J2 ^ S); |
|
1328 |
|
1329 TUint32 imm32 = S ? 0xFFFFFFFF : 0; |
|
1330 imm32 = (imm32 << 1) | S; |
|
1331 imm32 = (imm32 << 1) | I1; |
|
1332 imm32 = (imm32 << 1) | I2; |
|
1333 imm32 = (imm32 << 10) | imm10; |
|
1334 imm32 = (imm32 << 11) | imm11; |
|
1335 imm32 = (imm32 << 1) | 0; |
|
1336 |
|
1337 breakAddress = aCurrentPC + imm32; |
|
1338 } |
|
1339 |
|
1340 |
|
1341 // ARM ARM DDI0406A - section A8.6.225 - TBB, TBH |
|
1342 // |
|
1343 // Table Branch Byte, Table Branch Halfword |
|
1344 if (inst32 & 0xFFF0FFE0 == 0xE8D0F000) |
|
1345 { |
|
1346 LOG_MSG("ARM ARM DDI0406A - section A8.6.225 TBB,TBH Encoding T1"); |
|
1347 |
|
1348 // Decoding as per ARM ARM description |
|
1349 TUint32 Rn = inst32 & 0x000F0000 >> 16; |
|
1350 TUint32 H = inst32 & 0x00000010 >> 4; |
|
1351 TUint32 Rm = inst32 & 0x0000000F; |
|
1352 |
|
1353 // Unpredictable? |
|
1354 if (Rm == 13 || Rm == 15) |
|
1355 { |
|
1356 LOG_MSG("ARM ARM DDI0406A - section A8.6.225 TBB,TBH Encoding T1 - Unpredictable"); |
|
1357 break; |
|
1358 } |
|
1359 |
|
1360 TUint32 halfwords; |
|
1361 TUint32 address; |
|
1362 ReturnIfError(RegisterValue(aThread,Rn,address)); |
|
1363 |
|
1364 TUint32 offset; |
|
1365 ReturnIfError(RegisterValue(aThread,Rm,offset)); |
|
1366 |
|
1367 if (H) |
|
1368 { |
|
1369 |
|
1370 address += offset << 1; |
|
1371 } |
|
1372 else |
|
1373 { |
|
1374 address += offset; |
|
1375 } |
|
1376 |
|
1377 ReturnIfError(ReadMem32(aThread,address,halfwords)); |
|
1378 |
|
1379 breakAddress = aCurrentPC + 2*halfwords; |
|
1380 break; |
|
1381 } |
|
1382 |
|
1383 // ARM ARM DDI0406A - section A8.6.55 - LDMDB, LDMEA |
|
1384 // |
|
1385 // LDMDB Encoding T1 |
|
1386 if (inst32 & 0xFFD02000 == 0xE9100000) |
|
1387 { |
|
1388 LOG_MSG("ARM ARM DDI0406 - section A8.6.55 LDMDB Encoding T1"); |
|
1389 |
|
1390 // Decoding as per ARM ARM description |
|
1391 // TUint32 W = inst32 & 0x00200000 >> 21; // Not needed for this encoding |
|
1392 TUint32 Rn = inst32 & 0x000F0000 >> 16; |
|
1393 TUint32 P = inst32 & 0x00008000 >> 15; |
|
1394 TUint32 M = inst32 & 0x00004000 >> 14; |
|
1395 TUint32 registers = inst32 & 0x00001FFF; |
|
1396 |
|
1397 //TBool wback = (W == 1); // not needed for this encoding |
|
1398 |
|
1399 // Unpredictable? |
|
1400 if (Rn == 15 || BitCount(registers) < 2 || ((P == 1) && (M==1))) |
|
1401 { |
|
1402 LOG_MSG("ARM ARM DDI0406 - section A8.6.55 LDMDB Encoding T1 - Unpredictable"); |
|
1403 break; |
|
1404 } |
|
1405 |
|
1406 TUint32 address; |
|
1407 ReturnIfError(RegisterValue(aThread,Rn,address)); |
|
1408 |
|
1409 address -= 4*BitCount(registers); |
|
1410 |
|
1411 for(TInt i=0; i<15; i++) |
|
1412 { |
|
1413 if (IsBitSet(registers,i)) |
|
1414 { |
|
1415 address +=4; |
|
1416 } |
|
1417 } |
|
1418 |
|
1419 if (IsBitSet(registers,15)) |
|
1420 { |
|
1421 TUint32 RnVal = 0; |
|
1422 ReturnIfError(ReadMem32(aThread,address,RnVal)); |
|
1423 |
|
1424 breakAddress = RnVal; |
|
1425 } |
|
1426 break; |
|
1427 } |
|
1428 |
|
1429 // ARM ARM DDI0406A - section A8.6.121 POP |
|
1430 // |
|
1431 // POP.W Encoding T2 |
|
1432 if (inst32 & 0xFFFF2000 == 0xE8BD0000) |
|
1433 { |
|
1434 LOG_MSG("ARM ARM DDI0406A - section A8.6.121 POP Encoding T2"); |
|
1435 |
|
1436 // Decoding as per ARM ARM description |
|
1437 TUint32 registers = inst32 & 0x00001FFF; |
|
1438 TUint32 P = inst32 & 0x00008000; |
|
1439 TUint32 M = inst32 & 0x00004000; |
|
1440 |
|
1441 // Unpredictable? |
|
1442 if ( (BitCount(registers)<2) || ((P == 1)&&(M == 1)) ) |
|
1443 { |
|
1444 LOG_MSG("ARM ARM DDI0406A - section A8.6.121 POP Encoding T2 - Unpredictable"); |
|
1445 break; |
|
1446 } |
|
1447 |
|
1448 TUint32 address; |
|
1449 ReturnIfError(RegisterValue(aThread,13,address)); |
|
1450 |
|
1451 for(TInt i=0; i< 15; i++) |
|
1452 { |
|
1453 if (IsBitSet(registers,i)) |
|
1454 { |
|
1455 address += 4; |
|
1456 } |
|
1457 } |
|
1458 |
|
1459 // Is the PC written? |
|
1460 if (IsBitSet(registers,15)) |
|
1461 { |
|
1462 // Yes |
|
1463 ReturnIfError(ReadMem32(aThread,address,breakAddress)); |
|
1464 } |
|
1465 } |
|
1466 |
|
1467 // POP Encoding T3 |
|
1468 if (inst32 & 0xFFFF0FFFF == 0xF85D0B04) |
|
1469 { |
|
1470 LOG_MSG("ARM ARM DDI0406A - section A8.6.121 POP Encoding T3"); |
|
1471 |
|
1472 // Decoding as per ARM ARM description |
|
1473 TUint32 Rt = inst32 & 0x0000F000 >> 12; |
|
1474 TUint32 registers = 1 << Rt; |
|
1475 |
|
1476 // Unpredictable? |
|
1477 if (Rt == 13 || Rt == 15) |
|
1478 { |
|
1479 LOG_MSG("ARM ARM DDI0406A - section A8.6.121 POP Encoding T3 - Unpredictable"); |
|
1480 break; |
|
1481 } |
|
1482 |
|
1483 TUint32 address; |
|
1484 ReturnIfError(RegisterValue(aThread,13,address)); |
|
1485 |
|
1486 for(TInt i=0; i< 15; i++) |
|
1487 { |
|
1488 if (IsBitSet(registers,i)) |
|
1489 { |
|
1490 address += 4; |
|
1491 } |
|
1492 } |
|
1493 |
|
1494 // Is the PC written? |
|
1495 if (IsBitSet(registers,15)) |
|
1496 { |
|
1497 // Yes |
|
1498 ReturnIfError(ReadMem32(aThread,address,breakAddress)); |
|
1499 } |
|
1500 |
|
1501 break; |
|
1502 } |
|
1503 |
|
1504 // ARM ARM DDI0406A - section A8.6.53 LDM |
|
1505 // |
|
1506 // Load Multiple Encoding T2 |
|
1507 if ((inst32 & 0xFFD02000) == 0xE8900000) |
|
1508 { |
|
1509 LOG_MSG("ARM ARM DDI0406A - section A8.6.53 LDM Encoding T2"); |
|
1510 |
|
1511 // Decoding as per ARM ARM description |
|
1512 TUint32 W = inst32 & 0x0020000 >> 21; |
|
1513 TUint32 Rn = inst32 & 0x000F0000 >> 16; |
|
1514 TUint32 P = inst32 & 0x00008000 >> 15; |
|
1515 TUint32 M = inst32 & 0x00004000 >> 14; |
|
1516 TUint32 registers = inst32 & 0x0000FFFF; |
|
1517 TUint32 register_list = inst32 & 0x00001FFF; |
|
1518 |
|
1519 // POP? |
|
1520 if ( (W == 1) && (Rn == 13) ) |
|
1521 { |
|
1522 // POP instruction |
|
1523 LOG_MSG("ARM ARM DDI0406A - section A8.6.53 LDM Encoding T2 - POP"); |
|
1524 } |
|
1525 |
|
1526 // Unpredictable? |
|
1527 if (Rn == 15 || BitCount(register_list) < 2 || ((P == 1) && (M == 1)) ) |
|
1528 { |
|
1529 LOG_MSG("ARM ARM DDI0406A - section A8.6.53 LDM Encoding T2 - Unpredictable"); |
|
1530 break; |
|
1531 } |
|
1532 |
|
1533 TUint32 RnVal; |
|
1534 ReturnIfError(RegisterValue(aThread,Rn,RnVal)); |
|
1535 |
|
1536 TUint32 address = RnVal; |
|
1537 |
|
1538 // Calculate offset of address |
|
1539 for(TInt i = 0; i < 15; i++) |
|
1540 { |
|
1541 if (IsBitSet(registers,i)) |
|
1542 { |
|
1543 address += 4; |
|
1544 } |
|
1545 } |
|
1546 |
|
1547 // Does it load the PC? |
|
1548 if (IsBitSet(registers,15)) |
|
1549 { |
|
1550 // Obtain the value loaded into the PC |
|
1551 ReturnIfError(ReadMem32(aThread,address,breakAddress)); |
|
1552 } |
|
1553 break; |
|
1554 |
|
1555 } |
|
1556 |
|
1557 // ARM ARM DDI0406A - section B6.1.8 RFE |
|
1558 // |
|
1559 // Return From Exception Encoding T1 RFEDB |
|
1560 if ((inst32 & 0xFFD0FFFF) == 0xE810C000) |
|
1561 { |
|
1562 LOG_MSG("ARM ARM DDI0406A - section B6.1.8 RFE Encoding T1"); |
|
1563 |
|
1564 // Decoding as per ARM ARM description |
|
1565 // TUint32 W = (inst32 & 0x00200000) >> 21; // not needed for this encoding |
|
1566 TUint32 Rn = (inst32 & 0x000F0000) >> 16; |
|
1567 |
|
1568 // TBool wback = (W == 1); // not needed for this encoding |
|
1569 TBool increment = EFalse; |
|
1570 TBool wordhigher = EFalse; |
|
1571 |
|
1572 // Do calculation |
|
1573 if (Rn == 15) |
|
1574 { |
|
1575 // Unpredictable |
|
1576 LOG_MSG("ARM ARM DDI0406A - section B6.1.8 RFE Encoding T1 - Unpredictable"); |
|
1577 break; |
|
1578 } |
|
1579 |
|
1580 TUint32 RnVal = 0; |
|
1581 ReturnIfError(RegisterValue(aThread,Rn,RnVal)); |
|
1582 |
|
1583 TUint32 address = 0; |
|
1584 ReturnIfError(ReadMem32(aThread,RnVal,address)); |
|
1585 |
|
1586 if (increment) |
|
1587 { |
|
1588 address -= 8; |
|
1589 } |
|
1590 |
|
1591 if (wordhigher) |
|
1592 { |
|
1593 address += 4; |
|
1594 } |
|
1595 |
|
1596 breakAddress = address; |
|
1597 break; |
|
1598 } |
|
1599 |
|
1600 // Return From Exception Encoding T2 RFEIA |
|
1601 if ((inst32 & 0xFFD0FFFF) == 0xE990C000) |
|
1602 { |
|
1603 LOG_MSG("ARM ARM DDI0406A - section B6.1.8 RFE Encoding T2"); |
|
1604 |
|
1605 // Decoding as per ARM ARM description |
|
1606 // TUint32 W = (inst32 & 0x00200000) >> 21; // not needed for this encoding |
|
1607 TUint32 Rn = (inst32 & 0x000F0000) >> 16; |
|
1608 |
|
1609 // TBool wback = (W == 1); // not needed for this encoding |
|
1610 TBool increment = ETrue; |
|
1611 TBool wordhigher = EFalse; |
|
1612 |
|
1613 // Do calculation |
|
1614 if (Rn == 15) |
|
1615 { |
|
1616 // Unpredictable |
|
1617 LOG_MSG("ARM ARM DDI0406A - section B6.1.8 RFE Encoding T2 - Unpredictable"); |
|
1618 break; |
|
1619 } |
|
1620 |
|
1621 TUint32 RnVal = 0; |
|
1622 ReturnIfError(RegisterValue(aThread,Rn,RnVal)); |
|
1623 |
|
1624 TUint32 address = 0; |
|
1625 ReturnIfError(ReadMem32(aThread,RnVal,address)); |
|
1626 |
|
1627 if (increment) |
|
1628 { |
|
1629 address -= 8; |
|
1630 } |
|
1631 |
|
1632 if (wordhigher) |
|
1633 { |
|
1634 address += 4; |
|
1635 } |
|
1636 |
|
1637 breakAddress = RnVal; |
|
1638 break; |
|
1639 } |
|
1640 |
|
1641 // Return From Exception Encoding A1 RFE<amode> |
|
1642 if ((inst32 & 0xFE50FFFF) == 0xF8100A00) |
|
1643 { |
|
1644 LOG_MSG("ARM ARM DDI0406A - section B6.1.8 RFE Encoding A1"); |
|
1645 |
|
1646 // Decoding as per ARM ARM description |
|
1647 TUint32 P = (inst32 & 0x01000000) >> 24; |
|
1648 TUint32 U = (inst32 & 0x00800000) >> 23; |
|
1649 // TUint32 W = (inst32 & 0x00200000) >> 21; // not needed for this encoding |
|
1650 TUint32 Rn = (inst32 & 0x000F0000) >> 16; |
|
1651 |
|
1652 // TBool wback = (W == 1); // not needed for this encoding |
|
1653 TBool increment = (U == 1); |
|
1654 TBool wordhigher = (P == U); |
|
1655 |
|
1656 // Do calculation |
|
1657 if (Rn == 15) |
|
1658 { |
|
1659 // Unpredictable |
|
1660 LOG_MSG("ARM ARM DDI0406A - section B6.1.8 RFE Encoding A1 - Unpredictable"); |
|
1661 break; |
|
1662 } |
|
1663 |
|
1664 TUint32 RnVal = 0; |
|
1665 ReturnIfError(RegisterValue(aThread,Rn,RnVal)); |
|
1666 |
|
1667 TUint32 address = 0; |
|
1668 ReturnIfError(ReadMem32(aThread,RnVal,address)); |
|
1669 |
|
1670 if (increment) |
|
1671 { |
|
1672 address -= 8; |
|
1673 } |
|
1674 |
|
1675 if (wordhigher) |
|
1676 { |
|
1677 address += 4; |
|
1678 } |
|
1679 |
|
1680 breakAddress = address; |
|
1681 break; |
|
1682 } |
|
1683 } |
|
1684 |
|
1685 // v4T/v5T/v6T instructions |
|
1686 switch(thumb_opcode(inst)) |
|
1687 { |
|
1688 case 0x08: |
|
1689 { |
|
1690 // Data-processing. See ARM ARM DDI0406A, section A6-8, A6.2.2. |
|
1691 |
|
1692 if ((thumb_inst_7_15(inst) == 0x08F)) |
|
1693 { |
|
1694 // BLX(2) |
|
1695 err = iChannel->ReadKernelRegisterValue(aThread, ((inst & 0x0078) >> 3), breakAddress); |
|
1696 if(err != KErrNone) |
|
1697 { |
|
1698 LOG_MSG2("Non-zero error code discarded: %d", err); |
|
1699 } |
|
1700 |
|
1701 if ((breakAddress & 0x00000001) == 0) |
|
1702 { |
|
1703 aChangingModes = ETrue; |
|
1704 } |
|
1705 |
|
1706 breakAddress &= 0xFFFFFFFE; |
|
1707 |
|
1708 // Report how we decoded this instruction |
|
1709 LOG_MSG("DRMDStepping::PCAfterInstructionExecutes: Decoded as BLX (2)"); |
|
1710 } |
|
1711 else if (thumb_inst_7_15(inst) == 0x08E) |
|
1712 { |
|
1713 // BX |
|
1714 err = iChannel->ReadKernelRegisterValue(aThread, ((inst & 0x0078) >> 3), breakAddress); |
|
1715 if(err != KErrNone) |
|
1716 { |
|
1717 LOG_MSG2("Non-zero error code discarded: %d", err); |
|
1718 } |
|
1719 |
|
1720 if ((breakAddress & 0x00000001) == 0) |
|
1721 { |
|
1722 aChangingModes = ETrue; |
|
1723 } |
|
1724 |
|
1725 breakAddress &= 0xFFFFFFFE; |
|
1726 |
|
1727 // Report how we decoded this instruction |
|
1728 LOG_MSG("DRMDStepping::PCAfterInstructionExecutes: Decoded as BX"); |
|
1729 } |
|
1730 else if ((thumb_inst_8_15(inst) == 0x46) && ((inst & 0x87) == 0x87)) |
|
1731 { |
|
1732 // MOV with PC as the destination |
|
1733 err = iChannel->ReadKernelRegisterValue(aThread, ((inst & 0x0078) >> 3), breakAddress); |
|
1734 if(err != KErrNone) |
|
1735 { |
|
1736 LOG_MSG2("Non-zero error code discarded: %d", err); |
|
1737 } |
|
1738 |
|
1739 // Report how we decoded this instruction |
|
1740 LOG_MSG("DRMDStepping::PCAfterInstructionExecutes: Decoded as MOV with PC as the destination"); |
|
1741 } |
|
1742 else if ((thumb_inst_8_15(inst) == 0x44) && ((inst & 0x87) == 0x87)) |
|
1743 { |
|
1744 // ADD with PC as the destination |
|
1745 err = iChannel->ReadKernelRegisterValue(aThread, ((inst & 0x0078) >> 3), breakAddress); |
|
1746 if(err != KErrNone) |
|
1747 { |
|
1748 LOG_MSG2("Non-zero error code discarded: %d", err); |
|
1749 } |
|
1750 breakAddress += aCurrentPC + 4; // +4 because we need to use the PC+4 according to ARM ARM DDI0406A, section A6.1.2. |
|
1751 |
|
1752 // Report how we decoded this instruction |
|
1753 LOG_MSG("DRMDStepping::PCAfterInstructionExecutes: Decoded as ADD with PC as the destination"); |
|
1754 } |
|
1755 break; |
|
1756 } |
|
1757 case 0x13: |
|
1758 { |
|
1759 // Load/Store single data item. See ARM ARM DDI0406A, section A6-10 |
|
1760 |
|
1761 //This instruction doesn't modify the PC. |
|
1762 |
|
1763 //if (thumb_inst_8_15(inst) == 0x9F) |
|
1764 //{ |
|
1765 // LDR(4) with the PC as the destination |
|
1766 // breakAddress = ReadRegister(aThread, SP_REGISTER) + (4 * (inst & 0x00FF)); |
|
1767 //} |
|
1768 |
|
1769 // Report how we decoded this instruction |
|
1770 LOG_MSG("DRMDStepping::PCAfterInstructionExecutes: Decoded as This instruction doesn't modify the PC."); |
|
1771 break; |
|
1772 } |
|
1773 case 0x17: |
|
1774 { |
|
1775 // Misc 16-bit instruction. See ARM ARM DDI0406A, section A6-11 |
|
1776 |
|
1777 if (thumb_inst_8_15(inst) == 0xBD) |
|
1778 { |
|
1779 // POP with the PC in the list |
|
1780 TUint32 regList = (inst & 0x00FF); |
|
1781 TInt offset = 0; |
|
1782 err = iChannel->ReadKernelRegisterValue(aThread, SP_REGISTER, (T4ByteRegisterValue&)offset); |
|
1783 if(err != KErrNone) |
|
1784 { |
|
1785 LOG_MSG2("Non-zero error code discarded: %d", err); |
|
1786 } |
|
1787 offset += (BitCount(regList) * 4); |
|
1788 |
|
1789 TBuf8<4> destination; |
|
1790 err = iChannel->DoReadMemory(aThread, offset, 4, destination); |
|
1791 |
|
1792 if (KErrNone == err) |
|
1793 { |
|
1794 breakAddress = *(TUint32 *)destination.Ptr(); |
|
1795 |
|
1796 if ((breakAddress & 0x00000001) == 0) |
|
1797 { |
|
1798 aChangingModes = ETrue; |
|
1799 } |
|
1800 |
|
1801 breakAddress &= 0xFFFFFFFE; |
|
1802 } |
|
1803 else |
|
1804 { |
|
1805 LOG_MSG("Error reading memory in decoding step instruction"); |
|
1806 } |
|
1807 |
|
1808 // Report how we decoded this instruction |
|
1809 LOG_MSG("DRMDStepping::PCAfterInstructionExecutes: Decoded as POP with the PC in the list"); |
|
1810 } |
|
1811 break; |
|
1812 } |
|
1813 case 0x1A: |
|
1814 case 0x1B: |
|
1815 { |
|
1816 // Conditional branch, and supervisor call. See ARM ARM DDI0406A, section A6-13 |
|
1817 |
|
1818 if (thumb_inst_8_15(inst) < 0xDE) |
|
1819 { |
|
1820 // B(1) conditional branch |
|
1821 if (IsExecuted(((inst & 0x0F00) >> 8), aStatusRegister)) |
|
1822 { |
|
1823 TUint32 offset = ((inst & 0x000000FF) << 1); |
|
1824 if (offset & 0x00000100) |
|
1825 { |
|
1826 offset |= 0xFFFFFF00; |
|
1827 } |
|
1828 |
|
1829 breakAddress = aCurrentPC + 4 + offset; |
|
1830 |
|
1831 // Report how we decoded this instruction |
|
1832 LOG_MSG("DRMDStepping::PCAfterInstructionExecutes: Decoded as B(1) conditional branch"); |
|
1833 } |
|
1834 } |
|
1835 break; |
|
1836 } |
|
1837 case 0x1C: |
|
1838 { |
|
1839 // Unconditional branch, See ARM ARM DDI0406A, section A8-44. |
|
1840 |
|
1841 // B(2) unconditional branch |
|
1842 TUint32 offset = (inst & 0x000007FF) << 1; |
|
1843 if (offset & 0x00000800) |
|
1844 { |
|
1845 offset |= 0xFFFFF800; |
|
1846 } |
|
1847 |
|
1848 breakAddress = aCurrentPC + 4 + offset; |
|
1849 |
|
1850 // Report how we decoded this instruction |
|
1851 LOG_MSG("DRMDStepping::PCAfterInstructionExecutes: Decoded as B(2) unconditional branch"); |
|
1852 |
|
1853 break; |
|
1854 } |
|
1855 case 0x1D: |
|
1856 { |
|
1857 if (!(inst & 0x0001)) |
|
1858 { |
|
1859 // BLX(1) |
|
1860 err = iChannel->ReadKernelRegisterValue(aThread, LINK_REGISTER, breakAddress); |
|
1861 if(err != KErrNone) |
|
1862 { |
|
1863 LOG_MSG2("Non-zero error code discarded: %d", err); |
|
1864 } |
|
1865 breakAddress += ((inst & 0x07FF) << 1); |
|
1866 if ((breakAddress & 0x00000001) == 0) |
|
1867 { |
|
1868 aChangingModes = ETrue; |
|
1869 } |
|
1870 |
|
1871 breakAddress &= 0xFFFFFFFC; |
|
1872 |
|
1873 // Report how we decoded this instruction |
|
1874 LOG_MSG("DRMDStepping::PCAfterInstructionExecutes: Decoded as BLX(1)"); |
|
1875 |
|
1876 } |
|
1877 break; |
|
1878 } |
|
1879 case 0x1E: |
|
1880 { |
|
1881 // Check for ARMv7 CPU |
|
1882 if(cpuid == 0xC0) |
|
1883 { |
|
1884 // BL/BLX 32-bit instruction |
|
1885 aNewRangeEnd += 4; |
|
1886 |
|
1887 breakAddress = (TUint32)thumb_instr_b_dest(inst32, aCurrentPC); |
|
1888 |
|
1889 if((inst32 >> 27) == 0x1D) |
|
1890 { |
|
1891 // BLX(1) |
|
1892 if ((breakAddress & 0x00000001) == 0) |
|
1893 { |
|
1894 aChangingModes = ETrue; |
|
1895 } |
|
1896 |
|
1897 breakAddress &= 0xFFFFFFFC; |
|
1898 |
|
1899 // Report how we decoded this instruction |
|
1900 LOG_MSG("DRMDStepping::PCAfterInstructionExecutes: Decoded as 32-bit BLX(1)"); |
|
1901 } |
|
1902 else |
|
1903 { |
|
1904 // Report how we decoded this instruction |
|
1905 LOG_MSG("DRMDStepping::PCAfterInstructionExecutes: 32-bit BL instruction"); |
|
1906 } |
|
1907 LOG_MSG2(" 32-bit BL/BLX instruction: breakAddress = 0x%X", breakAddress); |
|
1908 } |
|
1909 else |
|
1910 { |
|
1911 // BL/BLX prefix - destination is encoded in this and the next instruction |
|
1912 aNewRangeEnd += 2; |
|
1913 |
|
1914 // Report how we decoded this instruction |
|
1915 LOG_MSG("DRMDStepping::PCAfterInstructionExecutes: BL/BLX prefix - destination is encoded in this and the next instruction"); |
|
1916 } |
|
1917 |
|
1918 |
|
1919 break; |
|
1920 } |
|
1921 case 0x1F: |
|
1922 { |
|
1923 { |
|
1924 // BL |
|
1925 err = iChannel->ReadKernelRegisterValue(aThread, LINK_REGISTER, breakAddress); |
|
1926 if(err != KErrNone) |
|
1927 { |
|
1928 LOG_MSG2("Non-zero error code discarded: %d", err); |
|
1929 } |
|
1930 breakAddress += ((inst & 0x07FF) << 1); |
|
1931 |
|
1932 // Report how we decoded this instruction |
|
1933 LOG_MSG("DRMDStepping::PCAfterInstructionExecutes: Decoded as BL"); |
|
1934 } |
|
1935 break; |
|
1936 } |
|
1937 default: |
|
1938 { |
|
1939 // Don't know any better at this point! |
|
1940 LOG_MSG("DRMDStepping::PCAfterInstructionExecutes:- default to next instruction"); |
|
1941 } |
|
1942 break; |
|
1943 } |
|
1944 } |
|
1945 break; |
|
1946 |
|
1947 case Debug::EThumb2EEMode: |
|
1948 { |
|
1949 // Not yet supported |
|
1950 LOG_MSG("DRMDStepping::PCAfterInstructionExecutes - Debug::EThumb2Mode is not supported"); |
|
1951 |
|
1952 } |
|
1953 break; |
|
1954 |
|
1955 default: |
|
1956 LOG_MSG("DRMDStepping::PCAfterInstructionExecutes - Cannot determine CPU mode architecture"); |
|
1957 } |
|
1958 |
|
1959 LOG_MSG2("DRMDStepping::PCAfterInstructionExecutes : return 0x%08x",breakAddress); |
|
1960 return breakAddress; |
|
1961 } |
|
1962 |
|
1963 // Obtain a 32-bit memory value with minimum fuss |
|
1964 TInt DDebuggerEventHandler::ReadMem32(DThread* aThread, const TUint32 aAddress, TUint32& aValue) |
|
1965 { |
|
1966 TBuf8<4> valBuf; |
|
1967 TInt err = iChannel->DoReadMemory(aThread, aAddress, 4, valBuf); |
|
1968 if (err != KErrNone) |
|
1969 { |
|
1970 LOG_MSG2("DRMDStepping::ReadMem32 failed to read memory at 0x%08x", aAddress); |
|
1971 return err; |
|
1972 } |
|
1973 |
|
1974 aValue = *(TUint32 *)valBuf.Ptr(); |
|
1975 |
|
1976 return KErrNone; |
|
1977 } |
|
1978 |
|
1979 // Obtain a 16-bit memory value with minimum fuss |
|
1980 TInt DDebuggerEventHandler::ReadMem16(DThread* aThread, const TUint32 aAddress, TUint16& aValue) |
|
1981 { |
|
1982 TBuf8<2> valBuf; |
|
1983 TInt err = iChannel->DoReadMemory(aThread, aAddress, 2, valBuf); |
|
1984 if (err != KErrNone) |
|
1985 { |
|
1986 LOG_MSG2("DRMDStepping::ReadMem16 failed to read memory at 0x%08x", aAddress); |
|
1987 return err; |
|
1988 } |
|
1989 |
|
1990 aValue = *(TUint16 *)valBuf.Ptr(); |
|
1991 |
|
1992 return KErrNone; |
|
1993 } |
|
1994 |
|
1995 /*TOMSCI |
|
1996 // Obtain a 16-bit memory value with minimum fuss |
|
1997 TInt DRMDStepping::ReadMem8(DThread* aThread, const TUint32 aAddress, TUint8& aValue) |
|
1998 { |
|
1999 TBuf8<1> valBuf; |
|
2000 TInt err = iChannel->DoReadMemory(aThread, aAddress, 1, valBuf); |
|
2001 if (err != KErrNone) |
|
2002 { |
|
2003 LOG_MSG2("DRMDStepping::ReadMem8 failed to read memory at 0x%08x", aAddress); |
|
2004 return err; |
|
2005 } |
|
2006 |
|
2007 aValue = *(TUint8 *)valBuf.Ptr(); |
|
2008 |
|
2009 return KErrNone; |
|
2010 } |
|
2011 END TOMSCI*/ |
|
2012 |
|
2013 // Obtain a core register value with minimum fuss |
|
2014 TInt DDebuggerEventHandler::RegisterValue(DThread *aThread, const TUint32 aKernelRegisterId, TUint32 &aValue) |
|
2015 { |
|
2016 TInt err = iChannel->ReadKernelRegisterValue(aThread, aKernelRegisterId, aValue); |
|
2017 if(err != KErrNone) |
|
2018 { |
|
2019 LOG_MSG3("DRMDStepping::RegisterValue failed to read register %d err = %d", aKernelRegisterId, err); |
|
2020 } |
|
2021 return err; |
|
2022 } |
|
2023 |
|
2024 |
|
2025 // Encodings from ARM ARM DDI0406A, section 9.2.1 |
|
2026 enum TThumb2EEOpcode |
|
2027 { |
|
2028 EThumb2HDP, // Handler Branch with Parameter |
|
2029 EThumb2UNDEF, // UNDEFINED |
|
2030 EThumb2HB, // Handler Branch, Handler Branch with Link |
|
2031 EThumb2HBLP, // Handle Branch with Link and Parameter |
|
2032 EThumb2LDRF, // Load Register from a frame |
|
2033 EThumb2CHKA, // Check Array |
|
2034 EThumb2LDRL, // Load Register from a literal pool |
|
2035 EThumb2LDRA, // Load Register (array operations) |
|
2036 EThumb2STR // Store Register to a frame |
|
2037 }; |
|
2038 |
|
2039 TUint32 DDebuggerEventHandler::ShiftedRegValue(DThread *aThread, TUint32 aInstruction, TUint32 aCurrentPC, TUint32 aStatusRegister) |
|
2040 { |
|
2041 LOG_MSG("DRM_DebugChannel::ShiftedRegValue()"); |
|
2042 |
|
2043 TUint32 shift = 0; |
|
2044 if (aInstruction & 0x10) // bit 4 |
|
2045 { |
|
2046 shift = (arm_rs(aInstruction) == PC_REGISTER ? aCurrentPC + 8 : aStatusRegister) & 0xFF; |
|
2047 } |
|
2048 else |
|
2049 { |
|
2050 shift = arm_data_c(aInstruction); |
|
2051 } |
|
2052 |
|
2053 TInt rm = arm_rm(aInstruction); |
|
2054 |
|
2055 TUint32 res = 0; |
|
2056 if(rm == PC_REGISTER) |
|
2057 { |
|
2058 res = aCurrentPC + ((aInstruction & 0x10) ? 12 : 8); |
|
2059 } |
|
2060 else |
|
2061 { |
|
2062 TInt err = iChannel->ReadKernelRegisterValue(aThread, rm, res); |
|
2063 if(err != KErrNone) |
|
2064 { |
|
2065 LOG_MSG2("DRMDStepping::ShiftedRegValue - Non-zero error code discarded: %d", err); |
|
2066 } |
|
2067 } |
|
2068 |
|
2069 switch(arm_data_shift(aInstruction)) |
|
2070 { |
|
2071 case 0: // LSL |
|
2072 { |
|
2073 res = shift >= 32 ? 0 : res << shift; |
|
2074 break; |
|
2075 } |
|
2076 case 1: // LSR |
|
2077 { |
|
2078 res = shift >= 32 ? 0 : res >> shift; |
|
2079 break; |
|
2080 } |
|
2081 case 2: // ASR |
|
2082 { |
|
2083 if (shift >= 32) |
|
2084 shift = 31; |
|
2085 res = ((res & 0x80000000L) ? ~((~res) >> shift) : res >> shift); |
|
2086 break; |
|
2087 } |
|
2088 case 3: // ROR/RRX |
|
2089 { |
|
2090 shift &= 31; |
|
2091 if (shift == 0) |
|
2092 { |
|
2093 res = (res >> 1) | ((aStatusRegister & arm_carry_bit()) ? 0x80000000L : 0); |
|
2094 } |
|
2095 else |
|
2096 { |
|
2097 res = (res >> shift) | (res << (32 - shift)); |
|
2098 } |
|
2099 break; |
|
2100 } |
|
2101 } |
|
2102 |
|
2103 return res & 0xFFFFFFFF; |
|
2104 } |
|
2105 |
|
2106 // |
|
2107 // DRMDStepping::CurrentPC |
|
2108 // |
|
2109 // |
|
2110 // |
|
2111 TInt DDebuggerEventHandler::CurrentPC(DThread* aThread, TUint32& aPC) |
|
2112 { |
|
2113 LOG_MSG("DRMDStepping::CurrentPC"); |
|
2114 |
|
2115 TInt err = iChannel->ReadKernelRegisterValue(aThread, PC_REGISTER, aPC); |
|
2116 if(err != KErrNone) |
|
2117 { |
|
2118 // We don't know the current PC for this thread! |
|
2119 LOG_MSG("DRMDStepping::CurrentPC - Failed to read the current PC"); |
|
2120 |
|
2121 return KErrGeneral; |
|
2122 } |
|
2123 |
|
2124 LOG_MSG2("DRMDStepping::CurrentPC 0x%08x", aPC); |
|
2125 |
|
2126 return KErrNone; |
|
2127 } |
|
2128 |
|
2129 TInt DDebuggerEventHandler::CurrentCPSR(DThread* aThread, TUint32& aCPSR) |
|
2130 { |
|
2131 LOG_MSG("DRMDStepping::CurrentCPSR"); |
|
2132 |
|
2133 TInt err = iChannel->ReadKernelRegisterValue(aThread, STATUS_REGISTER, aCPSR); |
|
2134 if(err != KErrNone) |
|
2135 { |
|
2136 // We don't know the current PC for this thread! |
|
2137 LOG_MSG("DRMDStepping::CurrentPC - Failed to read the current CPSR"); |
|
2138 |
|
2139 return KErrGeneral; |
|
2140 } |
|
2141 |
|
2142 LOG_MSG2("DRMDStepping::CurrentCPSR 0x%08x", aCPSR); |
|
2143 |
|
2144 return KErrNone; |
|
2145 } |