0
|
1 |
// Copyright (c) 1997-2009 Nokia Corporation and/or its subsidiary(-ies).
|
|
2 |
// All rights reserved.
|
|
3 |
// This component and the accompanying materials are made available
|
|
4 |
// under the terms of the License "Eclipse Public License v1.0"
|
|
5 |
// which accompanies this distribution, and is available
|
|
6 |
// at the URL "http://www.eclipse.org/legal/epl-v10.html".
|
|
7 |
//
|
|
8 |
// Initial Contributors:
|
|
9 |
// Nokia Corporation - initial contribution.
|
|
10 |
//
|
|
11 |
// Contributors:
|
|
12 |
//
|
|
13 |
// Description:
|
|
14 |
// e32test\mmu\d_shadow.h
|
|
15 |
//
|
|
16 |
//
|
|
17 |
|
|
18 |
#if !defined(__D_SHADOW_H__)
|
|
19 |
#define __D_SHADOW_H__
|
|
20 |
#include <e32cmn.h>
|
|
21 |
#ifndef __KERNEL_MODE__
|
|
22 |
#include <e32std.h>
|
|
23 |
#endif
|
|
24 |
|
|
25 |
|
|
26 |
enum TMemModel
|
|
27 |
{
|
|
28 |
EMemModelOther,
|
|
29 |
EMemModelMoving,
|
|
30 |
EMemModelMultiple,
|
|
31 |
EMemModelFlexible
|
|
32 |
};
|
|
33 |
|
|
34 |
enum TCpu
|
|
35 |
{
|
|
36 |
ECpuUnknown,
|
|
37 |
ECpuArm,
|
|
38 |
ECpuX86
|
|
39 |
};
|
|
40 |
|
|
41 |
|
|
42 |
class TCapsShadowV01
|
|
43 |
{
|
|
44 |
public:
|
|
45 |
TVersion iVersion;
|
|
46 |
};
|
|
47 |
|
|
48 |
const TUint KGlobalPageDirectory=0xFFFFFFFF;
|
|
49 |
const TUint KErrNoPageTable = 0x80000000;
|
|
50 |
const TUint KPageOffsetMask = 0x7FFFFFFF;
|
|
51 |
|
|
52 |
class RShadow : public RBusLogicalChannel
|
|
53 |
{
|
|
54 |
public:
|
|
55 |
enum TControl
|
|
56 |
{
|
|
57 |
EControlAllocShadow,
|
|
58 |
EControlFreeShadow,
|
|
59 |
EControlWriteShadow,
|
|
60 |
EControlFreezeShadow,
|
|
61 |
EControlSetPriority,
|
|
62 |
EControlRead,
|
|
63 |
EControlMmuId,
|
|
64 |
EControlCacheType,
|
|
65 |
EControlMeasureKernStackUse,
|
|
66 |
EControlMeasureKernHeapFree,
|
|
67 |
EControlWalkHeap,
|
|
68 |
EControlCallFunction,
|
|
69 |
EControlAllocPhys,
|
|
70 |
EControlFreePhys,
|
|
71 |
EControlClaimPhys,
|
|
72 |
EControlGetMemoryArchitecture,
|
|
73 |
EControlGetMemModelInfo,
|
|
74 |
EControlGetPdInfo
|
|
75 |
};
|
|
76 |
|
|
77 |
public:
|
|
78 |
inline TInt Open();
|
|
79 |
inline TInt Alloc(TUint anAddr); // allocate a shadow ROM page
|
|
80 |
inline TInt Free(TUint anAddr); // free a shadow ROM page
|
|
81 |
inline TInt Write(TUint anAddr, TAny* aSrc); // write to a shadow ROM page
|
|
82 |
inline TInt Freeze(TUint anAddr); // freeze a shadow ROM page
|
|
83 |
inline TInt SetPriority(TInt aHandle, TInt aPriority);
|
|
84 |
inline TUint Read(TUint aLinAddr);
|
|
85 |
inline TUint MmuId();
|
|
86 |
inline TUint CacheType();
|
|
87 |
inline TInt KernStackUsed();
|
|
88 |
inline TInt KernHeapFree();
|
|
89 |
inline void WalkHeap(TInt aThreadHandle);
|
|
90 |
inline TInt CallFunction(TThreadFunction aFunction, TAny* aPtr);
|
|
91 |
inline TInt AllocPhysicalRam(TUint32& aAddr, TInt aSize, TInt aAlign);
|
|
92 |
inline TInt FreePhysicalRam(TUint32 aAddr, TInt aSize);
|
|
93 |
inline TInt ClaimPhysicalRam(TUint32 aAddr, TInt aSize);
|
|
94 |
inline void GetMemoryArchitecture(TCpu &aCpu, TUint &aCR);
|
|
95 |
inline TMemModel GetMemModelInfo(TUint &aPageTable, TUint &aNumPds);
|
|
96 |
inline TInt GetPdInfo(TUint aPdNo, TUint &aPdSize, TUint &aPdBase, TUint &aOffset);
|
|
97 |
};
|
|
98 |
|
|
99 |
|
|
100 |
#ifndef __KERNEL_MODE__
|
|
101 |
inline TInt RShadow::Open()
|
|
102 |
{
|
|
103 |
return DoCreate(_L("Shadow"),TVersion(0,1,1),KNullUnit,NULL,NULL);
|
|
104 |
}
|
|
105 |
|
|
106 |
inline TInt RShadow::Alloc(TUint anAddr)
|
|
107 |
{ return DoControl(EControlAllocShadow,(TAny*)anAddr); }
|
|
108 |
|
|
109 |
inline TInt RShadow::Free(TUint anAddr)
|
|
110 |
{ return DoControl(EControlFreeShadow,(TAny*)anAddr); }
|
|
111 |
|
|
112 |
inline TInt RShadow::Write(TUint anAddr, TAny *aSrc)
|
|
113 |
{ return DoControl(EControlWriteShadow,(TAny*)anAddr,aSrc); }
|
|
114 |
|
|
115 |
inline TInt RShadow::Freeze(TUint anAddr)
|
|
116 |
{ return DoControl(EControlFreezeShadow,(TAny*)anAddr); }
|
|
117 |
|
|
118 |
inline TInt RShadow::SetPriority(TInt aHandle, TInt aPriority)
|
|
119 |
{ return DoControl(EControlSetPriority, (TAny*)aHandle, (TAny*)aPriority); }
|
|
120 |
|
|
121 |
inline TUint RShadow::Read(TUint aLinAddr)
|
|
122 |
{ return DoControl(EControlRead, (TAny*)aLinAddr); }
|
|
123 |
|
|
124 |
inline TUint RShadow::MmuId()
|
|
125 |
{ return DoControl(EControlMmuId); }
|
|
126 |
|
|
127 |
inline TUint RShadow::CacheType()
|
|
128 |
{ return DoControl(EControlCacheType); }
|
|
129 |
|
|
130 |
inline TInt RShadow::KernStackUsed()
|
|
131 |
{ return DoControl(EControlMeasureKernStackUse); }
|
|
132 |
|
|
133 |
inline TInt RShadow::KernHeapFree()
|
|
134 |
{ return DoControl(EControlMeasureKernHeapFree); }
|
|
135 |
|
|
136 |
inline void RShadow::WalkHeap(TInt aThreadHandle)
|
|
137 |
{ DoControl(EControlWalkHeap,(TAny*)aThreadHandle); }
|
|
138 |
|
|
139 |
inline TInt RShadow::CallFunction(TThreadFunction aFunction, TAny* aPtr)
|
|
140 |
{ return DoControl(EControlCallFunction, (TAny*)aFunction, aPtr); }
|
|
141 |
|
|
142 |
inline TInt RShadow::AllocPhysicalRam(TUint32& aAddr, TInt aSize, TInt aAlign)
|
|
143 |
{ TInt r=DoControl(EControlAllocPhys, (TAny*)aSize, (TAny*)aAlign); if (r>=0) aAddr=TUint32(r)<<4; return r<0?r:KErrNone; }
|
|
144 |
|
|
145 |
inline TInt RShadow::FreePhysicalRam(TUint32 aAddr, TInt aSize)
|
|
146 |
{ return DoControl(EControlFreePhys, (TAny*)aAddr, (TAny*)aSize); }
|
|
147 |
|
|
148 |
inline TInt RShadow::ClaimPhysicalRam(TUint32 aAddr, TInt aSize)
|
|
149 |
{ return DoControl(EControlClaimPhys, (TAny*)aAddr, (TAny*)aSize); }
|
|
150 |
|
|
151 |
inline void RShadow::GetMemoryArchitecture(TCpu &aCpu, TUint &aCR)
|
|
152 |
{ DoControl(EControlGetMemoryArchitecture, (TAny*) &aCpu, (TAny*) &aCR); }
|
|
153 |
|
|
154 |
inline TMemModel RShadow::GetMemModelInfo(TUint &aPageTable, TUint &aNumPds)
|
|
155 |
{ return (TMemModel) DoControl(EControlGetMemModelInfo,(TAny*) &aPageTable, (TAny*) &aNumPds); }
|
|
156 |
|
|
157 |
inline TInt RShadow::GetPdInfo(TUint aPdNo, TUint &aPdSize, TUint &aPdBase, TUint &aOffset)
|
|
158 |
{
|
|
159 |
aPdSize=aPdNo;
|
|
160 |
TUint ret= (TUint) DoControl(EControlGetPdInfo,(TAny*) &aPdSize, (TAny*) &aPdBase);
|
|
161 |
aOffset = ret & KPageOffsetMask;
|
|
162 |
return (ret & KErrNoPageTable)?KErrNotFound:KErrNone;
|
|
163 |
}
|
|
164 |
|
|
165 |
#endif
|
|
166 |
|
|
167 |
#endif
|