author | Mike Kinghan <mikek@symbian.org> |
Mon, 26 Jul 2010 13:44:21 +0100 | |
branch | GCC_SURGE |
changeset 232 | 9143fc12f708 |
parent 209 | 6035754ebf88 |
permissions | -rw-r--r-- |
0 | 1 |
// Copyright (c) 2006-2009 Nokia Corporation and/or its subsidiary(-ies). |
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// All rights reserved. |
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// This component and the accompanying materials are made available |
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// under the terms of the License "Eclipse Public License v1.0" |
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// which accompanies this distribution, and is available |
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// at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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// |
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// Initial Contributors: |
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// Nokia Corporation - initial contribution. |
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// |
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// Contributors: |
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// |
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// Description: |
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// f32test\demandpaging\t_pagestress.cia |
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// |
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// |
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#include <u32std.h> |
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#ifdef DEF_T_PAGESTRESS |
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#include "../t_pagestress.h" |
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#else |
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#include "t_pagestress.h" |
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#endif |
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#ifdef __VC32__ |
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#pragma warning(disable:4706) |
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#endif |
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//#if defined(_DEBUG) || defined(_DEBUG_RELEASE) |
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||
209
6035754ebf88
Fix for bug 3291 - [GCCE] armcc build equated with armv5 build in f32test
Mike Kinghan <mikek@symbian.org>
parents:
0
diff
changeset
|
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#if defined __EABI__ || defined __X86__ |
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#ifdef __X86__ |
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#ifdef __GCC32__ |
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#define ASM_NOP asm("nop"); |
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#define ASM_RET asm("mov eax, dword ptr [esp+4]"); \ |
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asm("add eax, dword ptr [esp+8]"); \ |
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asm("ret"); // do not use C 'return' or stack frame will be created |
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#else |
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#define ASM_NOP _asm nop |
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#define ASM_RET return aParam1 + aParam2; |
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#endif |
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#define ASM_NOP2 ASM_NOP ASM_NOP |
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#define ASM_NOP4 ASM_NOP2 ASM_NOP2 |
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#define ASM_NOP8 ASM_NOP4 ASM_NOP4 |
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#define ASM_NOP16 ASM_NOP8 ASM_NOP8 |
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#define ASM_NOP32 ASM_NOP16 ASM_NOP16 |
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#define ASM_NOP64 ASM_NOP32 ASM_NOP32 |
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#define ASM_NOP128 ASM_NOP64 ASM_NOP64 |
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#define ASM_NOP256 ASM_NOP128 ASM_NOP128 |
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#define ASM_NOP512 ASM_NOP256 ASM_NOP256 |
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#define ASM_NOP1024 ASM_NOP512 ASM_NOP512 |
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#define ASM_NOP2048 ASM_NOP1024 ASM_NOP1024 |
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#define ASM_NOP3072 ASM_NOP1024 ASM_NOP2048 |
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#define ASM_NOP3584 ASM_NOP3072 ASM_NOP512 |
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#define ASM_NOP3840 ASM_NOP3584 ASM_NOP256 |
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#define ASM_NOP3968 ASM_NOP3840 ASM_NOP128 |
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#define ASM_NOP4032 ASM_NOP3968 ASM_NOP64 |
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#define ASM_NOP4064 ASM_NOP4032 ASM_NOP32 |
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#define ASM_NOP4080 ASM_NOP4064 ASM_NOP8 |
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#define ASM_ALL ASM_NOP4080 |
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#undef __NAKED__ |
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#define __NAKED__ |
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#endif |
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||
209
6035754ebf88
Fix for bug 3291 - [GCCE] armcc build equated with armv5 build in f32test
Mike Kinghan <mikek@symbian.org>
parents:
0
diff
changeset
|
71 |
#if defined __EABI__ |
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#define ASM_OP1 asm("movs r2,r0"); |
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#define ASM_OP2 asm("adds r0,r2,r1"); |
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#define ASM_OP3 asm("bx lr"); |
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#define ASM_OP4 asm(".space 4084"); |
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#define ASM_ALL1 ASM_OP1 ASM_OP2 |
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#define ASM_ALL2 ASM_ALL1 ASM_OP3 |
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#define ASM_ALL ASM_ALL2 ASM_OP4 |
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#define ASM_RET |
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#endif |
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||
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__NAKED__ TInt TestAlignment0(TInt aParam1, TInt aParam2) |
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{ |
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ASM_ALL |
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ASM_RET |
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} |
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__NAKED__ TInt TestAlignment1(TInt aParam1, TInt aParam2) |
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{ |
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ASM_ALL |
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ASM_RET |
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} |
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__NAKED__ TInt TestAlignment2(TInt aParam1, TInt aParam2) |
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{ |
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ASM_ALL |
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ASM_RET |
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} |
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__NAKED__ TInt TestAlignment3(TInt aParam1, TInt aParam2) |
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{ |
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ASM_ALL |
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ASM_RET |
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} |
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__NAKED__ TInt TestAlignment4(TInt aParam1, TInt aParam2) |
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{ |
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ASM_ALL |
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ASM_RET |
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} |
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__NAKED__ TInt TestAlignment5(TInt aParam1, TInt aParam2) |
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{ |
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ASM_ALL |
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ASM_RET |
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} |
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__NAKED__ TInt TestAlignment6(TInt aParam1, TInt aParam2) |
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{ |
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ASM_ALL |
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ASM_RET |
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} |
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__NAKED__ TInt TestAlignment7(TInt aParam1, TInt aParam2) |
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{ |
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ASM_ALL |
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ASM_RET |
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} |
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__NAKED__ TInt TestAlignment8(TInt aParam1, TInt aParam2) |
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{ |
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ASM_ALL |
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ASM_RET |
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} |
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__NAKED__ TInt TestAlignment9(TInt aParam1, TInt aParam2) |
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{ |
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ASM_ALL |
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ASM_RET |
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} |
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__NAKED__ TInt TestAlignment10(TInt aParam1, TInt aParam2) |
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{ |
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ASM_ALL |
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ASM_RET |
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} |
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__NAKED__ TInt TestAlignment11(TInt aParam1, TInt aParam2) |
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{ |
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ASM_ALL |
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ASM_RET |
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} |
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__NAKED__ TInt TestAlignment12(TInt aParam1, TInt aParam2) |
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{ |
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ASM_ALL |
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ASM_RET |
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} |
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__NAKED__ TInt TestAlignment13(TInt aParam1, TInt aParam2) |
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{ |
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ASM_ALL |
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ASM_RET |
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} |
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__NAKED__ TInt TestAlignment14(TInt aParam1, TInt aParam2) |
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{ |
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ASM_ALL |
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ASM_RET |
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} |
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__NAKED__ TInt TestAlignment15(TInt aParam1, TInt aParam2) |
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{ |
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ASM_ALL |
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ASM_RET |
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} |
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__NAKED__ TInt TestAlignment16(TInt aParam1, TInt aParam2) |
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{ |
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ASM_ALL |
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ASM_RET |
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} |
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__NAKED__ TInt TestAlignment17(TInt aParam1, TInt aParam2) |
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{ |
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ASM_ALL |
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ASM_RET |
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} |
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__NAKED__ TInt TestAlignment18(TInt aParam1, TInt aParam2) |
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{ |
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ASM_ALL |
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ASM_RET |
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} |
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__NAKED__ TInt TestAlignment19(TInt aParam1, TInt aParam2) |
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{ |
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ASM_ALL |
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ASM_RET |
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} |
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__NAKED__ TInt TestAlignment20(TInt aParam1, TInt aParam2) |
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{ |
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ASM_ALL |
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ASM_RET |
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} |
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__NAKED__ TInt TestAlignment21(TInt aParam1, TInt aParam2) |
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{ |
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ASM_ALL |
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ASM_RET |
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} |
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__NAKED__ TInt TestAlignment22(TInt aParam1, TInt aParam2) |
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{ |
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ASM_ALL |
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ASM_RET |
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} |
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__NAKED__ TInt TestAlignment23(TInt aParam1, TInt aParam2) |
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{ |
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ASM_ALL |
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ASM_RET |
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} |
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__NAKED__ TInt TestAlignment24(TInt aParam1, TInt aParam2) |
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{ |
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ASM_ALL |
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ASM_RET |
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} |
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__NAKED__ TInt TestAlignment25(TInt aParam1, TInt aParam2) |
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{ |
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ASM_ALL |
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ASM_RET |
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} |
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__NAKED__ TInt TestAlignment26(TInt aParam1, TInt aParam2) |
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{ |
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ASM_ALL |
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ASM_RET |
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} |
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__NAKED__ TInt TestAlignment27(TInt aParam1, TInt aParam2) |
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{ |
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ASM_ALL |
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ASM_RET |
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} |
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__NAKED__ TInt TestAlignment28(TInt aParam1, TInt aParam2) |
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{ |
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ASM_ALL |
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ASM_RET |
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} |
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__NAKED__ TInt TestAlignment29(TInt aParam1, TInt aParam2) |
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{ |
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ASM_ALL |
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ASM_RET |
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} |
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__NAKED__ TInt TestAlignment30(TInt aParam1, TInt aParam2) |
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{ |
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ASM_ALL |
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ASM_RET |
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} |
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__NAKED__ TInt TestAlignment31(TInt aParam1, TInt aParam2) |
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{ |
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ASM_ALL |
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ASM_RET |
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} |
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__NAKED__ TInt TestAlignment32(TInt aParam1, TInt aParam2) |
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{ |
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ASM_ALL |
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ASM_RET |
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} |
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__NAKED__ TInt TestAlignment33(TInt aParam1, TInt aParam2) |
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{ |
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ASM_ALL |
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ASM_RET |
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} |
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__NAKED__ TInt TestAlignment34(TInt aParam1, TInt aParam2) |
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{ |
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ASM_ALL |
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ASM_RET |
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} |
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__NAKED__ TInt TestAlignment35(TInt aParam1, TInt aParam2) |
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{ |
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ASM_ALL |
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ASM_RET |
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} |
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__NAKED__ TInt TestAlignment36(TInt aParam1, TInt aParam2) |
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{ |
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ASM_ALL |
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ASM_RET |
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} |
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__NAKED__ TInt TestAlignment37(TInt aParam1, TInt aParam2) |
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{ |
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ASM_ALL |
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ASM_RET |
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} |
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__NAKED__ TInt TestAlignment38(TInt aParam1, TInt aParam2) |
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{ |
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ASM_ALL |
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ASM_RET |
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} |
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__NAKED__ TInt TestAlignment39(TInt aParam1, TInt aParam2) |
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{ |
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ASM_ALL |
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ASM_RET |
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} |
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__NAKED__ TInt TestAlignment40(TInt aParam1, TInt aParam2) |
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{ |
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ASM_ALL |
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ASM_RET |
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} |
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__NAKED__ TInt TestAlignment41(TInt aParam1, TInt aParam2) |
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{ |
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ASM_ALL |
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ASM_RET |
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} |
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__NAKED__ TInt TestAlignment42(TInt aParam1, TInt aParam2) |
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{ |
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ASM_ALL |
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ASM_RET |
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} |
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__NAKED__ TInt TestAlignment43(TInt aParam1, TInt aParam2) |
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{ |
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ASM_ALL |
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ASM_RET |
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} |
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__NAKED__ TInt TestAlignment44(TInt aParam1, TInt aParam2) |
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{ |
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ASM_ALL |
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ASM_RET |
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} |
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__NAKED__ TInt TestAlignment45(TInt aParam1, TInt aParam2) |
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{ |
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ASM_ALL |
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ASM_RET |
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} |
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__NAKED__ TInt TestAlignment46(TInt aParam1, TInt aParam2) |
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{ |
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ASM_ALL |
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ASM_RET |
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} |
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||
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__NAKED__ TInt TestAlignment47(TInt aParam1, TInt aParam2) |
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{ |
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ASM_ALL |
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ASM_RET |
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} |
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||
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__NAKED__ TInt TestAlignment48(TInt aParam1, TInt aParam2) |
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{ |
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ASM_ALL |
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ASM_RET |
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} |
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||
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__NAKED__ TInt TestAlignment49(TInt aParam1, TInt aParam2) |
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{ |
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ASM_ALL |
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ASM_RET |
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} |
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__NAKED__ TInt TestAlignment50(TInt aParam1, TInt aParam2) |
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{ |
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ASM_ALL |
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ASM_RET |
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} |
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387 |
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__NAKED__ TInt TestAlignment51(TInt aParam1, TInt aParam2) |
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{ |
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390 |
ASM_ALL |
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ASM_RET |
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} |
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393 |
||
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__NAKED__ TInt TestAlignment52(TInt aParam1, TInt aParam2) |
|
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{ |
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396 |
ASM_ALL |
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ASM_RET |
|
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} |
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399 |
||
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__NAKED__ TInt TestAlignment53(TInt aParam1, TInt aParam2) |
|
401 |
{ |
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402 |
ASM_ALL |
|
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ASM_RET |
|
404 |
} |
|
405 |
||
406 |
__NAKED__ TInt TestAlignment54(TInt aParam1, TInt aParam2) |
|
407 |
{ |
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408 |
ASM_ALL |
|
409 |
ASM_RET |
|
410 |
} |
|
411 |
||
412 |
__NAKED__ TInt TestAlignment55(TInt aParam1, TInt aParam2) |
|
413 |
{ |
|
414 |
ASM_ALL |
|
415 |
ASM_RET |
|
416 |
} |
|
417 |
||
418 |
__NAKED__ TInt TestAlignment56(TInt aParam1, TInt aParam2) |
|
419 |
{ |
|
420 |
ASM_ALL |
|
421 |
ASM_RET |
|
422 |
} |
|
423 |
||
424 |
__NAKED__ TInt TestAlignment57(TInt aParam1, TInt aParam2) |
|
425 |
{ |
|
426 |
ASM_ALL |
|
427 |
ASM_RET |
|
428 |
} |
|
429 |
||
430 |
__NAKED__ TInt TestAlignment58(TInt aParam1, TInt aParam2) |
|
431 |
{ |
|
432 |
ASM_ALL |
|
433 |
ASM_RET |
|
434 |
} |
|
435 |
||
436 |
__NAKED__ TInt TestAlignment59(TInt aParam1, TInt aParam2) |
|
437 |
{ |
|
438 |
ASM_ALL |
|
439 |
ASM_RET |
|
440 |
} |
|
441 |
||
442 |
__NAKED__ TInt TestAlignment60(TInt aParam1, TInt aParam2) |
|
443 |
{ |
|
444 |
ASM_ALL |
|
445 |
ASM_RET |
|
446 |
} |
|
447 |
||
448 |
||
449 |
__NAKED__ TInt TestAlignment61(TInt aParam1, TInt aParam2) |
|
450 |
{ |
|
451 |
ASM_ALL |
|
452 |
ASM_RET |
|
453 |
} |
|
454 |
||
455 |
||
456 |
__NAKED__ TInt TestAlignment62(TInt aParam1, TInt aParam2) |
|
457 |
{ |
|
458 |
ASM_ALL |
|
459 |
ASM_RET |
|
460 |
} |
|
461 |
||
462 |
__NAKED__ TInt TestAlignment63(TInt aParam1, TInt aParam2) |
|
463 |
{ |
|
464 |
ASM_ALL |
|
465 |
ASM_RET |
|
466 |
} |
|
467 |
||
468 |
#ifdef T_PAGESTRESS_LARGE_ARRAY |
|
469 |
__NAKED__ TInt TestAlignment64(TInt aParam1, TInt aParam2) |
|
470 |
{ |
|
471 |
ASM_ALL |
|
472 |
ASM_RET |
|
473 |
} |
|
474 |
||
475 |
__NAKED__ TInt TestAlignment65(TInt aParam1, TInt aParam2) |
|
476 |
{ |
|
477 |
ASM_ALL |
|
478 |
ASM_RET |
|
479 |
} |
|
480 |
||
481 |
__NAKED__ TInt TestAlignment66(TInt aParam1, TInt aParam2) |
|
482 |
{ |
|
483 |
ASM_ALL |
|
484 |
ASM_RET |
|
485 |
} |
|
486 |
||
487 |
__NAKED__ TInt TestAlignment67(TInt aParam1, TInt aParam2) |
|
488 |
{ |
|
489 |
ASM_ALL |
|
490 |
ASM_RET |
|
491 |
} |
|
492 |
||
493 |
__NAKED__ TInt TestAlignment68(TInt aParam1, TInt aParam2) |
|
494 |
{ |
|
495 |
ASM_ALL |
|
496 |
ASM_RET |
|
497 |
} |
|
498 |
||
499 |
__NAKED__ TInt TestAlignment69(TInt aParam1, TInt aParam2) |
|
500 |
{ |
|
501 |
ASM_ALL |
|
502 |
ASM_RET |
|
503 |
} |
|
504 |
||
505 |
__NAKED__ TInt TestAlignment70(TInt aParam1, TInt aParam2) |
|
506 |
{ |
|
507 |
ASM_ALL |
|
508 |
ASM_RET |
|
509 |
} |
|
510 |
||
511 |
__NAKED__ TInt TestAlignment71(TInt aParam1, TInt aParam2) |
|
512 |
{ |
|
513 |
ASM_ALL |
|
514 |
ASM_RET |
|
515 |
} |
|
516 |
||
517 |
__NAKED__ TInt TestAlignment72(TInt aParam1, TInt aParam2) |
|
518 |
{ |
|
519 |
ASM_ALL |
|
520 |
ASM_RET |
|
521 |
} |
|
522 |
||
523 |
__NAKED__ TInt TestAlignment73(TInt aParam1, TInt aParam2) |
|
524 |
{ |
|
525 |
ASM_ALL |
|
526 |
ASM_RET |
|
527 |
} |
|
528 |
||
529 |
__NAKED__ TInt TestAlignment74(TInt aParam1, TInt aParam2) |
|
530 |
{ |
|
531 |
ASM_ALL |
|
532 |
ASM_RET |
|
533 |
} |
|
534 |
||
535 |
__NAKED__ TInt TestAlignment75(TInt aParam1, TInt aParam2) |
|
536 |
{ |
|
537 |
ASM_ALL |
|
538 |
ASM_RET |
|
539 |
} |
|
540 |
||
541 |
__NAKED__ TInt TestAlignment76(TInt aParam1, TInt aParam2) |
|
542 |
{ |
|
543 |
ASM_ALL |
|
544 |
ASM_RET |
|
545 |
} |
|
546 |
||
547 |
__NAKED__ TInt TestAlignment77(TInt aParam1, TInt aParam2) |
|
548 |
{ |
|
549 |
ASM_ALL |
|
550 |
ASM_RET |
|
551 |
} |
|
552 |
||
553 |
__NAKED__ TInt TestAlignment78(TInt aParam1, TInt aParam2) |
|
554 |
{ |
|
555 |
ASM_ALL |
|
556 |
ASM_RET |
|
557 |
} |
|
558 |
||
559 |
__NAKED__ TInt TestAlignment79(TInt aParam1, TInt aParam2) |
|
560 |
{ |
|
561 |
ASM_ALL |
|
562 |
ASM_RET |
|
563 |
} |
|
564 |
||
565 |
__NAKED__ TInt TestAlignment80(TInt aParam1, TInt aParam2) |
|
566 |
{ |
|
567 |
ASM_ALL |
|
568 |
ASM_RET |
|
569 |
} |
|
570 |
||
571 |
__NAKED__ TInt TestAlignment81(TInt aParam1, TInt aParam2) |
|
572 |
{ |
|
573 |
ASM_ALL |
|
574 |
ASM_RET |
|
575 |
} |
|
576 |
||
577 |
__NAKED__ TInt TestAlignment82(TInt aParam1, TInt aParam2) |
|
578 |
{ |
|
579 |
ASM_ALL |
|
580 |
ASM_RET |
|
581 |
} |
|
582 |
||
583 |
__NAKED__ TInt TestAlignment83(TInt aParam1, TInt aParam2) |
|
584 |
{ |
|
585 |
ASM_ALL |
|
586 |
ASM_RET |
|
587 |
} |
|
588 |
||
589 |
__NAKED__ TInt TestAlignment84(TInt aParam1, TInt aParam2) |
|
590 |
{ |
|
591 |
ASM_ALL |
|
592 |
ASM_RET |
|
593 |
} |
|
594 |
||
595 |
__NAKED__ TInt TestAlignment85(TInt aParam1, TInt aParam2) |
|
596 |
{ |
|
597 |
ASM_ALL |
|
598 |
ASM_RET |
|
599 |
} |
|
600 |
||
601 |
__NAKED__ TInt TestAlignment86(TInt aParam1, TInt aParam2) |
|
602 |
{ |
|
603 |
ASM_ALL |
|
604 |
ASM_RET |
|
605 |
} |
|
606 |
||
607 |
__NAKED__ TInt TestAlignment87(TInt aParam1, TInt aParam2) |
|
608 |
{ |
|
609 |
ASM_ALL |
|
610 |
ASM_RET |
|
611 |
} |
|
612 |
||
613 |
__NAKED__ TInt TestAlignment88(TInt aParam1, TInt aParam2) |
|
614 |
{ |
|
615 |
ASM_ALL |
|
616 |
ASM_RET |
|
617 |
} |
|
618 |
||
619 |
__NAKED__ TInt TestAlignment89(TInt aParam1, TInt aParam2) |
|
620 |
{ |
|
621 |
ASM_ALL |
|
622 |
ASM_RET |
|
623 |
} |
|
624 |
||
625 |
__NAKED__ TInt TestAlignment90(TInt aParam1, TInt aParam2) |
|
626 |
{ |
|
627 |
ASM_ALL |
|
628 |
ASM_RET |
|
629 |
} |
|
630 |
||
631 |
__NAKED__ TInt TestAlignment91(TInt aParam1, TInt aParam2) |
|
632 |
{ |
|
633 |
ASM_ALL |
|
634 |
ASM_RET |
|
635 |
} |
|
636 |
||
637 |
__NAKED__ TInt TestAlignment92(TInt aParam1, TInt aParam2) |
|
638 |
{ |
|
639 |
ASM_ALL |
|
640 |
ASM_RET |
|
641 |
} |
|
642 |
||
643 |
__NAKED__ TInt TestAlignment93(TInt aParam1, TInt aParam2) |
|
644 |
{ |
|
645 |
ASM_ALL |
|
646 |
ASM_RET |
|
647 |
} |
|
648 |
||
649 |
__NAKED__ TInt TestAlignment94(TInt aParam1, TInt aParam2) |
|
650 |
{ |
|
651 |
ASM_ALL |
|
652 |
ASM_RET |
|
653 |
} |
|
654 |
||
655 |
__NAKED__ TInt TestAlignment95(TInt aParam1, TInt aParam2) |
|
656 |
{ |
|
657 |
ASM_ALL |
|
658 |
ASM_RET |
|
659 |
} |
|
660 |
||
661 |
__NAKED__ TInt TestAlignment96(TInt aParam1, TInt aParam2) |
|
662 |
{ |
|
663 |
ASM_ALL |
|
664 |
ASM_RET |
|
665 |
} |
|
666 |
||
667 |
__NAKED__ TInt TestAlignment97(TInt aParam1, TInt aParam2) |
|
668 |
{ |
|
669 |
ASM_ALL |
|
670 |
ASM_RET |
|
671 |
} |
|
672 |
||
673 |
__NAKED__ TInt TestAlignment98(TInt aParam1, TInt aParam2) |
|
674 |
{ |
|
675 |
ASM_ALL |
|
676 |
ASM_RET |
|
677 |
} |
|
678 |
||
679 |
__NAKED__ TInt TestAlignment99(TInt aParam1, TInt aParam2) |
|
680 |
{ |
|
681 |
ASM_ALL |
|
682 |
ASM_RET |
|
683 |
} |
|
684 |
||
685 |
__NAKED__ TInt TestAlignment100(TInt aParam1, TInt aParam2) |
|
686 |
{ |
|
687 |
ASM_ALL |
|
688 |
ASM_RET |
|
689 |
} |
|
690 |
||
691 |
__NAKED__ TInt TestAlignment101(TInt aParam1, TInt aParam2) |
|
692 |
{ |
|
693 |
ASM_ALL |
|
694 |
ASM_RET |
|
695 |
} |
|
696 |
||
697 |
__NAKED__ TInt TestAlignment102(TInt aParam1, TInt aParam2) |
|
698 |
{ |
|
699 |
ASM_ALL |
|
700 |
ASM_RET |
|
701 |
} |
|
702 |
||
703 |
__NAKED__ TInt TestAlignment103(TInt aParam1, TInt aParam2) |
|
704 |
{ |
|
705 |
ASM_ALL |
|
706 |
ASM_RET |
|
707 |
} |
|
708 |
||
709 |
__NAKED__ TInt TestAlignment104(TInt aParam1, TInt aParam2) |
|
710 |
{ |
|
711 |
ASM_ALL |
|
712 |
ASM_RET |
|
713 |
} |
|
714 |
||
715 |
__NAKED__ TInt TestAlignment105(TInt aParam1, TInt aParam2) |
|
716 |
{ |
|
717 |
ASM_ALL |
|
718 |
ASM_RET |
|
719 |
} |
|
720 |
||
721 |
__NAKED__ TInt TestAlignment106(TInt aParam1, TInt aParam2) |
|
722 |
{ |
|
723 |
ASM_ALL |
|
724 |
ASM_RET |
|
725 |
} |
|
726 |
||
727 |
__NAKED__ TInt TestAlignment107(TInt aParam1, TInt aParam2) |
|
728 |
{ |
|
729 |
ASM_ALL |
|
730 |
ASM_RET |
|
731 |
} |
|
732 |
||
733 |
__NAKED__ TInt TestAlignment108(TInt aParam1, TInt aParam2) |
|
734 |
{ |
|
735 |
ASM_ALL |
|
736 |
ASM_RET |
|
737 |
} |
|
738 |
||
739 |
__NAKED__ TInt TestAlignment109(TInt aParam1, TInt aParam2) |
|
740 |
{ |
|
741 |
ASM_ALL |
|
742 |
ASM_RET |
|
743 |
} |
|
744 |
||
745 |
__NAKED__ TInt TestAlignment110(TInt aParam1, TInt aParam2) |
|
746 |
{ |
|
747 |
ASM_ALL |
|
748 |
ASM_RET |
|
749 |
} |
|
750 |
||
751 |
__NAKED__ TInt TestAlignment111(TInt aParam1, TInt aParam2) |
|
752 |
{ |
|
753 |
ASM_ALL |
|
754 |
ASM_RET |
|
755 |
} |
|
756 |
||
757 |
__NAKED__ TInt TestAlignment112(TInt aParam1, TInt aParam2) |
|
758 |
{ |
|
759 |
ASM_ALL |
|
760 |
ASM_RET |
|
761 |
} |
|
762 |
||
763 |
__NAKED__ TInt TestAlignment113(TInt aParam1, TInt aParam2) |
|
764 |
{ |
|
765 |
ASM_ALL |
|
766 |
ASM_RET |
|
767 |
} |
|
768 |
||
769 |
__NAKED__ TInt TestAlignment114(TInt aParam1, TInt aParam2) |
|
770 |
{ |
|
771 |
ASM_ALL |
|
772 |
ASM_RET |
|
773 |
} |
|
774 |
||
775 |
__NAKED__ TInt TestAlignment115(TInt aParam1, TInt aParam2) |
|
776 |
{ |
|
777 |
ASM_ALL |
|
778 |
ASM_RET |
|
779 |
} |
|
780 |
||
781 |
__NAKED__ TInt TestAlignment116(TInt aParam1, TInt aParam2) |
|
782 |
{ |
|
783 |
ASM_ALL |
|
784 |
ASM_RET |
|
785 |
} |
|
786 |
||
787 |
__NAKED__ TInt TestAlignment117(TInt aParam1, TInt aParam2) |
|
788 |
{ |
|
789 |
ASM_ALL |
|
790 |
ASM_RET |
|
791 |
} |
|
792 |
||
793 |
__NAKED__ TInt TestAlignment118(TInt aParam1, TInt aParam2) |
|
794 |
{ |
|
795 |
ASM_ALL |
|
796 |
ASM_RET |
|
797 |
} |
|
798 |
||
799 |
__NAKED__ TInt TestAlignment119(TInt aParam1, TInt aParam2) |
|
800 |
{ |
|
801 |
ASM_ALL |
|
802 |
ASM_RET |
|
803 |
} |
|
804 |
||
805 |
__NAKED__ TInt TestAlignment120(TInt aParam1, TInt aParam2) |
|
806 |
{ |
|
807 |
ASM_ALL |
|
808 |
ASM_RET |
|
809 |
} |
|
810 |
||
811 |
__NAKED__ TInt TestAlignment121(TInt aParam1, TInt aParam2) |
|
812 |
{ |
|
813 |
ASM_ALL |
|
814 |
ASM_RET |
|
815 |
} |
|
816 |
||
817 |
__NAKED__ TInt TestAlignment122(TInt aParam1, TInt aParam2) |
|
818 |
{ |
|
819 |
ASM_ALL |
|
820 |
ASM_RET |
|
821 |
} |
|
822 |
||
823 |
__NAKED__ TInt TestAlignment123(TInt aParam1, TInt aParam2) |
|
824 |
{ |
|
825 |
ASM_ALL |
|
826 |
ASM_RET |
|
827 |
} |
|
828 |
||
829 |
__NAKED__ TInt TestAlignment124(TInt aParam1, TInt aParam2) |
|
830 |
{ |
|
831 |
ASM_ALL |
|
832 |
ASM_RET |
|
833 |
} |
|
834 |
||
835 |
__NAKED__ TInt TestAlignment125(TInt aParam1, TInt aParam2) |
|
836 |
{ |
|
837 |
ASM_ALL |
|
838 |
ASM_RET |
|
839 |
} |
|
840 |
||
841 |
__NAKED__ TInt TestAlignment126(TInt aParam1, TInt aParam2) |
|
842 |
{ |
|
843 |
ASM_ALL |
|
844 |
ASM_RET |
|
845 |
} |
|
846 |
||
847 |
__NAKED__ TInt TestAlignment127(TInt aParam1, TInt aParam2) |
|
848 |
{ |
|
849 |
ASM_ALL |
|
850 |
ASM_RET |
|
851 |
} |
|
852 |
||
853 |
__NAKED__ TInt TestAlignment128(TInt aParam1, TInt aParam2) |
|
854 |
{ |
|
855 |
ASM_ALL |
|
856 |
ASM_RET |
|
857 |
} |
|
858 |
||
859 |
__NAKED__ TInt TestAlignment129(TInt aParam1, TInt aParam2) |
|
860 |
{ |
|
861 |
ASM_ALL |
|
862 |
ASM_RET |
|
863 |
} |
|
864 |
||
865 |
__NAKED__ TInt TestAlignment130(TInt aParam1, TInt aParam2) |
|
866 |
{ |
|
867 |
ASM_ALL |
|
868 |
ASM_RET |
|
869 |
} |
|
870 |
||
871 |
__NAKED__ TInt TestAlignment131(TInt aParam1, TInt aParam2) |
|
872 |
{ |
|
873 |
ASM_ALL |
|
874 |
ASM_RET |
|
875 |
} |
|
876 |
||
877 |
__NAKED__ TInt TestAlignment132(TInt aParam1, TInt aParam2) |
|
878 |
{ |
|
879 |
ASM_ALL |
|
880 |
ASM_RET |
|
881 |
} |
|
882 |
||
883 |
__NAKED__ TInt TestAlignment133(TInt aParam1, TInt aParam2) |
|
884 |
{ |
|
885 |
ASM_ALL |
|
886 |
ASM_RET |
|
887 |
} |
|
888 |
||
889 |
__NAKED__ TInt TestAlignment134(TInt aParam1, TInt aParam2) |
|
890 |
{ |
|
891 |
ASM_ALL |
|
892 |
ASM_RET |
|
893 |
} |
|
894 |
||
895 |
__NAKED__ TInt TestAlignment135(TInt aParam1, TInt aParam2) |
|
896 |
{ |
|
897 |
ASM_ALL |
|
898 |
ASM_RET |
|
899 |
} |
|
900 |
||
901 |
__NAKED__ TInt TestAlignment136(TInt aParam1, TInt aParam2) |
|
902 |
{ |
|
903 |
ASM_ALL |
|
904 |
ASM_RET |
|
905 |
} |
|
906 |
||
907 |
__NAKED__ TInt TestAlignment137(TInt aParam1, TInt aParam2) |
|
908 |
{ |
|
909 |
ASM_ALL |
|
910 |
ASM_RET |
|
911 |
} |
|
912 |
||
913 |
__NAKED__ TInt TestAlignment138(TInt aParam1, TInt aParam2) |
|
914 |
{ |
|
915 |
ASM_ALL |
|
916 |
ASM_RET |
|
917 |
} |
|
918 |
||
919 |
__NAKED__ TInt TestAlignment139(TInt aParam1, TInt aParam2) |
|
920 |
{ |
|
921 |
ASM_ALL |
|
922 |
ASM_RET |
|
923 |
} |
|
924 |
||
925 |
__NAKED__ TInt TestAlignment140(TInt aParam1, TInt aParam2) |
|
926 |
{ |
|
927 |
ASM_ALL |
|
928 |
ASM_RET |
|
929 |
} |
|
930 |
||
931 |
__NAKED__ TInt TestAlignment141(TInt aParam1, TInt aParam2) |
|
932 |
{ |
|
933 |
ASM_ALL |
|
934 |
ASM_RET |
|
935 |
} |
|
936 |
||
937 |
__NAKED__ TInt TestAlignment142(TInt aParam1, TInt aParam2) |
|
938 |
{ |
|
939 |
ASM_ALL |
|
940 |
ASM_RET |
|
941 |
} |
|
942 |
||
943 |
__NAKED__ TInt TestAlignment143(TInt aParam1, TInt aParam2) |
|
944 |
{ |
|
945 |
ASM_ALL |
|
946 |
ASM_RET |
|
947 |
} |
|
948 |
||
949 |
__NAKED__ TInt TestAlignment144(TInt aParam1, TInt aParam2) |
|
950 |
{ |
|
951 |
ASM_ALL |
|
952 |
ASM_RET |
|
953 |
} |
|
954 |
||
955 |
__NAKED__ TInt TestAlignment145(TInt aParam1, TInt aParam2) |
|
956 |
{ |
|
957 |
ASM_ALL |
|
958 |
ASM_RET |
|
959 |
} |
|
960 |
||
961 |
__NAKED__ TInt TestAlignment146(TInt aParam1, TInt aParam2) |
|
962 |
{ |
|
963 |
ASM_ALL |
|
964 |
ASM_RET |
|
965 |
} |
|
966 |
||
967 |
__NAKED__ TInt TestAlignment147(TInt aParam1, TInt aParam2) |
|
968 |
{ |
|
969 |
ASM_ALL |
|
970 |
ASM_RET |
|
971 |
} |
|
972 |
||
973 |
__NAKED__ TInt TestAlignment148(TInt aParam1, TInt aParam2) |
|
974 |
{ |
|
975 |
ASM_ALL |
|
976 |
ASM_RET |
|
977 |
} |
|
978 |
||
979 |
__NAKED__ TInt TestAlignment149(TInt aParam1, TInt aParam2) |
|
980 |
{ |
|
981 |
ASM_ALL |
|
982 |
ASM_RET |
|
983 |
} |
|
984 |
||
985 |
__NAKED__ TInt TestAlignment150(TInt aParam1, TInt aParam2) |
|
986 |
{ |
|
987 |
ASM_ALL |
|
988 |
ASM_RET |
|
989 |
} |
|
990 |
||
991 |
__NAKED__ TInt TestAlignment151(TInt aParam1, TInt aParam2) |
|
992 |
{ |
|
993 |
ASM_ALL |
|
994 |
ASM_RET |
|
995 |
} |
|
996 |
||
997 |
__NAKED__ TInt TestAlignment152(TInt aParam1, TInt aParam2) |
|
998 |
{ |
|
999 |
ASM_ALL |
|
1000 |
ASM_RET |
|
1001 |
} |
|
1002 |
||
1003 |
__NAKED__ TInt TestAlignment153(TInt aParam1, TInt aParam2) |
|
1004 |
{ |
|
1005 |
ASM_ALL |
|
1006 |
ASM_RET |
|
1007 |
} |
|
1008 |
||
1009 |
__NAKED__ TInt TestAlignment154(TInt aParam1, TInt aParam2) |
|
1010 |
{ |
|
1011 |
ASM_ALL |
|
1012 |
ASM_RET |
|
1013 |
} |
|
1014 |
||
1015 |
__NAKED__ TInt TestAlignment155(TInt aParam1, TInt aParam2) |
|
1016 |
{ |
|
1017 |
ASM_ALL |
|
1018 |
ASM_RET |
|
1019 |
} |
|
1020 |
||
1021 |
__NAKED__ TInt TestAlignment156(TInt aParam1, TInt aParam2) |
|
1022 |
{ |
|
1023 |
ASM_ALL |
|
1024 |
ASM_RET |
|
1025 |
} |
|
1026 |
||
1027 |
__NAKED__ TInt TestAlignment157(TInt aParam1, TInt aParam2) |
|
1028 |
{ |
|
1029 |
ASM_ALL |
|
1030 |
ASM_RET |
|
1031 |
} |
|
1032 |
||
1033 |
__NAKED__ TInt TestAlignment158(TInt aParam1, TInt aParam2) |
|
1034 |
{ |
|
1035 |
ASM_ALL |
|
1036 |
ASM_RET |
|
1037 |
} |
|
1038 |
||
1039 |
__NAKED__ TInt TestAlignment159(TInt aParam1, TInt aParam2) |
|
1040 |
{ |
|
1041 |
ASM_ALL |
|
1042 |
ASM_RET |
|
1043 |
} |
|
1044 |
||
1045 |
__NAKED__ TInt TestAlignment160(TInt aParam1, TInt aParam2) |
|
1046 |
{ |
|
1047 |
ASM_ALL |
|
1048 |
ASM_RET |
|
1049 |
} |
|
1050 |
||
1051 |
__NAKED__ TInt TestAlignment161(TInt aParam1, TInt aParam2) |
|
1052 |
{ |
|
1053 |
ASM_ALL |
|
1054 |
ASM_RET |
|
1055 |
} |
|
1056 |
||
1057 |
__NAKED__ TInt TestAlignment162(TInt aParam1, TInt aParam2) |
|
1058 |
{ |
|
1059 |
ASM_ALL |
|
1060 |
ASM_RET |
|
1061 |
} |
|
1062 |
||
1063 |
__NAKED__ TInt TestAlignment163(TInt aParam1, TInt aParam2) |
|
1064 |
{ |
|
1065 |
ASM_ALL |
|
1066 |
ASM_RET |
|
1067 |
} |
|
1068 |
||
1069 |
__NAKED__ TInt TestAlignment164(TInt aParam1, TInt aParam2) |
|
1070 |
{ |
|
1071 |
ASM_ALL |
|
1072 |
ASM_RET |
|
1073 |
} |
|
1074 |
||
1075 |
__NAKED__ TInt TestAlignment165(TInt aParam1, TInt aParam2) |
|
1076 |
{ |
|
1077 |
ASM_ALL |
|
1078 |
ASM_RET |
|
1079 |
} |
|
1080 |
||
1081 |
__NAKED__ TInt TestAlignment166(TInt aParam1, TInt aParam2) |
|
1082 |
{ |
|
1083 |
ASM_ALL |
|
1084 |
ASM_RET |
|
1085 |
} |
|
1086 |
||
1087 |
__NAKED__ TInt TestAlignment167(TInt aParam1, TInt aParam2) |
|
1088 |
{ |
|
1089 |
ASM_ALL |
|
1090 |
ASM_RET |
|
1091 |
} |
|
1092 |
||
1093 |
__NAKED__ TInt TestAlignment168(TInt aParam1, TInt aParam2) |
|
1094 |
{ |
|
1095 |
ASM_ALL |
|
1096 |
ASM_RET |
|
1097 |
} |
|
1098 |
||
1099 |
__NAKED__ TInt TestAlignment169(TInt aParam1, TInt aParam2) |
|
1100 |
{ |
|
1101 |
ASM_ALL |
|
1102 |
ASM_RET |
|
1103 |
} |
|
1104 |
||
1105 |
__NAKED__ TInt TestAlignment170(TInt aParam1, TInt aParam2) |
|
1106 |
{ |
|
1107 |
ASM_ALL |
|
1108 |
ASM_RET |
|
1109 |
} |
|
1110 |
||
1111 |
__NAKED__ TInt TestAlignment171(TInt aParam1, TInt aParam2) |
|
1112 |
{ |
|
1113 |
ASM_ALL |
|
1114 |
ASM_RET |
|
1115 |
} |
|
1116 |
||
1117 |
__NAKED__ TInt TestAlignment172(TInt aParam1, TInt aParam2) |
|
1118 |
{ |
|
1119 |
ASM_ALL |
|
1120 |
ASM_RET |
|
1121 |
} |
|
1122 |
||
1123 |
__NAKED__ TInt TestAlignment173(TInt aParam1, TInt aParam2) |
|
1124 |
{ |
|
1125 |
ASM_ALL |
|
1126 |
ASM_RET |
|
1127 |
} |
|
1128 |
||
1129 |
__NAKED__ TInt TestAlignment174(TInt aParam1, TInt aParam2) |
|
1130 |
{ |
|
1131 |
ASM_ALL |
|
1132 |
ASM_RET |
|
1133 |
} |
|
1134 |
||
1135 |
__NAKED__ TInt TestAlignment175(TInt aParam1, TInt aParam2) |
|
1136 |
{ |
|
1137 |
ASM_ALL |
|
1138 |
ASM_RET |
|
1139 |
} |
|
1140 |
||
1141 |
__NAKED__ TInt TestAlignment176(TInt aParam1, TInt aParam2) |
|
1142 |
{ |
|
1143 |
ASM_ALL |
|
1144 |
ASM_RET |
|
1145 |
} |
|
1146 |
||
1147 |
__NAKED__ TInt TestAlignment177(TInt aParam1, TInt aParam2) |
|
1148 |
{ |
|
1149 |
ASM_ALL |
|
1150 |
ASM_RET |
|
1151 |
} |
|
1152 |
||
1153 |
__NAKED__ TInt TestAlignment178(TInt aParam1, TInt aParam2) |
|
1154 |
{ |
|
1155 |
ASM_ALL |
|
1156 |
ASM_RET |
|
1157 |
} |
|
1158 |
||
1159 |
__NAKED__ TInt TestAlignment179(TInt aParam1, TInt aParam2) |
|
1160 |
{ |
|
1161 |
ASM_ALL |
|
1162 |
ASM_RET |
|
1163 |
} |
|
1164 |
||
1165 |
__NAKED__ TInt TestAlignment180(TInt aParam1, TInt aParam2) |
|
1166 |
{ |
|
1167 |
ASM_ALL |
|
1168 |
ASM_RET |
|
1169 |
} |
|
1170 |
||
1171 |
__NAKED__ TInt TestAlignment181(TInt aParam1, TInt aParam2) |
|
1172 |
{ |
|
1173 |
ASM_ALL |
|
1174 |
ASM_RET |
|
1175 |
} |
|
1176 |
||
1177 |
__NAKED__ TInt TestAlignment182(TInt aParam1, TInt aParam2) |
|
1178 |
{ |
|
1179 |
ASM_ALL |
|
1180 |
ASM_RET |
|
1181 |
} |
|
1182 |
||
1183 |
__NAKED__ TInt TestAlignment183(TInt aParam1, TInt aParam2) |
|
1184 |
{ |
|
1185 |
ASM_ALL |
|
1186 |
ASM_RET |
|
1187 |
} |
|
1188 |
||
1189 |
__NAKED__ TInt TestAlignment184(TInt aParam1, TInt aParam2) |
|
1190 |
{ |
|
1191 |
ASM_ALL |
|
1192 |
ASM_RET |
|
1193 |
} |
|
1194 |
||
1195 |
__NAKED__ TInt TestAlignment185(TInt aParam1, TInt aParam2) |
|
1196 |
{ |
|
1197 |
ASM_ALL |
|
1198 |
ASM_RET |
|
1199 |
} |
|
1200 |
||
1201 |
__NAKED__ TInt TestAlignment186(TInt aParam1, TInt aParam2) |
|
1202 |
{ |
|
1203 |
ASM_ALL |
|
1204 |
ASM_RET |
|
1205 |
} |
|
1206 |
||
1207 |
__NAKED__ TInt TestAlignment187(TInt aParam1, TInt aParam2) |
|
1208 |
{ |
|
1209 |
ASM_ALL |
|
1210 |
ASM_RET |
|
1211 |
} |
|
1212 |
||
1213 |
__NAKED__ TInt TestAlignment188(TInt aParam1, TInt aParam2) |
|
1214 |
{ |
|
1215 |
ASM_ALL |
|
1216 |
ASM_RET |
|
1217 |
} |
|
1218 |
||
1219 |
__NAKED__ TInt TestAlignment189(TInt aParam1, TInt aParam2) |
|
1220 |
{ |
|
1221 |
ASM_ALL |
|
1222 |
ASM_RET |
|
1223 |
} |
|
1224 |
||
1225 |
__NAKED__ TInt TestAlignment190(TInt aParam1, TInt aParam2) |
|
1226 |
{ |
|
1227 |
ASM_ALL |
|
1228 |
ASM_RET |
|
1229 |
} |
|
1230 |
||
1231 |
__NAKED__ TInt TestAlignment191(TInt aParam1, TInt aParam2) |
|
1232 |
{ |
|
1233 |
ASM_ALL |
|
1234 |
ASM_RET |
|
1235 |
} |
|
1236 |
||
1237 |
__NAKED__ TInt TestAlignment192(TInt aParam1, TInt aParam2) |
|
1238 |
{ |
|
1239 |
ASM_ALL |
|
1240 |
ASM_RET |
|
1241 |
} |
|
1242 |
||
1243 |
__NAKED__ TInt TestAlignment193(TInt aParam1, TInt aParam2) |
|
1244 |
{ |
|
1245 |
ASM_ALL |
|
1246 |
ASM_RET |
|
1247 |
} |
|
1248 |
||
1249 |
__NAKED__ TInt TestAlignment194(TInt aParam1, TInt aParam2) |
|
1250 |
{ |
|
1251 |
ASM_ALL |
|
1252 |
ASM_RET |
|
1253 |
} |
|
1254 |
||
1255 |
__NAKED__ TInt TestAlignment195(TInt aParam1, TInt aParam2) |
|
1256 |
{ |
|
1257 |
ASM_ALL |
|
1258 |
ASM_RET |
|
1259 |
} |
|
1260 |
||
1261 |
__NAKED__ TInt TestAlignment196(TInt aParam1, TInt aParam2) |
|
1262 |
{ |
|
1263 |
ASM_ALL |
|
1264 |
ASM_RET |
|
1265 |
} |
|
1266 |
||
1267 |
__NAKED__ TInt TestAlignment197(TInt aParam1, TInt aParam2) |
|
1268 |
{ |
|
1269 |
ASM_ALL |
|
1270 |
ASM_RET |
|
1271 |
} |
|
1272 |
||
1273 |
__NAKED__ TInt TestAlignment198(TInt aParam1, TInt aParam2) |
|
1274 |
{ |
|
1275 |
ASM_ALL |
|
1276 |
ASM_RET |
|
1277 |
} |
|
1278 |
||
1279 |
__NAKED__ TInt TestAlignment199(TInt aParam1, TInt aParam2) |
|
1280 |
{ |
|
1281 |
ASM_ALL |
|
1282 |
ASM_RET |
|
1283 |
} |
|
1284 |
||
1285 |
__NAKED__ TInt TestAlignment200(TInt aParam1, TInt aParam2) |
|
1286 |
{ |
|
1287 |
ASM_ALL |
|
1288 |
ASM_RET |
|
1289 |
} |
|
1290 |
||
1291 |
__NAKED__ TInt TestAlignment201(TInt aParam1, TInt aParam2) |
|
1292 |
{ |
|
1293 |
ASM_ALL |
|
1294 |
ASM_RET |
|
1295 |
} |
|
1296 |
||
1297 |
__NAKED__ TInt TestAlignment202(TInt aParam1, TInt aParam2) |
|
1298 |
{ |
|
1299 |
ASM_ALL |
|
1300 |
ASM_RET |
|
1301 |
} |
|
1302 |
||
1303 |
__NAKED__ TInt TestAlignment203(TInt aParam1, TInt aParam2) |
|
1304 |
{ |
|
1305 |
ASM_ALL |
|
1306 |
ASM_RET |
|
1307 |
} |
|
1308 |
||
1309 |
__NAKED__ TInt TestAlignment204(TInt aParam1, TInt aParam2) |
|
1310 |
{ |
|
1311 |
ASM_ALL |
|
1312 |
ASM_RET |
|
1313 |
} |
|
1314 |
||
1315 |
__NAKED__ TInt TestAlignment205(TInt aParam1, TInt aParam2) |
|
1316 |
{ |
|
1317 |
ASM_ALL |
|
1318 |
ASM_RET |
|
1319 |
} |
|
1320 |
||
1321 |
__NAKED__ TInt TestAlignment206(TInt aParam1, TInt aParam2) |
|
1322 |
{ |
|
1323 |
ASM_ALL |
|
1324 |
ASM_RET |
|
1325 |
} |
|
1326 |
||
1327 |
__NAKED__ TInt TestAlignment207(TInt aParam1, TInt aParam2) |
|
1328 |
{ |
|
1329 |
ASM_ALL |
|
1330 |
ASM_RET |
|
1331 |
} |
|
1332 |
||
1333 |
__NAKED__ TInt TestAlignment208(TInt aParam1, TInt aParam2) |
|
1334 |
{ |
|
1335 |
ASM_ALL |
|
1336 |
ASM_RET |
|
1337 |
} |
|
1338 |
||
1339 |
__NAKED__ TInt TestAlignment209(TInt aParam1, TInt aParam2) |
|
1340 |
{ |
|
1341 |
ASM_ALL |
|
1342 |
ASM_RET |
|
1343 |
} |
|
1344 |
||
1345 |
__NAKED__ TInt TestAlignment210(TInt aParam1, TInt aParam2) |
|
1346 |
{ |
|
1347 |
ASM_ALL |
|
1348 |
ASM_RET |
|
1349 |
} |
|
1350 |
||
1351 |
__NAKED__ TInt TestAlignment211(TInt aParam1, TInt aParam2) |
|
1352 |
{ |
|
1353 |
ASM_ALL |
|
1354 |
ASM_RET |
|
1355 |
} |
|
1356 |
||
1357 |
__NAKED__ TInt TestAlignment212(TInt aParam1, TInt aParam2) |
|
1358 |
{ |
|
1359 |
ASM_ALL |
|
1360 |
ASM_RET |
|
1361 |
} |
|
1362 |
||
1363 |
__NAKED__ TInt TestAlignment213(TInt aParam1, TInt aParam2) |
|
1364 |
{ |
|
1365 |
ASM_ALL |
|
1366 |
ASM_RET |
|
1367 |
} |
|
1368 |
||
1369 |
__NAKED__ TInt TestAlignment214(TInt aParam1, TInt aParam2) |
|
1370 |
{ |
|
1371 |
ASM_ALL |
|
1372 |
ASM_RET |
|
1373 |
} |
|
1374 |
||
1375 |
__NAKED__ TInt TestAlignment215(TInt aParam1, TInt aParam2) |
|
1376 |
{ |
|
1377 |
ASM_ALL |
|
1378 |
ASM_RET |
|
1379 |
} |
|
1380 |
||
1381 |
__NAKED__ TInt TestAlignment216(TInt aParam1, TInt aParam2) |
|
1382 |
{ |
|
1383 |
ASM_ALL |
|
1384 |
ASM_RET |
|
1385 |
} |
|
1386 |
||
1387 |
__NAKED__ TInt TestAlignment217(TInt aParam1, TInt aParam2) |
|
1388 |
{ |
|
1389 |
ASM_ALL |
|
1390 |
ASM_RET |
|
1391 |
} |
|
1392 |
||
1393 |
__NAKED__ TInt TestAlignment218(TInt aParam1, TInt aParam2) |
|
1394 |
{ |
|
1395 |
ASM_ALL |
|
1396 |
ASM_RET |
|
1397 |
} |
|
1398 |
||
1399 |
__NAKED__ TInt TestAlignment219(TInt aParam1, TInt aParam2) |
|
1400 |
{ |
|
1401 |
ASM_ALL |
|
1402 |
ASM_RET |
|
1403 |
} |
|
1404 |
||
1405 |
__NAKED__ TInt TestAlignment220(TInt aParam1, TInt aParam2) |
|
1406 |
{ |
|
1407 |
ASM_ALL |
|
1408 |
ASM_RET |
|
1409 |
} |
|
1410 |
||
1411 |
__NAKED__ TInt TestAlignment221(TInt aParam1, TInt aParam2) |
|
1412 |
{ |
|
1413 |
ASM_ALL |
|
1414 |
ASM_RET |
|
1415 |
} |
|
1416 |
||
1417 |
__NAKED__ TInt TestAlignment222(TInt aParam1, TInt aParam2) |
|
1418 |
{ |
|
1419 |
ASM_ALL |
|
1420 |
ASM_RET |
|
1421 |
} |
|
1422 |
||
1423 |
__NAKED__ TInt TestAlignment223(TInt aParam1, TInt aParam2) |
|
1424 |
{ |
|
1425 |
ASM_ALL |
|
1426 |
ASM_RET |
|
1427 |
} |
|
1428 |
||
1429 |
__NAKED__ TInt TestAlignment224(TInt aParam1, TInt aParam2) |
|
1430 |
{ |
|
1431 |
ASM_ALL |
|
1432 |
ASM_RET |
|
1433 |
} |
|
1434 |
||
1435 |
__NAKED__ TInt TestAlignment225(TInt aParam1, TInt aParam2) |
|
1436 |
{ |
|
1437 |
ASM_ALL |
|
1438 |
ASM_RET |
|
1439 |
} |
|
1440 |
||
1441 |
__NAKED__ TInt TestAlignment226(TInt aParam1, TInt aParam2) |
|
1442 |
{ |
|
1443 |
ASM_ALL |
|
1444 |
ASM_RET |
|
1445 |
} |
|
1446 |
||
1447 |
__NAKED__ TInt TestAlignment227(TInt aParam1, TInt aParam2) |
|
1448 |
{ |
|
1449 |
ASM_ALL |
|
1450 |
ASM_RET |
|
1451 |
} |
|
1452 |
||
1453 |
__NAKED__ TInt TestAlignment228(TInt aParam1, TInt aParam2) |
|
1454 |
{ |
|
1455 |
ASM_ALL |
|
1456 |
ASM_RET |
|
1457 |
} |
|
1458 |
||
1459 |
__NAKED__ TInt TestAlignment229(TInt aParam1, TInt aParam2) |
|
1460 |
{ |
|
1461 |
ASM_ALL |
|
1462 |
ASM_RET |
|
1463 |
} |
|
1464 |
||
1465 |
__NAKED__ TInt TestAlignment230(TInt aParam1, TInt aParam2) |
|
1466 |
{ |
|
1467 |
ASM_ALL |
|
1468 |
ASM_RET |
|
1469 |
} |
|
1470 |
||
1471 |
__NAKED__ TInt TestAlignment231(TInt aParam1, TInt aParam2) |
|
1472 |
{ |
|
1473 |
ASM_ALL |
|
1474 |
ASM_RET |
|
1475 |
} |
|
1476 |
||
1477 |
__NAKED__ TInt TestAlignment232(TInt aParam1, TInt aParam2) |
|
1478 |
{ |
|
1479 |
ASM_ALL |
|
1480 |
ASM_RET |
|
1481 |
} |
|
1482 |
||
1483 |
__NAKED__ TInt TestAlignment233(TInt aParam1, TInt aParam2) |
|
1484 |
{ |
|
1485 |
ASM_ALL |
|
1486 |
ASM_RET |
|
1487 |
} |
|
1488 |
||
1489 |
__NAKED__ TInt TestAlignment234(TInt aParam1, TInt aParam2) |
|
1490 |
{ |
|
1491 |
ASM_ALL |
|
1492 |
ASM_RET |
|
1493 |
} |
|
1494 |
||
1495 |
__NAKED__ TInt TestAlignment235(TInt aParam1, TInt aParam2) |
|
1496 |
{ |
|
1497 |
ASM_ALL |
|
1498 |
ASM_RET |
|
1499 |
} |
|
1500 |
||
1501 |
__NAKED__ TInt TestAlignment236(TInt aParam1, TInt aParam2) |
|
1502 |
{ |
|
1503 |
ASM_ALL |
|
1504 |
ASM_RET |
|
1505 |
} |
|
1506 |
||
1507 |
__NAKED__ TInt TestAlignment237(TInt aParam1, TInt aParam2) |
|
1508 |
{ |
|
1509 |
ASM_ALL |
|
1510 |
ASM_RET |
|
1511 |
} |
|
1512 |
||
1513 |
__NAKED__ TInt TestAlignment238(TInt aParam1, TInt aParam2) |
|
1514 |
{ |
|
1515 |
ASM_ALL |
|
1516 |
ASM_RET |
|
1517 |
} |
|
1518 |
||
1519 |
__NAKED__ TInt TestAlignment239(TInt aParam1, TInt aParam2) |
|
1520 |
{ |
|
1521 |
ASM_ALL |
|
1522 |
ASM_RET |
|
1523 |
} |
|
1524 |
||
1525 |
__NAKED__ TInt TestAlignment240(TInt aParam1, TInt aParam2) |
|
1526 |
{ |
|
1527 |
ASM_ALL |
|
1528 |
ASM_RET |
|
1529 |
} |
|
1530 |
||
1531 |
__NAKED__ TInt TestAlignment241(TInt aParam1, TInt aParam2) |
|
1532 |
{ |
|
1533 |
ASM_ALL |
|
1534 |
ASM_RET |
|
1535 |
} |
|
1536 |
||
1537 |
__NAKED__ TInt TestAlignment242(TInt aParam1, TInt aParam2) |
|
1538 |
{ |
|
1539 |
ASM_ALL |
|
1540 |
ASM_RET |
|
1541 |
} |
|
1542 |
||
1543 |
__NAKED__ TInt TestAlignment243(TInt aParam1, TInt aParam2) |
|
1544 |
{ |
|
1545 |
ASM_ALL |
|
1546 |
ASM_RET |
|
1547 |
} |
|
1548 |
||
1549 |
__NAKED__ TInt TestAlignment244(TInt aParam1, TInt aParam2) |
|
1550 |
{ |
|
1551 |
ASM_ALL |
|
1552 |
ASM_RET |
|
1553 |
} |
|
1554 |
||
1555 |
__NAKED__ TInt TestAlignment245(TInt aParam1, TInt aParam2) |
|
1556 |
{ |
|
1557 |
ASM_ALL |
|
1558 |
ASM_RET |
|
1559 |
} |
|
1560 |
||
1561 |
__NAKED__ TInt TestAlignment246(TInt aParam1, TInt aParam2) |
|
1562 |
{ |
|
1563 |
ASM_ALL |
|
1564 |
ASM_RET |
|
1565 |
} |
|
1566 |
||
1567 |
__NAKED__ TInt TestAlignment247(TInt aParam1, TInt aParam2) |
|
1568 |
{ |
|
1569 |
ASM_ALL |
|
1570 |
ASM_RET |
|
1571 |
} |
|
1572 |
||
1573 |
__NAKED__ TInt TestAlignment248(TInt aParam1, TInt aParam2) |
|
1574 |
{ |
|
1575 |
ASM_ALL |
|
1576 |
ASM_RET |
|
1577 |
} |
|
1578 |
||
1579 |
__NAKED__ TInt TestAlignment249(TInt aParam1, TInt aParam2) |
|
1580 |
{ |
|
1581 |
ASM_ALL |
|
1582 |
ASM_RET |
|
1583 |
} |
|
1584 |
||
1585 |
__NAKED__ TInt TestAlignment250(TInt aParam1, TInt aParam2) |
|
1586 |
{ |
|
1587 |
ASM_ALL |
|
1588 |
ASM_RET |
|
1589 |
} |
|
1590 |
||
1591 |
__NAKED__ TInt TestAlignment251(TInt aParam1, TInt aParam2) |
|
1592 |
{ |
|
1593 |
ASM_ALL |
|
1594 |
ASM_RET |
|
1595 |
} |
|
1596 |
||
1597 |
__NAKED__ TInt TestAlignment252(TInt aParam1, TInt aParam2) |
|
1598 |
{ |
|
1599 |
ASM_ALL |
|
1600 |
ASM_RET |
|
1601 |
} |
|
1602 |
||
1603 |
__NAKED__ TInt TestAlignment253(TInt aParam1, TInt aParam2) |
|
1604 |
{ |
|
1605 |
ASM_ALL |
|
1606 |
ASM_RET |
|
1607 |
} |
|
1608 |
||
1609 |
__NAKED__ TInt TestAlignment254(TInt aParam1, TInt aParam2) |
|
1610 |
{ |
|
1611 |
ASM_ALL |
|
1612 |
ASM_RET |
|
1613 |
} |
|
1614 |
||
1615 |
__NAKED__ TInt TestAlignment255(TInt aParam1, TInt aParam2) |
|
1616 |
{ |
|
1617 |
ASM_ALL |
|
1618 |
ASM_RET |
|
1619 |
} |
|
1620 |
||
1621 |
#define DUMMY_ARRAY_SIZE 4096 |
|
1622 |
TInt dummyArray[DUMMY_ARRAY_SIZE]; // 4 pages, probably spanning 5 pages? |
|
1623 |
||
1624 |
__NAKED__ TInt DoLdmia(TInt *aAddress) |
|
1625 |
{ |
|
1626 |
#ifdef __X86__ |
|
1627 |
return 0; |
|
1628 |
#else |
|
1629 |
asm("ldmia r0, {r0,r1}"); |
|
1630 |
asm("bx lr"); |
|
1631 |
#endif |
|
1632 |
} |
|
1633 |
||
1634 |
__NAKED__ TInt TestAlignmentxXXx(TInt aParam1) |
|
1635 |
{ |
|
209
6035754ebf88
Fix for bug 3291 - [GCCE] armcc build equated with armv5 build in f32test
Mike Kinghan <mikek@symbian.org>
parents:
0
diff
changeset
|
1636 |
#if defined(__X86__) |
0 | 1637 |
return 0; |
209
6035754ebf88
Fix for bug 3291 - [GCCE] armcc build equated with armv5 build in f32test
Mike Kinghan <mikek@symbian.org>
parents:
0
diff
changeset
|
1638 |
#elif defined(__ARMCC__) |
0 | 1639 |
space 4096 |
1640 |
BX lr |
|
1641 |
ENDP |
|
209
6035754ebf88
Fix for bug 3291 - [GCCE] armcc build equated with armv5 build in f32test
Mike Kinghan <mikek@symbian.org>
parents:
0
diff
changeset
|
1642 |
#elif defined(__GCCE__) |
6035754ebf88
Fix for bug 3291 - [GCCE] armcc build equated with armv5 build in f32test
Mike Kinghan <mikek@symbian.org>
parents:
0
diff
changeset
|
1643 |
asm(".fill 4096"); |
6035754ebf88
Fix for bug 3291 - [GCCE] armcc build equated with armv5 build in f32test
Mike Kinghan <mikek@symbian.org>
parents:
0
diff
changeset
|
1644 |
asm("bx lr"); |
6035754ebf88
Fix for bug 3291 - [GCCE] armcc build equated with armv5 build in f32test
Mike Kinghan <mikek@symbian.org>
parents:
0
diff
changeset
|
1645 |
#else |
6035754ebf88
Fix for bug 3291 - [GCCE] armcc build equated with armv5 build in f32test
Mike Kinghan <mikek@symbian.org>
parents:
0
diff
changeset
|
1646 |
#error What compiler? |
0 | 1647 |
#endif |
1648 |
} |
|
1649 |
||
1650 |
TInt *CheckLdmiaInstr(void) |
|
1651 |
{ |
|
1652 |
TInt *pIntArray; |
|
1653 |
TInt offset = ((TInt)dummyArray) % 4096; |
|
1654 |
||
1655 |
if (offset == 0) |
|
1656 |
{ |
|
1657 |
pIntArray = (TInt *)(((TInt)dummyArray) + 4092); |
|
1658 |
} |
|
1659 |
else |
|
1660 |
{ |
|
1661 |
pIntArray = (TInt *)(((TInt)dummyArray) + (4092 - offset)); |
|
1662 |
} |
|
1663 |
DoLdmia(pIntArray); |
|
1664 |
return pIntArray; |
|
1665 |
} |
|
1666 |
||
1667 |
#endif //T_PAGESTRESS_LARGE_ARRAY |
|
1668 |
||
1669 |
#else |
|
1670 |
||
1671 |
#define TPS_DECLARE(_num) \ |
|
1672 |
TInt TestAlignment##_num(TInt aParam1, TInt aParam2)\ |
|
1673 |
{\ |
|
1674 |
return aParam1 + aParam2;\ |
|
1675 |
} |
|
1676 |
||
1677 |
TPS_DECLARE(0) |
|
1678 |
TPS_DECLARE(1) |
|
1679 |
TPS_DECLARE(2) |
|
1680 |
TPS_DECLARE(3) |
|
1681 |
TPS_DECLARE(4) |
|
1682 |
TPS_DECLARE(5) |
|
1683 |
TPS_DECLARE(6) |
|
1684 |
TPS_DECLARE(7) |
|
1685 |
TPS_DECLARE(8) |
|
1686 |
TPS_DECLARE(9) |
|
1687 |
TPS_DECLARE(10) |
|
1688 |
TPS_DECLARE(11) |
|
1689 |
TPS_DECLARE(12) |
|
1690 |
TPS_DECLARE(13) |
|
1691 |
TPS_DECLARE(14) |
|
1692 |
TPS_DECLARE(15) |
|
1693 |
TPS_DECLARE(16) |
|
1694 |
TPS_DECLARE(17) |
|
1695 |
TPS_DECLARE(18) |
|
1696 |
TPS_DECLARE(19) |
|
1697 |
TPS_DECLARE(20) |
|
1698 |
TPS_DECLARE(21) |
|
1699 |
TPS_DECLARE(22) |
|
1700 |
TPS_DECLARE(23) |
|
1701 |
TPS_DECLARE(24) |
|
1702 |
TPS_DECLARE(25) |
|
1703 |
TPS_DECLARE(26) |
|
1704 |
TPS_DECLARE(27) |
|
1705 |
TPS_DECLARE(28) |
|
1706 |
TPS_DECLARE(29) |
|
1707 |
TPS_DECLARE(30) |
|
1708 |
TPS_DECLARE(31) |
|
1709 |
TPS_DECLARE(32) |
|
1710 |
TPS_DECLARE(33) |
|
1711 |
TPS_DECLARE(34) |
|
1712 |
TPS_DECLARE(35) |
|
1713 |
TPS_DECLARE(36) |
|
1714 |
TPS_DECLARE(37) |
|
1715 |
TPS_DECLARE(38) |
|
1716 |
TPS_DECLARE(39) |
|
1717 |
TPS_DECLARE(40) |
|
1718 |
TPS_DECLARE(41) |
|
1719 |
TPS_DECLARE(42) |
|
1720 |
TPS_DECLARE(43) |
|
1721 |
TPS_DECLARE(44) |
|
1722 |
TPS_DECLARE(45) |
|
1723 |
TPS_DECLARE(46) |
|
1724 |
TPS_DECLARE(47) |
|
1725 |
TPS_DECLARE(48) |
|
1726 |
TPS_DECLARE(49) |
|
1727 |
TPS_DECLARE(50) |
|
1728 |
TPS_DECLARE(51) |
|
1729 |
TPS_DECLARE(52) |
|
1730 |
TPS_DECLARE(53) |
|
1731 |
TPS_DECLARE(54) |
|
1732 |
TPS_DECLARE(55) |
|
1733 |
TPS_DECLARE(56) |
|
1734 |
TPS_DECLARE(57) |
|
1735 |
TPS_DECLARE(58) |
|
1736 |
TPS_DECLARE(59) |
|
1737 |
TPS_DECLARE(60) |
|
1738 |
TPS_DECLARE(61) |
|
1739 |
TPS_DECLARE(62) |
|
1740 |
TPS_DECLARE(63) |
|
1741 |
#ifdef T_PAGESTRESS_LARGE_ARRAY |
|
1742 |
TPS_DECLARE(64) |
|
1743 |
TPS_DECLARE(65) |
|
1744 |
TPS_DECLARE(66) |
|
1745 |
TPS_DECLARE(67) |
|
1746 |
TPS_DECLARE(68) |
|
1747 |
TPS_DECLARE(69) |
|
1748 |
TPS_DECLARE(70) |
|
1749 |
TPS_DECLARE(71) |
|
1750 |
TPS_DECLARE(72) |
|
1751 |
TPS_DECLARE(73) |
|
1752 |
TPS_DECLARE(74) |
|
1753 |
TPS_DECLARE(75) |
|
1754 |
TPS_DECLARE(76) |
|
1755 |
TPS_DECLARE(77) |
|
1756 |
TPS_DECLARE(78) |
|
1757 |
TPS_DECLARE(79) |
|
1758 |
TPS_DECLARE(80) |
|
1759 |
TPS_DECLARE(81) |
|
1760 |
TPS_DECLARE(82) |
|
1761 |
TPS_DECLARE(83) |
|
1762 |
TPS_DECLARE(84) |
|
1763 |
TPS_DECLARE(85) |
|
1764 |
TPS_DECLARE(86) |
|
1765 |
TPS_DECLARE(87) |
|
1766 |
TPS_DECLARE(88) |
|
1767 |
TPS_DECLARE(89) |
|
1768 |
TPS_DECLARE(90) |
|
1769 |
TPS_DECLARE(91) |
|
1770 |
TPS_DECLARE(92) |
|
1771 |
TPS_DECLARE(93) |
|
1772 |
TPS_DECLARE(94) |
|
1773 |
TPS_DECLARE(95) |
|
1774 |
TPS_DECLARE(96) |
|
1775 |
TPS_DECLARE(97) |
|
1776 |
TPS_DECLARE(98) |
|
1777 |
TPS_DECLARE(99) |
|
1778 |
TPS_DECLARE(100) |
|
1779 |
TPS_DECLARE(101) |
|
1780 |
TPS_DECLARE(102) |
|
1781 |
TPS_DECLARE(103) |
|
1782 |
TPS_DECLARE(104) |
|
1783 |
TPS_DECLARE(105) |
|
1784 |
TPS_DECLARE(106) |
|
1785 |
TPS_DECLARE(107) |
|
1786 |
TPS_DECLARE(108) |
|
1787 |
TPS_DECLARE(109) |
|
1788 |
TPS_DECLARE(110) |
|
1789 |
TPS_DECLARE(111) |
|
1790 |
TPS_DECLARE(112) |
|
1791 |
TPS_DECLARE(113) |
|
1792 |
TPS_DECLARE(114) |
|
1793 |
TPS_DECLARE(115) |
|
1794 |
TPS_DECLARE(116) |
|
1795 |
TPS_DECLARE(117) |
|
1796 |
TPS_DECLARE(118) |
|
1797 |
TPS_DECLARE(119) |
|
1798 |
TPS_DECLARE(120) |
|
1799 |
TPS_DECLARE(121) |
|
1800 |
TPS_DECLARE(122) |
|
1801 |
TPS_DECLARE(123) |
|
1802 |
TPS_DECLARE(124) |
|
1803 |
TPS_DECLARE(125) |
|
1804 |
TPS_DECLARE(126) |
|
1805 |
TPS_DECLARE(127) |
|
1806 |
TPS_DECLARE(128) |
|
1807 |
TPS_DECLARE(129) |
|
1808 |
TPS_DECLARE(130) |
|
1809 |
TPS_DECLARE(131) |
|
1810 |
TPS_DECLARE(132) |
|
1811 |
TPS_DECLARE(133) |
|
1812 |
TPS_DECLARE(134) |
|
1813 |
TPS_DECLARE(135) |
|
1814 |
TPS_DECLARE(136) |
|
1815 |
TPS_DECLARE(137) |
|
1816 |
TPS_DECLARE(138) |
|
1817 |
TPS_DECLARE(139) |
|
1818 |
TPS_DECLARE(140) |
|
1819 |
TPS_DECLARE(141) |
|
1820 |
TPS_DECLARE(142) |
|
1821 |
TPS_DECLARE(143) |
|
1822 |
TPS_DECLARE(144) |
|
1823 |
TPS_DECLARE(145) |
|
1824 |
TPS_DECLARE(146) |
|
1825 |
TPS_DECLARE(147) |
|
1826 |
TPS_DECLARE(148) |
|
1827 |
TPS_DECLARE(149) |
|
1828 |
TPS_DECLARE(150) |
|
1829 |
TPS_DECLARE(151) |
|
1830 |
TPS_DECLARE(152) |
|
1831 |
TPS_DECLARE(153) |
|
1832 |
TPS_DECLARE(154) |
|
1833 |
TPS_DECLARE(155) |
|
1834 |
TPS_DECLARE(156) |
|
1835 |
TPS_DECLARE(157) |
|
1836 |
TPS_DECLARE(158) |
|
1837 |
TPS_DECLARE(159) |
|
1838 |
TPS_DECLARE(160) |
|
1839 |
TPS_DECLARE(161) |
|
1840 |
TPS_DECLARE(162) |
|
1841 |
TPS_DECLARE(163) |
|
1842 |
TPS_DECLARE(164) |
|
1843 |
TPS_DECLARE(165) |
|
1844 |
TPS_DECLARE(166) |
|
1845 |
TPS_DECLARE(167) |
|
1846 |
TPS_DECLARE(168) |
|
1847 |
TPS_DECLARE(169) |
|
1848 |
TPS_DECLARE(170) |
|
1849 |
TPS_DECLARE(171) |
|
1850 |
TPS_DECLARE(172) |
|
1851 |
TPS_DECLARE(173) |
|
1852 |
TPS_DECLARE(174) |
|
1853 |
TPS_DECLARE(175) |
|
1854 |
TPS_DECLARE(176) |
|
1855 |
TPS_DECLARE(177) |
|
1856 |
TPS_DECLARE(178) |
|
1857 |
TPS_DECLARE(179) |
|
1858 |
TPS_DECLARE(180) |
|
1859 |
TPS_DECLARE(181) |
|
1860 |
TPS_DECLARE(182) |
|
1861 |
TPS_DECLARE(183) |
|
1862 |
TPS_DECLARE(184) |
|
1863 |
TPS_DECLARE(185) |
|
1864 |
TPS_DECLARE(186) |
|
1865 |
TPS_DECLARE(187) |
|
1866 |
TPS_DECLARE(188) |
|
1867 |
TPS_DECLARE(189) |
|
1868 |
TPS_DECLARE(190) |
|
1869 |
TPS_DECLARE(191) |
|
1870 |
TPS_DECLARE(192) |
|
1871 |
TPS_DECLARE(193) |
|
1872 |
TPS_DECLARE(194) |
|
1873 |
TPS_DECLARE(195) |
|
1874 |
TPS_DECLARE(196) |
|
1875 |
TPS_DECLARE(197) |
|
1876 |
TPS_DECLARE(198) |
|
1877 |
TPS_DECLARE(199) |
|
1878 |
TPS_DECLARE(200) |
|
1879 |
TPS_DECLARE(201) |
|
1880 |
TPS_DECLARE(202) |
|
1881 |
TPS_DECLARE(203) |
|
1882 |
TPS_DECLARE(204) |
|
1883 |
TPS_DECLARE(205) |
|
1884 |
TPS_DECLARE(206) |
|
1885 |
TPS_DECLARE(207) |
|
1886 |
TPS_DECLARE(208) |
|
1887 |
TPS_DECLARE(209) |
|
1888 |
TPS_DECLARE(210) |
|
1889 |
TPS_DECLARE(211) |
|
1890 |
TPS_DECLARE(212) |
|
1891 |
TPS_DECLARE(213) |
|
1892 |
TPS_DECLARE(214) |
|
1893 |
TPS_DECLARE(215) |
|
1894 |
TPS_DECLARE(216) |
|
1895 |
TPS_DECLARE(217) |
|
1896 |
TPS_DECLARE(218) |
|
1897 |
TPS_DECLARE(219) |
|
1898 |
TPS_DECLARE(220) |
|
1899 |
TPS_DECLARE(221) |
|
1900 |
TPS_DECLARE(222) |
|
1901 |
TPS_DECLARE(223) |
|
1902 |
TPS_DECLARE(224) |
|
1903 |
TPS_DECLARE(225) |
|
1904 |
TPS_DECLARE(226) |
|
1905 |
TPS_DECLARE(227) |
|
1906 |
TPS_DECLARE(228) |
|
1907 |
TPS_DECLARE(229) |
|
1908 |
TPS_DECLARE(230) |
|
1909 |
TPS_DECLARE(231) |
|
1910 |
TPS_DECLARE(232) |
|
1911 |
TPS_DECLARE(233) |
|
1912 |
TPS_DECLARE(234) |
|
1913 |
TPS_DECLARE(235) |
|
1914 |
TPS_DECLARE(236) |
|
1915 |
TPS_DECLARE(237) |
|
1916 |
TPS_DECLARE(238) |
|
1917 |
TPS_DECLARE(239) |
|
1918 |
TPS_DECLARE(240) |
|
1919 |
TPS_DECLARE(241) |
|
1920 |
TPS_DECLARE(242) |
|
1921 |
TPS_DECLARE(243) |
|
1922 |
TPS_DECLARE(244) |
|
1923 |
TPS_DECLARE(245) |
|
1924 |
TPS_DECLARE(246) |
|
1925 |
TPS_DECLARE(247) |
|
1926 |
TPS_DECLARE(248) |
|
1927 |
TPS_DECLARE(249) |
|
1928 |
TPS_DECLARE(250) |
|
1929 |
TPS_DECLARE(251) |
|
1930 |
TPS_DECLARE(252) |
|
1931 |
TPS_DECLARE(253) |
|
1932 |
TPS_DECLARE(254) |
|
1933 |
TPS_DECLARE(255) |
|
1934 |
#endif //T_PAGESTRESS_LARGE_ARRAY |
|
1935 |
||
1936 |
TInt *CheckLdmiaInstr(void) |
|
1937 |
{ |
|
1938 |
return NULL; |
|
1939 |
} |
|
1940 |
||
1941 |
||
209
6035754ebf88
Fix for bug 3291 - [GCCE] armcc build equated with armv5 build in f32test
Mike Kinghan <mikek@symbian.org>
parents:
0
diff
changeset
|
1942 |
#endif // __EABI__ |
0 | 1943 |
|
1944 |
TInt CallTestFunc(TInt aParam1, TInt aParam2, TInt aIndex) |
|
1945 |
{ |
|
1946 |
#define CALLFUNC(_num) case _num: return TestAlignment##_num(aParam1, aParam2); |
|
1947 |
||
1948 |
switch (aIndex) |
|
1949 |
{ |
|
1950 |
CALLFUNC(0) |
|
1951 |
CALLFUNC(1) |
|
1952 |
CALLFUNC(2) |
|
1953 |
CALLFUNC(3) |
|
1954 |
CALLFUNC(4) |
|
1955 |
CALLFUNC(5) |
|
1956 |
CALLFUNC(6) |
|
1957 |
CALLFUNC(7) |
|
1958 |
CALLFUNC(8) |
|
1959 |
CALLFUNC(9) |
|
1960 |
CALLFUNC(10) |
|
1961 |
CALLFUNC(11) |
|
1962 |
CALLFUNC(12) |
|
1963 |
CALLFUNC(13) |
|
1964 |
CALLFUNC(14) |
|
1965 |
CALLFUNC(15) |
|
1966 |
CALLFUNC(16) |
|
1967 |
CALLFUNC(17) |
|
1968 |
CALLFUNC(18) |
|
1969 |
CALLFUNC(19) |
|
1970 |
CALLFUNC(20) |
|
1971 |
CALLFUNC(21) |
|
1972 |
CALLFUNC(22) |
|
1973 |
CALLFUNC(23) |
|
1974 |
CALLFUNC(24) |
|
1975 |
CALLFUNC(25) |
|
1976 |
CALLFUNC(26) |
|
1977 |
CALLFUNC(27) |
|
1978 |
CALLFUNC(28) |
|
1979 |
CALLFUNC(29) |
|
1980 |
CALLFUNC(30) |
|
1981 |
CALLFUNC(31) |
|
1982 |
CALLFUNC(32) |
|
1983 |
CALLFUNC(33) |
|
1984 |
CALLFUNC(34) |
|
1985 |
CALLFUNC(35) |
|
1986 |
CALLFUNC(36) |
|
1987 |
CALLFUNC(37) |
|
1988 |
CALLFUNC(38) |
|
1989 |
CALLFUNC(39) |
|
1990 |
CALLFUNC(40) |
|
1991 |
CALLFUNC(41) |
|
1992 |
CALLFUNC(42) |
|
1993 |
CALLFUNC(43) |
|
1994 |
CALLFUNC(44) |
|
1995 |
CALLFUNC(45) |
|
1996 |
CALLFUNC(46) |
|
1997 |
CALLFUNC(47) |
|
1998 |
CALLFUNC(48) |
|
1999 |
CALLFUNC(49) |
|
2000 |
CALLFUNC(50) |
|
2001 |
CALLFUNC(51) |
|
2002 |
CALLFUNC(52) |
|
2003 |
CALLFUNC(53) |
|
2004 |
CALLFUNC(54) |
|
2005 |
CALLFUNC(55) |
|
2006 |
CALLFUNC(56) |
|
2007 |
CALLFUNC(57) |
|
2008 |
CALLFUNC(58) |
|
2009 |
CALLFUNC(59) |
|
2010 |
CALLFUNC(60) |
|
2011 |
CALLFUNC(61) |
|
2012 |
CALLFUNC(62) |
|
2013 |
CALLFUNC(63) |
|
2014 |
#ifdef T_PAGESTRESS_LARGE_ARRAY |
|
2015 |
CALLFUNC(64) |
|
2016 |
CALLFUNC(65) |
|
2017 |
CALLFUNC(66) |
|
2018 |
CALLFUNC(67) |
|
2019 |
CALLFUNC(68) |
|
2020 |
CALLFUNC(69) |
|
2021 |
CALLFUNC(70) |
|
2022 |
CALLFUNC(71) |
|
2023 |
CALLFUNC(72) |
|
2024 |
CALLFUNC(73) |
|
2025 |
CALLFUNC(74) |
|
2026 |
CALLFUNC(75) |
|
2027 |
CALLFUNC(76) |
|
2028 |
CALLFUNC(77) |
|
2029 |
CALLFUNC(78) |
|
2030 |
CALLFUNC(79) |
|
2031 |
CALLFUNC(80) |
|
2032 |
CALLFUNC(81) |
|
2033 |
CALLFUNC(82) |
|
2034 |
CALLFUNC(83) |
|
2035 |
CALLFUNC(84) |
|
2036 |
CALLFUNC(85) |
|
2037 |
CALLFUNC(86) |
|
2038 |
CALLFUNC(87) |
|
2039 |
CALLFUNC(88) |
|
2040 |
CALLFUNC(89) |
|
2041 |
CALLFUNC(90) |
|
2042 |
CALLFUNC(91) |
|
2043 |
CALLFUNC(92) |
|
2044 |
CALLFUNC(93) |
|
2045 |
CALLFUNC(94) |
|
2046 |
CALLFUNC(95) |
|
2047 |
CALLFUNC(96) |
|
2048 |
CALLFUNC(97) |
|
2049 |
CALLFUNC(98) |
|
2050 |
CALLFUNC(99) |
|
2051 |
CALLFUNC(100) |
|
2052 |
CALLFUNC(101) |
|
2053 |
CALLFUNC(102) |
|
2054 |
CALLFUNC(103) |
|
2055 |
CALLFUNC(104) |
|
2056 |
CALLFUNC(105) |
|
2057 |
CALLFUNC(106) |
|
2058 |
CALLFUNC(107) |
|
2059 |
CALLFUNC(108) |
|
2060 |
CALLFUNC(109) |
|
2061 |
CALLFUNC(110) |
|
2062 |
CALLFUNC(111) |
|
2063 |
CALLFUNC(112) |
|
2064 |
CALLFUNC(113) |
|
2065 |
CALLFUNC(114) |
|
2066 |
CALLFUNC(115) |
|
2067 |
CALLFUNC(116) |
|
2068 |
CALLFUNC(117) |
|
2069 |
CALLFUNC(118) |
|
2070 |
CALLFUNC(119) |
|
2071 |
CALLFUNC(120) |
|
2072 |
CALLFUNC(121) |
|
2073 |
CALLFUNC(122) |
|
2074 |
CALLFUNC(123) |
|
2075 |
CALLFUNC(124) |
|
2076 |
CALLFUNC(125) |
|
2077 |
CALLFUNC(126) |
|
2078 |
CALLFUNC(127) |
|
2079 |
CALLFUNC(128) |
|
2080 |
CALLFUNC(129) |
|
2081 |
CALLFUNC(130) |
|
2082 |
CALLFUNC(131) |
|
2083 |
CALLFUNC(132) |
|
2084 |
CALLFUNC(133) |
|
2085 |
CALLFUNC(134) |
|
2086 |
CALLFUNC(135) |
|
2087 |
CALLFUNC(136) |
|
2088 |
CALLFUNC(137) |
|
2089 |
CALLFUNC(138) |
|
2090 |
CALLFUNC(139) |
|
2091 |
CALLFUNC(140) |
|
2092 |
CALLFUNC(141) |
|
2093 |
CALLFUNC(142) |
|
2094 |
CALLFUNC(143) |
|
2095 |
CALLFUNC(144) |
|
2096 |
CALLFUNC(145) |
|
2097 |
CALLFUNC(146) |
|
2098 |
CALLFUNC(147) |
|
2099 |
CALLFUNC(148) |
|
2100 |
CALLFUNC(149) |
|
2101 |
CALLFUNC(150) |
|
2102 |
CALLFUNC(151) |
|
2103 |
CALLFUNC(152) |
|
2104 |
CALLFUNC(153) |
|
2105 |
CALLFUNC(154) |
|
2106 |
CALLFUNC(155) |
|
2107 |
CALLFUNC(156) |
|
2108 |
CALLFUNC(157) |
|
2109 |
CALLFUNC(158) |
|
2110 |
CALLFUNC(159) |
|
2111 |
CALLFUNC(160) |
|
2112 |
CALLFUNC(161) |
|
2113 |
CALLFUNC(162) |
|
2114 |
CALLFUNC(163) |
|
2115 |
CALLFUNC(164) |
|
2116 |
CALLFUNC(165) |
|
2117 |
CALLFUNC(166) |
|
2118 |
CALLFUNC(167) |
|
2119 |
CALLFUNC(168) |
|
2120 |
CALLFUNC(169) |
|
2121 |
CALLFUNC(170) |
|
2122 |
CALLFUNC(171) |
|
2123 |
CALLFUNC(172) |
|
2124 |
CALLFUNC(173) |
|
2125 |
CALLFUNC(174) |
|
2126 |
CALLFUNC(175) |
|
2127 |
CALLFUNC(176) |
|
2128 |
CALLFUNC(177) |
|
2129 |
CALLFUNC(178) |
|
2130 |
CALLFUNC(179) |
|
2131 |
CALLFUNC(180) |
|
2132 |
CALLFUNC(181) |
|
2133 |
CALLFUNC(182) |
|
2134 |
CALLFUNC(183) |
|
2135 |
CALLFUNC(184) |
|
2136 |
CALLFUNC(185) |
|
2137 |
CALLFUNC(186) |
|
2138 |
CALLFUNC(187) |
|
2139 |
CALLFUNC(188) |
|
2140 |
CALLFUNC(189) |
|
2141 |
CALLFUNC(190) |
|
2142 |
CALLFUNC(191) |
|
2143 |
CALLFUNC(192) |
|
2144 |
CALLFUNC(193) |
|
2145 |
CALLFUNC(194) |
|
2146 |
CALLFUNC(195) |
|
2147 |
CALLFUNC(196) |
|
2148 |
CALLFUNC(197) |
|
2149 |
CALLFUNC(198) |
|
2150 |
CALLFUNC(199) |
|
2151 |
CALLFUNC(200) |
|
2152 |
CALLFUNC(201) |
|
2153 |
CALLFUNC(202) |
|
2154 |
CALLFUNC(203) |
|
2155 |
CALLFUNC(204) |
|
2156 |
CALLFUNC(205) |
|
2157 |
CALLFUNC(206) |
|
2158 |
CALLFUNC(207) |
|
2159 |
CALLFUNC(208) |
|
2160 |
CALLFUNC(209) |
|
2161 |
CALLFUNC(210) |
|
2162 |
CALLFUNC(211) |
|
2163 |
CALLFUNC(212) |
|
2164 |
CALLFUNC(213) |
|
2165 |
CALLFUNC(214) |
|
2166 |
CALLFUNC(215) |
|
2167 |
CALLFUNC(216) |
|
2168 |
CALLFUNC(217) |
|
2169 |
CALLFUNC(218) |
|
2170 |
CALLFUNC(219) |
|
2171 |
CALLFUNC(220) |
|
2172 |
CALLFUNC(221) |
|
2173 |
CALLFUNC(222) |
|
2174 |
CALLFUNC(223) |
|
2175 |
CALLFUNC(224) |
|
2176 |
CALLFUNC(225) |
|
2177 |
CALLFUNC(226) |
|
2178 |
CALLFUNC(227) |
|
2179 |
CALLFUNC(228) |
|
2180 |
CALLFUNC(229) |
|
2181 |
CALLFUNC(230) |
|
2182 |
CALLFUNC(231) |
|
2183 |
CALLFUNC(232) |
|
2184 |
CALLFUNC(233) |
|
2185 |
CALLFUNC(234) |
|
2186 |
CALLFUNC(235) |
|
2187 |
CALLFUNC(236) |
|
2188 |
CALLFUNC(237) |
|
2189 |
CALLFUNC(238) |
|
2190 |
CALLFUNC(239) |
|
2191 |
CALLFUNC(240) |
|
2192 |
CALLFUNC(241) |
|
2193 |
CALLFUNC(242) |
|
2194 |
CALLFUNC(243) |
|
2195 |
CALLFUNC(244) |
|
2196 |
CALLFUNC(245) |
|
2197 |
CALLFUNC(246) |
|
2198 |
CALLFUNC(247) |
|
2199 |
CALLFUNC(248) |
|
2200 |
CALLFUNC(249) |
|
2201 |
CALLFUNC(250) |
|
2202 |
CALLFUNC(251) |
|
2203 |
CALLFUNC(252) |
|
2204 |
CALLFUNC(253) |
|
2205 |
CALLFUNC(254) |
|
2206 |
CALLFUNC(255) |
|
2207 |
#endif //T_PAGESTRESS_LARGE_ARRAY |
|
2208 |
default: break; |
|
2209 |
} |
|
2210 |
return 0; |
|
2211 |
} |
|
2212 |
||
2213 |
//#endif // defined(_DEBUG) || defined(_DEBUG_RELEASE) |
|
2214 |