kerneltest/e32test/iic/t_iic.h
author Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
Fri, 16 Apr 2010 16:24:37 +0300
changeset 90 947f0dc9f7a8
parent 33 0173bcd7697c
child 199 189ece41fa29
permissions -rw-r--r--
Revision: 201015 Kit: 201015
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// Copyright (c) 1995-2009 Nokia Corporation and/or its subsidiary(-ies).
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// All rights reserved.
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// This component and the accompanying materials are made available
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// under the terms of the License "Eclipse Public License v1.0"
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// which accompanies this distribution, and is available
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// at the URL "http://www.eclipse.org/legal/epl-v10.html".
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//
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// Initial Contributors:
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// Nokia Corporation - initial contribution.
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//
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// Contributors:
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//
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// Description:
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// e32test\iic\t_iic.h
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//
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#ifndef __T_IIC_H__
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#define __T_IIC_H__
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#include <e32ver.h>
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const TInt KIicClientMajorVersionNumber = 1;
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const TInt KIicClientMinorVersionNumber = 0;
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const TInt KIicClientBuildVersionNumber = KE32BuildVersionNumber;
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const TInt KPriorityTestNum = 6; // 1 blocking transaction + 5 test transactions
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// For IIC,
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// If bit 31 is set and bit 30 cleared it is used to extend the Master-Slave channel;
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// if bit 31 is cleared and bit 30 is set, it extends the Master channel; 
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// if both bits 31 and 30 are cleared it extends the Slave channel interface.
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// However,
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// since the kernel-side proxy clients interpret the msb being set as indicative of an
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// asynchronous request, the values here will have the static extension pattern represented
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// in bits 30 and 29, instead. In addition, to support communication with the slave-side proxy,
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// the Slave extension value will be represented as bits 30 and 29 set, so that it can be distinguished
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// from 'normal' synchronous operations.
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//
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const TUint KTestControlIoMask =			0x60000000;
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const TUint KTestMasterControlIo =		0x20000000;
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const TUint KTestSlaveControlIo =		0x60000000;
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const TUint KTestMasterSlaveControlIo =	0x40000000;
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const TUint KTestControlIoPilOffset =	0x00000002;	// Corresponds to 1 higher than the number used by PIL
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const TUint KTestControlUnitTestOffset = 0x10000000;
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//
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// Enumerations TReqType and TBusType defined in kernel-side class TIicBusTransfer
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// The user-side test, and the kernel-side proxy client require access to this
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enum TReqType
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	{
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	EMasterRead,
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	EMasterWrite
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	};
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enum TBusType
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	{
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	EI2c	   = 0,
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	ESpi	   = 0x01,
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	EMicrowire = 0x02,
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	ECci	   = 0x03,
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	ESccb	   = 0x04,
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	EInvalidBus
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	};
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#define MAX_TRANS_LENGTH 20	
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#ifndef __KERNEL_MODE__
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//
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//	For convenience, selected kernel-side information is replicated here
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//  to allow the user-side test to populate buffers accordingly
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//
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// Bus-specific configuration
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//
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enum TEndianness
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	{
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	EBigEndian,
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	ELittleEndian
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	};
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enum TBitOrder
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	{
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	ELsbFirst,
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	EMsbFirst
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	};
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//
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// Bus-specific configuration for SPI bus
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//
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enum TSpiWordWidth
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	{
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	ESpiWordWidth_8,
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	ESpiWordWidth_10,
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	ESpiWordWidth_12,
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	ESpiWordWidth_16
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	};
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enum TSpiClkMode
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	{
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	ESpiPolarityLowRisingEdge,		// Active high, odd edges
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	ESpiPolarityLowFallingEdge,		// Active high, even edges
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	ESpiPolarityHighFallingEdge,	// Active low,  odd edges
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	ESpiPolarityHighRisingEdge		// Active low,  even edges
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	};
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enum TSpiSsPinMode
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    {
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    ESpiCSPinActiveLow,      // Active low
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    ESpiCSPinActiveHigh     // Active high
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    };
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class TConfigSpiV01
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	{
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public:
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	TSpiWordWidth	iWordWidth;
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	TInt32			iClkSpeedHz;
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	TSpiClkMode		iClkMode;
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	TInt32			iTimeoutPeriod;
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	TEndianness		iEndianness;
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	TBitOrder		iBitOrder;
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	TUint			iTransactionWaitCycles;
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	TSpiSsPinMode	iSSPinActiveMode;
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	};
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typedef TPckgBuf <TConfigSpiV01> TConfigSpiBufV01;
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//
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// Bus-specific configuration for I2C bus
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//
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enum TI2cAddrType
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	{
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	EI2cAddr7Bit,
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	EI2cAddr10Bit
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	};
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class TConfigI2cV01
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	{
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	public:
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	TI2cAddrType	iAddrType;		// 7 or 10-bit addressing
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	TInt32			iClkSpeedHz;
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	TEndianness		iEndianness;
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	TInt32			iTimeoutPeriod;
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	};
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typedef TPckgBuf <TConfigI2cV01> TConfigI2cBufV01;
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inline static TInt CreateSpiBuf(TConfigSpiBufV01*& aBuf,
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								TSpiWordWidth	aWordWidth,
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								TInt32			aClkSpeedHz,
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								TSpiClkMode		aClkMode,
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								TInt32			aTimeoutPeriod,
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								TEndianness		aEndianness,
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								TBitOrder		aBitOrder,
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								TUint			aTransactionWaitCycles,
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								TSpiSsPinMode	aSSPinActiveMode)
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// Utility function to create a buffer for the SPI bus
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	{
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	aBuf = new TConfigSpiBufV01();
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	if(aBuf==NULL)
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		return KErrNoMemory;
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	TConfigSpiV01 *buf = &((*aBuf)());
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	buf->iWordWidth = aWordWidth;
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	buf->iClkSpeedHz = aClkSpeedHz;
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	buf->iClkMode = aClkMode;
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	buf->iTimeoutPeriod = aTimeoutPeriod;
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	buf->iEndianness = aEndianness;
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	buf->iBitOrder = aBitOrder;
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	buf->iTransactionWaitCycles = aTransactionWaitCycles;
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	buf->iSSPinActiveMode = aSSPinActiveMode;
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	return KErrNone;
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	}
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inline static TInt CreateI2cBuf(TConfigI2cBufV01*& aBuf,
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								TI2cAddrType	aAddrType,
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								TInt32			aClkSpeedHz,
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								TEndianness		aEndianness,
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								TInt32			aTimeoutPeriod)
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// Utility function to create a buffer for the I2C bus
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	{
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	aBuf = new TConfigI2cBufV01();
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	if(aBuf==NULL)
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		return KErrNoMemory;
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	TConfigI2cV01 *buf = &((*aBuf)());
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	buf->iAddrType = aAddrType;
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	buf->iClkSpeedHz = aClkSpeedHz;
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	buf->iEndianness = aEndianness;
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	buf->iTimeoutPeriod = aTimeoutPeriod;
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	return KErrNone;
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	}
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//
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// Enumerations for channel type and channel duplex defined in kernel-side class DIicBusChannel
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// duplicated for temporary test
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enum TChannelType
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	{
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	EMaster			= 0,
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	ESlave			= 0x01,
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	EMasterSlave	= 0x02,
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	EInvalidType
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	};
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enum TChannelDuplex
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	{
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	EHalfDuplex = 0,	// supports only half duplex transactions (even if bus spec supports full duplex)
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	EFullDuplex = 0x1,	// supports full duplex transactions (queud transactions may still be half duplex)
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	EInvalidDuplex
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	};
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//
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// Bus realisation configuration
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//
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// 31 30 29 28 | 27 26 25 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 | 11 10  9  8 |  7  6  5  4 |  3  2  1  0
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//
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// 31:29 - HS Master address (I2C only)
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// 28    - HS address valid bit
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// 27:23 - Reserved
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// 22:20 - Bus type
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// 19:15 - Channel number
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// 14:10 - Transaction speed	// deprecated
0
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//  9:0  - Slave address
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#define HS_MASTER_ADDR_SHIFT 29
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#define HS_MASTER_ADDR_MASK 0x7
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#define HS_ADDR_VALID_SHIFT 28
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#define HS_ADDR_VALID_MASK 0x1
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#define BUS_TYPE_SHIFT 20
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#define BUS_TYPE_MASK 0x7
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#define CHANNEL_NO_SHIFT 15
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#define CHANNEL_NO_MASK 0x1F
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//#define TRANS_SPEED_SHIFT 10
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//#define TRANS_SPEED_MASK 0x1F
0
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#define SLAVE_ADDR_SHIFT 0
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#define SLAVE_ADDR_MASK 0x3FF
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//
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// Macros to access fields within Bus Realisation Configuration data, used on a per-transaction basis with IIC
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#define SET_CONFIG_FIELD(aBusId,aField,aMask,aShift) aBusId=(aBusId&~(aMask<<aShift))|((aField&aMask)<<aShift);
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#define GET_CONFIG_FIELD(aBusId,aMask,aShift) (((aBusId)>>(aShift))&(aMask))
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#define GET_HS_MASTER_ADDR(aBusId) GET_CONFIG_FIELD(aBusId,HS_MASTER_ADDR_MASK,HS_MASTER_ADDR_SHIFT)
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#define SET_HS_MASTER_ADDR(aBusId,aHsMasterAddr) SET_CONFIG_FIELD(aBusId,aHsMasterAddr,HS_MASTER_ADDR_MASK,HS_MASTER_ADDR_SHIFT)
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#define GET_HS_VALID(aBusId) GET_CONFIG_FIELD(aBusId,HS_ADDR_VALID_MASK,HS_ADDR_VALID_SHIFT)
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#define SET_HS_VALID(aBusId,aHsValid) SET_CONFIG_FIELD(aBusId,aHsValid,HS_ADDR_VALID_MASK,HS_ADDR_VALID_SHIFT)
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#define GET_BUS_TYPE(aBusId) GET_CONFIG_FIELD(aBusId,BUS_TYPE_MASK,BUS_TYPE_SHIFT)
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#define SET_BUS_TYPE(aBusId,aBusType) SET_CONFIG_FIELD(aBusId,aBusType,BUS_TYPE_MASK,BUS_TYPE_SHIFT)
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#define GET_CHAN_NUM(aBusId) GET_CONFIG_FIELD(aBusId,CHANNEL_NO_MASK,CHANNEL_NO_SHIFT)
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#define SET_CHAN_NUM(aBusId,aChanNum) SET_CONFIG_FIELD(aBusId,aChanNum,CHANNEL_NO_MASK,CHANNEL_NO_SHIFT)
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//#define SET_TRANS_SPEED(aBusId,aTransSpeed) SET_CONFIG_FIELD(aBusId,aTransSpeed,TRANS_SPEED_MASK,TRANS_SPEED_SHIFT)
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//#define GET_TRANS_SPEED(aBusId) GET_CONFIG_FIELD(aBusId,TRANS_SPEED_MASK,TRANS_SPEED_SHIFT)
0
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#define SET_SLAVE_ADDR(aBusId,aSlaveAddr) SET_CONFIG_FIELD(aBusId,aSlaveAddr,SLAVE_ADDR_MASK,SLAVE_ADDR_SHIFT)
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#define GET_SLAVE_ADDR(aBusId) GET_CONFIG_FIELD(aBusId,SLAVE_ADDR_MASK,SLAVE_ADDR_SHIFT)
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static const TUint8 KTransactionWithPreamble = 0x80;
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static const TUint8 KTransactionWithMultiTransc = 0x40;
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enum TIicBusSlaveTrigger
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	{
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	ERxAllBytes			= 0x01,
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	ERxUnderrun			= 0x02,
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	ERxOverrun			= 0x04,
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	ETxAllBytes			= 0x08,
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	ETxUnderrun			= 0x10,
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	ETxOverrun			= 0x20,
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	EGeneralBusError	= 0x40,
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	EAsyncCaptChan		= 0x80
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	};
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#endif // #ifndef __KERNEL_MODE__
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//
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// User-Side abbreviation of kernel side classes TIicBusTransfer and TIicBusTransaction
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//
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struct TUsideTferDesc
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	{
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	TInt8 iType;			// as one of TReqType
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	TInt8 iBufGranularity;	// width of a transfer word in bits
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	TDes8* iBuffer;	// the data for this transfer (packed into 8-bit words with padding)
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	TUsideTferDesc* iNext;
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	};
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struct TUsideTracnDesc
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	{
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	TBusType iType;
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	TDes8* iHeader;
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	TUsideTferDesc* iHalfDuplexTrans;
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	TUsideTferDesc* iFullDuplexTrans;
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	TUint8 iFlags;				// used to indicate if it supports a preamble
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	TAny* iPreambleArg;			// used for preamble argument
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	TAny* iMultiTranscArg;		// used for multi transc argument
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	};
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class RBusDevIicClient : public RBusLogicalChannel
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	{
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    public:
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	enum TControl
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		{
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// Master mode operations
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		EQTransSync=1,						/**< Queue Transaction (Synchronous version)					*/
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// Slave mode operations
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		EInitSlaveClient,					/**< Instigate Slave initialisation required to support testing	*/
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		ECaptureChanSync,					/**< Capture Channel (Synchronous version)						*/
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		EReleaseChan,						/**< ReleaseChannel												*/
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		ERegisterRxBuffer,					/**< Register a buffer for receiving data						*/
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		ERegisterTxBuffer,					/**< Register a buffer for transmitting data					*/
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		ESetNotifTrigger					/**< Set the notification triggers                               */									
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		};
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	enum TStaticExt
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		{
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		ECtlIoNone = 0,
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		ECtlIoDumpChan = 1, // KCtrlIoDumpChan - defined only for UDEB
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// ControlIO codes for Master follow
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		ECtlIoBlockReqCompletion=(KTestMasterControlIo+KTestControlIoPilOffset),
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		ECtlIoUnblockReqCompletion,
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		ECtlIoDeRegChan,
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		ECtlIoTracnOne,
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		ECtlIoPriorityTest,
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		EGetTestResult,
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		ECtlIoSetTimeOutFlag,
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		ECtlIoTestFullDuplexTrans,
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// ControlIO codes for Slave follow
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		ECtrlIoRxWords=(KTestSlaveControlIo+KTestControlIoPilOffset),
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		ECtrlIoTxWords,
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		ECtrlIoRxTxWords,
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		ECtrlIoTxChkBuf,
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		ECtlIoBusError,
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		ECtrlIoBlockNotification,
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		ECtrlIoUnblockNotification,
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		ECtrlIoUpdTimeout,
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		ECtrlIoNotifNoTrigger
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		};
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	enum TTestFullDuplexTrans
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		{
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		ETestValidFullDuplexTrans=1,
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		ETestInvalidFullDuplexTrans1,
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		ETestInvalidFullDuplexTrans2,
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		ETestLastNodeFullDuplexTrans,
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		ETestDiffNodeNoFullDuplexTrans,
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		ETestNone
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		};
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   341
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	enum TRequest
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		{
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// Master mode operations
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		EQTransAsync=1,						/**< Queue Transaction (Asynchronous version)					*/
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		ECtrlIoTestBufReUse,
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// Slave mode operations
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		ECaptureChanAsync,					/**< Capture Channel (Asynchronous version)						*/
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		ECtrlIoOvUndRunRxTx
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		};
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	enum TTestMessages
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	    {
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	    ETestIicChannelInlineFunc=KTestControlUnitTestOffset    
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	    };
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   356
	
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#ifndef __KERNEL_MODE__
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	public:   
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	inline TInt TestIiicChannelInlineFunc(){return DoControl (ETestIicChannelInlineFunc, NULL, NULL);}	
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	// Master mode functions
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	inline TInt Open(TDesC& aProxyName) {return (DoCreate(aProxyName,TVersion(KIicClientMajorVersionNumber,KIicClientMinorVersionNumber,KIicClientBuildVersionNumber),-1,NULL,NULL,EOwnerThread));}
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   362
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	inline TInt QueueTransaction(TInt aBusId, TUsideTracnDesc* aTransaction) {return(DoControl(EQTransSync,(TAny*)aBusId,(TAny*)aTransaction));}
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   364
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	inline void QueueTransaction(TRequestStatus& aStatus, TInt aBusId, TUsideTracnDesc* aTransaction) {DoRequest(EQTransAsync,aStatus,(TAny*)aBusId,(TAny*)aTransaction);}
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	inline void CancelAsyncOperation(TRequestStatus* aStatus, TInt aBusId)	{TInt* parms[2]; parms[0]=(TInt*)aStatus; parms[1]=(TInt*)aBusId;DoCancel((TInt)&parms[0]);} 
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	// Slave mode functions
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	inline TInt InitSlaveClient() {return(DoControl(EInitSlaveClient,NULL,NULL));}
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   371
	inline TInt CaptureChannel(TInt aBusId, TDes8* aConfigHdr, TInt& aChannelId) {TInt* parms[2]; parms[0]=(TInt*)aBusId; parms[1]=&aChannelId;return(DoControl(ECaptureChanSync,(TAny*)aConfigHdr,(TAny*)(&parms[0])));}
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   372
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   373
	inline TInt CaptureChannel(TInt aBusId, TDes8* aConfigHdr, TInt& aChannelId, TRequestStatus& aStatus) {TInt* parms[2]; parms[0]=(TInt*)aBusId; parms[1]=&aChannelId;DoRequest(ECaptureChanAsync,aStatus,(TAny*)aConfigHdr,(TAny*)(&parms[0]));return KErrNone;}
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   374
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	inline TInt ReleaseChannel(TInt aChannelId){return(DoControl(EReleaseChan,(TAny*)aChannelId,NULL));};
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	inline TInt RegisterRxBuffer(TInt aChannelId, TInt8 aBufGranularity, TInt8 aNumWords, TInt8 aOffset){TInt8 parms[3]; parms[0]=aBufGranularity; parms[1]=aNumWords; parms[2]=aOffset;return(DoControl(ERegisterRxBuffer,(TAny*)aChannelId,(TAny*)(&parms[0])));};
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	inline TInt RegisterTxBuffer(TInt aChannelId, TInt8 aBufGranularity, TInt8 aNumWords, TInt8 aOffset){TInt8 parms[3]; parms[0]=aBufGranularity; parms[1]=aNumWords; parms[2]=aOffset;return(DoControl(ERegisterTxBuffer,(TAny*)aChannelId,(TAny*)(&parms[0])));};
90
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	inline TInt SetNotificationTrigger(TInt aChannelId, TInt aTrigger, TRequestStatus* aStatus){TInt parms[2]; parms[0]=aChannelId; parms[1]=aTrigger; *aStatus=KRequestPending; return(DoControl(ESetNotifTrigger,(TAny*)aStatus,(TAny*)(&parms[0])));};
0
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   379
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	// ControlIO functions follow
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	inline TInt BlockReqCompletion(TInt aBusId) {return(DoControl(ECtlIoBlockReqCompletion,(TAny*)aBusId));}
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	inline TInt UnblockReqCompletion(TInt aBusId) {return(DoControl(ECtlIoUnblockReqCompletion,(TAny*)aBusId));}
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   383
	inline TInt DeRegisterChan(TInt aBusId) {return(DoControl(ECtlIoDeRegChan,(TAny*)aBusId));}
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   384
	inline TInt TestTracnOne(TInt aBusId) {return(DoControl(ECtlIoTracnOne, (TAny*)aBusId));}
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   385
	inline TInt SetTimeOutFlag(TInt aBusId){return(DoControl(ECtlIoSetTimeOutFlag,(TAny*)aBusId));}
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   386
	inline TInt CancelTimeOutFlag(TInt aBusId){return(DoControl(ECtlIoNone,(TAny*)aBusId));}
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   387
	inline TInt TestPriority(TInt aBusId) {return(DoControl(ECtlIoPriorityTest, (TAny*)aBusId));}
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   388
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   389
	inline TInt TestValidFullDuplexTrans(TInt aBusId) {return(DoControl(ECtlIoTestFullDuplexTrans, (TAny*)aBusId, (TAny*)ETestValidFullDuplexTrans));}
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   390
	inline TInt TestInvalidFullDuplexTrans1(TInt aBusId) {return(DoControl(ECtlIoTestFullDuplexTrans, (TAny*)aBusId, (TAny*)ETestInvalidFullDuplexTrans1));}
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   391
	inline TInt TestInvalidFullDuplexTrans2(TInt aBusId) {return(DoControl(ECtlIoTestFullDuplexTrans, (TAny*)aBusId, (TAny*)ETestInvalidFullDuplexTrans2));}
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   392
	
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   393
	inline TInt TestLastNodeFullDuplexTrans(TInt aBusId) {return(DoControl(ECtlIoTestFullDuplexTrans, (TAny*)aBusId, (TAny*)ETestLastNodeFullDuplexTrans));}
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   394
	inline TInt TestDiffNodeNumFullDuplexTrans(TInt aBusId) {return(DoControl(ECtlIoTestFullDuplexTrans, (TAny*)aBusId, (TAny*)ETestDiffNodeNoFullDuplexTrans));}
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   395
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   396
	inline void TestBufferReUse(TInt aBusId, TRequestStatus& aStatus) {DoRequest(ECtrlIoTestBufReUse,aStatus,(TAny*)aBusId,NULL);}
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   397
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   398
	inline TInt SimulateRxNWords(TInt aBusId, TInt aChannelId, TInt aNumWords){TInt parms[2]; parms[0]=aChannelId; parms[1]=aNumWords;return(DoControl(ECtrlIoRxWords,(TAny*)aBusId,(TAny*)(&parms[0])));};
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   399
	inline TInt SimulateTxNWords(TInt aBusId, TInt aChannelId, TInt aNumWords){TInt parms[2]; parms[0]=aChannelId; parms[1]=aNumWords;return(DoControl(ECtrlIoTxWords,(TAny*)aBusId,(TAny*)(&parms[0])));};
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   400
	inline TInt SimulateRxTxNWords(TInt aBusId, TInt aChannelId, TInt aNumRxWords, TInt aNumTxWords){TInt parms[3]; parms[0]=aChannelId; parms[1]=aNumRxWords; parms[2]=aNumTxWords;return(DoControl(ECtrlIoRxTxWords,(TAny*)aBusId,(TAny*)(&parms[0])));};
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   401
	inline TInt SimulateBusErr(TInt aBusId, TInt aChannelId) {return(DoControl(ECtlIoBusError,(TAny*)aBusId,(TAny*)aChannelId));}
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   402
	inline TInt BlockNotification(TInt aBusId, TInt aChannelId) {return(DoControl(ECtrlIoBlockNotification,(TAny*)aBusId,(TAny*)aChannelId));}
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   403
	inline TInt UnblockNotification(TInt aBusId, TInt aChannelId) {return(DoControl(ECtrlIoUnblockNotification,(TAny*)aBusId,(TAny*)aChannelId));}
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   404
	inline TInt UpdateTimeoutValues(TInt aBusId, TInt aChannelId) {return(DoControl(ECtrlIoUpdTimeout,(TAny*)aBusId,(TAny*)aChannelId));}
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   405
	inline TInt SetNotifNoTrigger(TInt aChannelId, TInt aTrigger){return(DoControl(ECtrlIoNotifNoTrigger,(TAny*)aChannelId,(TAny*)aTrigger));};
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   406
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   407
	inline void TestOverrunUnderrun(TInt aBusId, TInt aChannelId, TRequestStatus& aStatus) {DoRequest(ECtrlIoOvUndRunRxTx,aStatus,(TAny*)aBusId,(TAny*)aChannelId);}
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   408
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   409
#endif
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   410
	};
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diff changeset
   411
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   412
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   413
#ifdef __KERNEL_MODE__
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diff changeset
   414
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   415
// Definition of function prototype for a callback function provided by the PSL
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   416
// to be invoked when the part played by the hardware in processing a transfer
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   417
// has completed.
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   418
typedef void (*THwDoneCbFn)(TAny* );
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   419
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   420
#endif
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diff changeset
   421
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   422
// Data used to support tests
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   423
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   424
// Transaction One
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   425
//
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   426
const TUint8 KTransOneTferOne[21] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20};
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   427
const TUint8 KTransOneTferTwo[8] = {17,18,19,20,21,22,23,24};
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   428
const TUint8 KTransOneTferThree[6] = {87,85,83,81,79,77};
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   429
const TUint8 KPriorityTestHeader[6] = {0,1,2,3,4,10}; 
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   430
const TInt KPriorityTestPrio[6] = {1,2,3,4,5,0};
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   431
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   432
const TInt KRxBufSizeInBytes = 64;
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   433
const TInt KTxBufSizeInBytes = 64;
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   434
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   435
#endif