// Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies).

// All rights reserved.

// This component and the accompanying materials are made available

// under the terms of the License "Eclipse Public License v1.0"

// which accompanies this distribution, and is available

// at the URL "http://www.eclipse.org/legal/epl-v10.html".

//

// Initial Contributors:

// Nokia Corporation - initial contribution.

//

// Contributors:

//

// Description:

// e32\common\x86\atomics.cpp

// 

//

#include <e32atomics.h>

#include <cpudefs.h>

/*

Versions needed:

	WINS/WINSCW		Use X86 locked operations. Assume Pentium or above CPU (CMPXCHG8B available)

	X86				For Pentium and above use locked operations

					For 486 use locked operations for 8, 16, 32 bit. For 64 bit must disable interrupts.

					NOTE: 486 not supported at the moment

	ARMv4/ARMv5		Must disable interrupts.

	ARMv6			LDREX/STREX for 8, 16, 32 bit. For 64 bit must disable interrupts (maybe).

	ARMv6K/ARMv7	LDREXB/LDREXH/LDREX/LDREXD

Need both kernel side and user side versions

*/

#if	defined(__SMP__) || !defined(__EPOC32__)

#define	__BARRIERS_NEEDED__

#define	__LOCK__	lock

#else

#define	__LOCK__

#endif

extern "C" {

#undef	__TUintX__

#undef	__TIntX__

#undef	__fname__

#undef	__A_REG__

#undef	__C_REG__

#undef	__D_REG__

#define	__TUintX__		TUint32

#define	__TIntX__		TInt32

#define	__fname__(x)	x##32

#define	__A_REG__		eax

#define	__C_REG__		ecx

#define	__D_REG__		edx

#include "atomic_skeleton.h"

#undef	__TUintX__

#undef	__TIntX__

#undef	__fname__

#undef	__A_REG__

#undef	__C_REG__

#undef	__D_REG__

#define	__TUintX__		TUint16

#define	__TIntX__		TInt16

#define	__fname__(x)	x##16

#define	__A_REG__		ax

#define	__C_REG__		cx

#define	__D_REG__		dx

#include "atomic_skeleton.h"

#undef	__TUintX__

#undef	__TIntX__

#undef	__fname__

#undef	__A_REG__

#undef	__C_REG__

#undef	__D_REG__

#define	__TUintX__		TUint8

#define	__TIntX__		TInt8

#define	__fname__(x)	x##8

#define	__A_REG__		al

#define	__C_REG__		cl

#define	__D_REG__		dl

#include "atomic_skeleton.h"

#undef	__TUintX__

#undef	__TIntX__

#undef	__fname__

#undef	__A_REG__

#undef	__C_REG__

#undef	__D_REG__

/** Full memory barrier for explicit memory accesses

*/

EXPORT_C __NAKED__ void __e32_memory_barrier()

	{

#ifdef __BARRIERS_NEEDED__

	_asm lock add dword ptr [esp], 0

#endif

	_asm ret

	}

/** Barrier guaranteeing completion as well as ordering

*/

EXPORT_C __NAKED__ void __e32_io_completion_barrier()

	{

	_asm push ebx

	_asm cpuid

	_asm pop ebx

	_asm ret

	}

/** Find the most significant 1 in a 32 bit word

	@param	v	The word to be scanned

	@return		The bit number of the most significant 1 if v != 0

				-1 if v == 0

*/

EXPORT_C __NAKED__ TInt __e32_find_ms1_32(TUint32 /*v*/)

	{

	_asm bsr eax, [esp+4]

	_asm jnz short done

	_asm mov eax, 0ffffffffh

done:

	_asm ret

	}

/** Find the least significant 1 in a 32 bit word

	@param	v	The word to be scanned

	@return		The bit number of the least significant 1 if v != 0

				-1 if v == 0

*/

EXPORT_C __NAKED__ TInt __e32_find_ls1_32(TUint32 /*v*/)

	{

	_asm bsf eax, [esp+4]

	_asm jnz short done

	_asm mov eax, 0ffffffffh

done:

	_asm ret

	}

/** Count the number of 1's in a 32 bit word

	@param	v	The word to be scanned

	@return		The number of 1's

*/

EXPORT_C __NAKED__ TInt __e32_bit_count_32(TUint32 /*v*/)

	{

	_asm mov eax, [esp+4]

	_asm mov edx, eax

	_asm and eax, 0aaaaaaaah

	_asm and edx, 055555555h

	_asm shr eax, 1

	_asm add eax, edx

	_asm mov edx, eax

	_asm and eax, 0cccccccch

	_asm and edx, 033333333h

	_asm shr eax, 2

	_asm add eax, edx

	_asm mov edx, eax

	_asm shr eax, 4

	_asm add eax, edx

	_asm and eax, 00f0f0f0fh

	_asm add al, ah

	_asm mov dl, al

	_asm shr eax, 16

	_asm add al, ah

	_asm xor ah, ah

	_asm add al, dl

	_asm ret

	}

/** Find the most significant 1 in a 64 bit word

	@param	v	The word to be scanned

	@return		The bit number of the most significant 1 if v != 0

				-1 if v == 0

*/

EXPORT_C __NAKED__ TInt __e32_find_ms1_64(TUint64 /*v*/)

	{

	_asm bsr eax, [esp+8]

	_asm jnz short mswnz

	_asm bsr eax, [esp+4]

	_asm jnz short lswnz

	_asm mov eax, 0ffffffffh

mswnz:

	_asm or eax, 32

lswnz:

	_asm ret

	}

/** Find the least significant 1 in a 64 bit word

	@param	v	The word to be scanned

	@return		The bit number of the least significant 1 if v != 0

				-1 if v == 0

*/

EXPORT_C __NAKED__ TInt __e32_find_ls1_64(TUint64 /*v*/)

	{

	_asm bsf eax, [esp+4]

	_asm jnz short lswnz

	_asm bsf eax, [esp+8]

	_asm jnz short mswnz

	_asm mov eax, 0ffffffffh

mswnz:

	_asm or eax, 32

lswnz:

	_asm ret

	}

/** Count the number of 1's in a 64 bit word

	@param	v	The word to be scanned

	@return		The number of 1's

*/

EXPORT_C __NAKED__ TInt __e32_bit_count_64(TUint64 /*v*/)

	{

	_asm mov eax, [esp+4]

	_asm mov edx, [esp+8]

	_asm mov ecx, eax

	_asm and eax, 0aaaaaaaah

	_asm and ecx, 055555555h

	_asm shr eax, 1

	_asm add eax, ecx			/* 16 groups of 2 bits, count=0,1,2 */

	_asm mov ecx, eax

	_asm and eax, 0cccccccch

	_asm and ecx, 033333333h

	_asm shr eax, 2

	_asm add ecx, eax			/* 8 groups of 4 bits, count=0...4 */

	_asm mov eax, edx

	_asm and eax, 0aaaaaaaah

	_asm and edx, 055555555h

	_asm shr eax, 1

	_asm add eax, edx			/* 16 groups of 2 bits, count=0,1,2 */

	_asm mov edx, eax

	_asm and eax, 0cccccccch

	_asm and edx, 033333333h

	_asm shr eax, 2

	_asm add eax, edx			/* 8 groups of 4 bits, count=0...4 */

	_asm add eax, ecx			/* 8 groups of 4 bits, count=0...8 */

	_asm mov edx, eax

	_asm and eax, 0f0f0f0f0h

	_asm and edx, 00f0f0f0fh

	_asm shr eax, 4

	_asm add eax, edx			/* 4 groups of 8 bits, count=0...16 */

	_asm add al, ah

	_asm mov dl, al

	_asm shr eax, 16

	_asm add al, ah

	_asm xor ah, ah

	_asm add al, dl

	_asm ret

	}

/** Read a 64 bit word with acquire semantics

	@param	a	Address of word to be read - must be a multiple of 8

	@return		The value read

*/

EXPORT_C __NAKED__ TUint64	__e32_atomic_load_acq64(const volatile TAny* /*a*/)

	{

	_asm push ebx

	_asm push edi

	_asm mov edi, [esp+12]

	_asm mov eax, 0badbeefh

	_asm mov edx, eax

	_asm mov ebx, eax

	_asm mov ecx, eax

	_asm __LOCK__ cmpxchg8b [edi]

	_asm pop edi

	_asm pop ebx

	_asm ret

	}

/** Write a 64 bit word with release semantics

	@param	a	Address of word to be written - must be a multiple of 8

	@param	v	The value to be written

	@return		The value written

*/

EXPORT_C __NAKED__ TUint64	__e32_atomic_store_rel64(volatile TAny* /*a*/, TUint64 /*v*/)

	{

	_asm push ebx

	_asm push edi

	_asm mov edi, [esp+12]

	_asm mov ebx, [esp+16]

	_asm mov ecx, [esp+20]

	_asm mov eax, [edi]

	_asm mov edx, [edi+4]

	_asm retry:

	_asm __LOCK__ cmpxchg8b [edi]

	_asm jne short retry

	_asm mov eax, ebx

	_asm mov edx, ecx

	_asm pop edi

	_asm pop ebx

	_asm ret

	}

/** Write a 64 bit word with full barrier semantics

	@param	a	Address of word to be written - must be a multiple of 8

	@param	v	The value to be written

	@return		The value written

*/

EXPORT_C __NAKED__ TUint64	__e32_atomic_store_ord64(volatile TAny* /*a*/, TUint64 /*v*/)

	{

	_asm jmp __e32_atomic_store_rel64

	}

/** Write a 64 bit word to memory and return the original value of the memory.

	Relaxed ordering.

	@param	a	Address of word to be written - must be a multiple of 8

	@param	v	The value to be written

	@return		The original value of *a

*/

EXPORT_C __NAKED__ TUint64	__e32_atomic_swp_rlx64(volatile TAny* /*a*/, TUint64 /*v*/)

	{

	_asm jmp __e32_atomic_swp_ord64

	}

/** Write a 64 bit word to memory and return the original value of the memory.

	Acquire semantics.

	@param	a	Address of word to be written - must be a multiple of 8

	@param	v	The value to be written

	@return		The original value of *a

*/

EXPORT_C __NAKED__ TUint64	__e32_atomic_swp_acq64(volatile TAny* /*a*/, TUint64 /*v*/)

	{

	_asm jmp __e32_atomic_swp_ord64

	}

/** Write a 64 bit word to memory and return the original value of the memory.

	Release semantics.

	@param	a	Address of word to be written - must be a multiple of 8

	@param	v	The value to be written

	@return		The original value of *a

*/

EXPORT_C __NAKED__ TUint64	__e32_atomic_swp_rel64(volatile TAny* /*a*/, TUint64 /*v*/)

	{

	_asm jmp __e32_atomic_swp_ord64

	}

/** Write a 64 bit word to memory and return the original value of the memory.

	Full barrier semantics.

	@param	a	Address of word to be written - must be a multiple of 8

	@param	v	The value to be written

	@return		The original value of *a

*/

EXPORT_C __NAKED__ TUint64	__e32_atomic_swp_ord64(volatile TAny* /*a*/, TUint64 /*v*/)

	{

	_asm push ebx

	_asm push edi

	_asm mov edi, [esp+12]

	_asm mov ebx, [esp+16]

	_asm mov ecx, [esp+20]

	_asm mov eax, [edi]

	_asm mov edx, [edi+4]

	_asm retry:

	_asm __LOCK__ cmpxchg8b [edi]

	_asm jne short retry

	_asm pop edi

	_asm pop ebx

	_asm ret

	}

/** 64 bit compare and swap, relaxed ordering.

	Atomically performs the following operation:

		if (*a == *q)	{ *a = v; return TRUE; }

		else			{ *q = *a; return FALSE; }

	@param	a	Address of word to be written - must be a multiple of 8

	@param	q	Address of location containing expected value

	@param	v	The new value to be written if the old value is as expected

	@return		TRUE if *a was updated, FALSE otherwise

*/

EXPORT_C __NAKED__ TBool		__e32_atomic_cas_rlx64(volatile TAny* /*a*/, TUint64* /*q*/, TUint64 /*v*/)

	{

	_asm jmp __e32_atomic_cas_ord64

	}

/** 64 bit compare and swap, acquire semantics.

	Atomically performs the following operation:

		if (*a == *q)	{ *a = v; return TRUE; }

		else			{ *q = *a; return FALSE; }

	@param	a	Address of word to be written - must be a multiple of 8

	@param	q	Address of location containing expected value

	@param	v	The new value to be written if the old value is as expected

	@return		TRUE if *a was updated, FALSE otherwise

*/

EXPORT_C __NAKED__ TBool		__e32_atomic_cas_acq64(volatile TAny* /*a*/, TUint64* /*q*/, TUint64 /*v*/)

	{

	_asm jmp __e32_atomic_cas_ord64

	}

/** 64 bit compare and swap, release semantics.

	Atomically performs the following operation:

		if (*a == *q)	{ *a = v; return TRUE; }

		else			{ *q = *a; return FALSE; }

	@param	a	Address of word to be written - must be a multiple of 8

	@param	q	Address of location containing expected value

	@param	v	The new value to be written if the old value is as expected

	@return		TRUE if *a was updated, FALSE otherwise

*/

EXPORT_C __NAKED__ TBool		__e32_atomic_cas_rel64(volatile TAny* /*a*/, TUint64* /*q*/, TUint64 /*v*/)

	{

	_asm jmp __e32_atomic_cas_ord64

	}

/** 64 bit compare and swap, full barrier semantics.

	Atomically performs the following operation:

		if (*a == *q)	{ *a = v; return TRUE; }

		else			{ *q = *a; return FALSE; }

	@param	a	Address of word to be written - must be a multiple of 8

	@param	q	Address of location containing expected value

	@param	v	The new value to be written if the old value is as expected

	@return		TRUE if *a was updated, FALSE otherwise

*/

EXPORT_C __NAKED__ TBool		__e32_atomic_cas_ord64(volatile TAny* /*a*/, TUint64* /*q*/, TUint64 /*v*/)

	{

	_asm push ebx

	_asm push edi

	_asm push esi

	_asm mov edi, [esp+16]				// edi = a

	_asm mov esi, [esp+20]				// esi = q

	_asm mov ebx, [esp+24]				// ecx:ebx = v

	_asm mov ecx, [esp+28]

	_asm mov eax, [esi]					// edx:eax = *q

	_asm mov edx, [esi+4]

	_asm __LOCK__ cmpxchg8b [edi]		// if (*a==*q) *a=v, ZF=1 else edx:eax=*a, ZF=0

	_asm jne short cas_fail

	_asm mov eax, 1

	_asm pop esi

	_asm pop edi

	_asm pop ebx

	_asm ret

	_asm cas_fail:

	_asm mov [esi], eax					// *q = edx:eax

	_asm mov [esi+4], edx

	_asm xor eax, eax

	_asm pop esi

	_asm pop edi

	_asm pop ebx

	_asm ret

	}

/** 64 bit atomic add, relaxed ordering.

	Atomically performs the following operation:

		oldv = *a; *a = oldv + v; return oldv;

	@param	a	Address of word to be updated - must be a multiple of 8

	@param	v	The value to be added

	@return		The original value of *a

*/

EXPORT_C __NAKED__ TUint64	__e32_atomic_add_rlx64(volatile TAny* /*a*/, TUint64 /*v*/)

	{

	_asm jmp __e32_atomic_add_ord64

	}

/** 64 bit atomic add, acquire semantics.

	Atomically performs the following operation:

		oldv = *a; *a = oldv + v; return oldv;

	@param	a	Address of word to be updated - must be a multiple of 8

	@param	v	The value to be added

	@return		The original value of *a

*/

EXPORT_C __NAKED__ TUint64	__e32_atomic_add_acq64(volatile TAny* /*a*/, TUint64 /*v*/)

	{

	_asm jmp __e32_atomic_add_ord64

	}

/** 64 bit atomic add, release semantics.

	Atomically performs the following operation:

		oldv = *a; *a = oldv + v; return oldv;

	@param	a	Address of word to be updated - must be a multiple of 8

	@param	v	The value to be added

	@return		The original value of *a

*/

EXPORT_C __NAKED__ TUint64	__e32_atomic_add_rel64(volatile TAny* /*a*/, TUint64 /*v*/)

	{

	_asm jmp __e32_atomic_add_ord64

	}