bsptemplate/asspandvariant/template_variant/config.inc
author John Imhofe
Mon, 19 Oct 2009 15:55:17 +0100
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permissions -rw-r--r--
Convert Kernelhwsrv package from SFL to EPL kernel\eka\compsupp is subject to the ARM EABI LICENSE userlibandfileserver\fatfilenameconversionplugins\unicodeTables is subject to the Unicode license kernel\eka\kernel\zlib is subject to the zlib license
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; template\config.inc
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;
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; Copyright (c) 1998-2001 Symbian Ltd. All rights reserved.
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;
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; Template bootstrap configuration file
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; Include to enable tracing
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;	GBLL	CFG_DebugBootRom
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; Include one of these to select the CPU
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;	GBLL	CFG_CPU_GENERIC_ARM4
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;	GBLL	CFG_CPU_ARM710T
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;	GBLL	CFG_CPU_ARM720T
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;	GBLL	CFG_CPU_SA1
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;	GBLL	CFG_CPU_ARM920T
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;	GBLL	CFG_CPU_ARM925T
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;	GBLL	CFG_CPU_ARM926J
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;	GBLL	CFG_CPU_XSCALE
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;	GBLL	CFG_CPU_ARM1136
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	GBLL	CFG_CPU_ARM1176
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;	GBLL	CFG_CORTEX_A8
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; Include the following line if this is a bootloader bootstrap
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;	GBLL	CFG_BootLoader
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; TO DO:
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; The following line needs to be removed for target hardware
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	GBLL	CFG_Template
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; If you want to supply a custom set of initial vectors (including reset vector) include the following line
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;	GBLL	CFG_CustomVectors
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;
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; and provide a custom_vectors.inc file
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; Variant Number, just an example:
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	INIT_NUMERIC_CONSTANT	CFG_HWVD, 0x09080001
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; On ARM architecture 6 processors, include the following line to override the threshold
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; on total physical RAM size at which the multiple memory model switches into large address space mode
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; i.e. size>threshold -> 2Gb per process, size<=threshold -> 1Gb per process
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; Defaults to 32Mb.
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;	INIT_NUMERIC_CONSTANT	CFG_ARMV6_LARGE_CONFIG_THRESHOLD, <value>
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; For the direct memory model only, include the following line if you wish the exception vectors at the
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; start of the bootstrap to be used at all times. This is only relevant if an MMU is present - this option
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; is mandatory if not.
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;	GBLL	CFG_UseBootstrapVectors
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;
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; If the above option is in use (including if no MMU is present) the following symbol should be defined
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; to specify the offset from the bootstrap to the kernel image.
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	INIT_NUMERIC_CONSTANT	KernelCodeOffset, 0x4000
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; Include the following line if you wish to include the ROM autodetection code based on data bus
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; capacitance and image repeats.
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;	GBLL	CFG_AutoDetectROM
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; Include the following line to minimise the initial kernel heap size
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; On the direct memory model the size of the kernel data area (super page to end of kernel heap) 
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; is rounded up to the next 1Mb if this is not included, 4K if it is.
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; On the moving and multiple models, the size of the initial kernel heap area is rounded up to
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; the next 64K if this is not included, 4K if it is.
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;	GBLL	CFG_MinimiseKernelHeap
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; Include the following line if default memory mapping should use shared memory.
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; Should be defined on multicore (SMP) devices.
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;	GBLL	CFG_USE_SHARED_MEMORY
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; On the moving or multiple memory models, include either or both of the following lines to
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; specify the size of the initial kernel heap
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;	INIT_NUMERIC_CONSTANT	CFG_KernelHeapMultiplier, <multiplier>
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;	INIT_NUMERIC_CONSTANT	CFG_KernelHeapBaseSize, <base>
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;
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; The initial kernel heap size is MAX( <base> + <multiplier> * N / 16, value specified in ROMBUILD )
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; where N is the total physical RAM size in pages.
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; <base> defaults to 24K and <multiplier> defaults to 9*16 (ie 9 bytes per page).
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; Uncomment if using ARM1136 processor and ARM1136 Erratum 353494
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; "Rare conditions can cause corruption of the Instruction Cache"
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; is fixed on this hardware.
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;
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; NOTE: The boot table should use this macro to determine whether RONO or RORO permissions
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; are used for the exception vectors. If the erratum is not fixed, RORO must be used.
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;
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;	GBLL	CFG_CPU_ARM1136_ERRATUM_353494_FIXED
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; Uncomment if using ARM1136 processor and ARM1136 Erratum 364296
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; "Possible Cache Data Corruption with Hit-Under-Miss"
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; is fixed on this hardware.
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;
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;	GBLL	CFG_CPU_ARM1136_ERRATUM_364296_FIXED
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; Uncomment if using ARM1136 processor and ARM1136 Erratum 399234
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; "Write back data cache entry evicted by write through entry causes data corruption"
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; is fixed on this hardware.
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; Workaround
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; The erratum may be avoided by marking all cacheable memory as one of write through or write back.
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; This requires the memory attributes described in the translation tables to be modified by software
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; appropriately, or the use of the remapping capability to remap write through regions to non cacheable.
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;
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; If this macro is enabled, it should be accompanied by:
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; 		"macro __CPU_ARM1136_ERRATUM_399234_FIXED" in variant.mmh
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;	GBLL	CFG_CPU_ARM1136_ERRATUM_399234_FIXED
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; Uncomment if:
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;	1)	using ARM1136 processor and ARM1136 Erratum 411920: "Invalidate Entire Instruction Cache
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;	  	operation might fail to invalidate some lines if coincident with linefill"
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;  	  	is fixed on this hardware, or
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;	2)	using ARM1176 processor and ARM1176 Erratum 415045: "Invalidate Entire Instruction Cache
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; 	  	operation might fail to invalidate some lines if coincident with linefill
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;	  	is fixed on this hardware.
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; Workaround:
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;	1)	Disables the use of of prefetch range cache operations by setting RV bit in Auxiliary Ctrl Reg.
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;	2)	Replaces Invalidate ICache operation with the sequence defined in the errata document.
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; If this macro is enabled, it should be accompanied by:
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; 	"macro __CPU_ARM1136_ERRATUM_411920_FIXED" in variant.mmh
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;
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;	GBLL	CFG_CPU_ARM1136_ERRATUM_411920_FIXED
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; Uncomment if using ARM1136 processor and ARM1136 Erratum 415662: "Invalidate Instruction Cache by
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; Index might corrupt cache when used with background prefetch range" is fixed on this hardware.
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; Workaround:
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; 	Disables the use of of prefetch range cache operations by setting RV bit in Auxiliary Ctrl Reg.
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;
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;	GBLL	CFG_CPU_ARM1136_ERRATUM_415662_FIXED
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; These are deduced from the supplied configuration
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;	CFG_ARMV6
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;	CFG_MMUPresent
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;	CFG_CachePresent
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;	CFG_WriteBufferPresent
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;	CFG_SplitCache
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;	CFG_SplitTLB
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;	CFG_AltDCachePresent
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;	CFG_WriteBackCache
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;	CFG_CacheWriteAllocate
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;	CFG_CachePhysicalTag
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;	CFG_CacheFlushByDataRead
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;	CFG_CacheFlushByWaySetIndex
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;	CFG_CacheFlushByLineAlloc
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;	CFG_CachePolicyInPTE
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;	CFG_TEX
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;	CFG_SingleEntryDCacheFlush
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;	CFG_SingleEntryICacheFlush
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;	CFG_SingleEntryITLBFlush
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;	CFG_SingleEntryTLBFlush
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;	CFG_CacheTypeReg
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;	CFG_BTBPresent
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;	CFG_CARPresent
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;	CFG_PrefetchBuffer
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;	CFG_FCSE_Present
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;	CFG_ASID_Present
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;	CFG_IncludeRAMAllocator
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	END