kerneltest/e32test/realtime/d_latncy.cia
author Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
Wed, 09 Jun 2010 11:10:19 +0300
branchRCL_3
changeset 147 bbf8bed59bcb
parent 0 a41df078684a
permissions -rw-r--r--
Revision: 201023 Kit: 2010123
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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// Copyright (c) 1999-2009 Nokia Corporation and/or its subsidiary(-ies).
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// All rights reserved.
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// This component and the accompanying materials are made available
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// under the terms of the License "Eclipse Public License v1.0"
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// which accompanies this distribution, and is available
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// at the URL "http://www.eclipse.org/legal/epl-v10.html".
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//
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// Initial Contributors:
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// Nokia Corporation - initial contribution.
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//
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// Contributors:
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//
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// Description:
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// e32test\realtime\d_latncy.cia
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// 
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//
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#include <platform.h>
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#if defined(__MEIG__)
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#include <cl7211.h>
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#elif defined(__MAWD__)
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#include <windermere.h>
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#elif defined(__MISA__)
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#include <sa1100.h>
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#elif defined(__MCOT__)
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#include <cotulla.h>
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#elif defined(__MI920__) || defined(__NI1136__)
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#include <integratorap.h>
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#elif defined(__RVEMUBOARD__)
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#include <rvemuboard.h>
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#endif
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#include <kernel/kern_priv.h>		//temporary
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#include "d_latncy.h"
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#if !defined(__SMP__)
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#if !defined(__EPOC32__) || !defined(__CPU_X86)
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__NAKED__ TUint IntStackPtr()
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	{
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	asm("mrs r1, cpsr ");
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	asm("bic r3, r1, #0x1f ");
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#ifdef __MISA__
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	asm("orr r3, r3, #0xd1 ");		// mode_fiq, all interrupts off
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#else
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	asm("orr r3, r3, #0xd2 ");		// mode_irq, all interrupts off
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#endif
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	asm("msr cpsr, r3 ");
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	asm("mov r0, sp ");				// r0=sp_irq or sp_fiq
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	asm("msr cpsr, r1 ");			// restore interrupts
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	__JUMP(,lr);
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	}
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#endif
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#ifdef __CAPTURE_EXTRAS
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#include <arm.h>
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__NAKED__ void CaptureExtras(SLatencyResults&)
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	{
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	asm("mrs r1, spsr ");			// r1=interrupted mode
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	asm("mrs r2, cpsr ");			// r2=current PSR
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	asm("tst r1, #0x0f ");			// check if we interrupted user mode
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	asm("orr ip, r1, #%a0" : : "i" ((TInt)KAllInterruptsMask));		// ip=interrupted mode with interrupts off
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	asm("orreq ip, ip, #0x1f ");	// if we interrupted user mode, go to system mode instead
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	asm("bic ip, ip, #0x20 ");		// make sure we don't go into THUMB mode
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	asm("msr cpsr, ip ");			// switch to interrupted mode with ints off
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	asm("mov r3, lr ");				// r3=interrupted mode R14
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	asm("msr cpsr, r2 ");			// back to interrupt mode
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	asm("str r1, [r0, #%a0]" : : "i" _FOFF(SLatencyResults,iIntSpsr));
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	asm("str r3, [r0, #%a0]" : : "i" _FOFF(SLatencyResults,iIntR14));
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	__JUMP(,lr);
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	}
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#endif
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#endif	// __SMP__
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#if defined (__MISA__) || defined (__MCOT__)
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__NAKED__ void DLatency::MsCallBack(TAny* aPtr)
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	{
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	asm("ldr ip, __KHwBaseOst");
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	asm("ldr r3, [r0, #%a0]" : : "i" _FOFF(DLatency,iTickIncrement));
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	asm("ldr r1, [ip, #0x10] ");		// r1=OSCR
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	asm("ldr r2, [ip, #0x00] ");		// r2=OSMR0
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	asm("sub r1, r1, r2 ");				// r1=int latency in ticks
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	asm("str r1, [r0, #%a0]" : : "i" _FOFF(DLatency,iResults.iIntTicks));
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	asm("str r2, [r0, #%a0]" : : "i" _FOFF(DLatency,iTriggerTime));
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	asm("add r2, r2, r3 ");				// add increment to OSMR0
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	asm("ldr r1, [r0, #%a0]" : : "i" _FOFF(DLatency,iIntStackTop));
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	asm("ldrb r3, [r0, #%a0]" : : "i" _FOFF(DLatency,iOff));
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	asm("str r2, [ip, #0x00] ");
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	asm("ldr r1, [r1, #-4] ");			// r1=interrupt return address
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	asm("mov r2, #1 ");
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	asm("cmp r3, #0 ");
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	asm("str r1, [r0, #%a0]" : : "i" _FOFF(DLatency,iResults.iIntRetAddr));
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	asm("str r2, [ip, #0x14] ");		// clear interrupt
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	asm("add r0, r0, #%a0" : : "i" _FOFF(DLatency,iMsDfc));
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	asm("beq Add__4TDfc ");
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	__JUMP(,lr);
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	asm("__KHwBaseOst: ");	//OS timer register locations
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#ifdef __MISA__
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	#ifdef __MEMMODEL_DIRECT__
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		asm(".word 0x90000000");		//Assabet direct MM
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	#else
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		asm(".word 0x63008000");		//Assabet non-direct MM
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	#endif
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#else
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	#ifdef __MEMMODEL_DIRECT__
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		asm(".word 0x40A00000");		//Lubbock direct MM
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	#else
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		asm(".word 0x6300A000");		//Lubbock non-direct MM
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	#endif
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#endif
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	}
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#endif
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