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// Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies).
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// All rights reserved.
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// This component and the accompanying materials are made available
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// under the terms of the License "Eclipse Public License v1.0"
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// which accompanies this distribution, and is available
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// at the URL "http://www.eclipse.org/legal/epl-v10.html".
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//
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// Initial Contributors:
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// Nokia Corporation - initial contribution.
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//
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// Contributors:
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//
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// Description:
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// e32\nkernsmp\arm\ncirq.cia
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//
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//
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/**
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@file
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@internalTechnology
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*/
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#include "nk_priv.h"
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#include "nk_plat.h"
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#include <nk_irq.h>
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#include <arm.h>
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#include <arm_gic.h>
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#include <arm_scu.h>
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#include <arm_tmr.h>
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//
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// Atomically increment run count provided ECount set or count <2.
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// If originally zero, atomically set CPU field
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// Wait for EWait to be clear
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// Return state of iIState immediately before increment
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//
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__NAKED__ TUint32 NIrq::EnterIsr()
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{
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GET_RWNO_TID(,r12);
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asm("add r3, r0, #%a0" : : "i" _FOFF(NIrq,iIState));
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asm("ldr r12, [r12, #%a0]" : : "i" _FOFF(TSubScheduler,iCpuNum));
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asm("1: ");
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LDREX(0,3);
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asm("mov r1, r0 ");
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asm("cmp r0, #0x10000 "); // run count >= 1 ?
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asm("biclo r1, r1, #0xff00 "); // if not, update CPU
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asm("orrlo r1, r1, r12, lsl #8 ");
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asm("add r1, r1, #0x10000 "); // increment run count
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asm("cmp r1, #0x20000 "); // >= 2 ?
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asm("bhs 3f ");
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asm("2: ");
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STREX(2,1,3);
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asm("cmp r2, #0 ");
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asm("bne 1b ");
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asm("4: ");
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__DATA_MEMORY_BARRIER__(r2);
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asm("tst r1, #%a0" : : "i" (NIrq::EWait));
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asm("bne 5f ");
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__JUMP(,lr);
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asm("3: ");
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asm("tst r1, #%a0" : : "i" (NIrq::ECount|NIrq::ERaw));
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asm("bne 2b ");
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asm("mov r2, #0 ");
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asm("b 4b ");
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asm("5: ");
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ARM_WFE;
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asm("ldr r1, [r3] ");
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asm("b 4b ");
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}
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//
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// Atomically decrement run count
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// Return TRUE if run count nonzero after decrement
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//
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__NAKED__ TBool NIrq::IsrDone()
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{
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asm("add r3, r0, #%a0" : : "i" _FOFF(NIrq,iIState));
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__DATA_MEMORY_BARRIER_Z__(r2);
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asm("1: ");
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LDREX(0,3);
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asm("subs r1, r0, #0x10000 ");
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STREX(2,1,3);
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asm("cmp r2, #0 ");
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asm("bne 1b ");
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asm("mov r0, r1, lsr #16 "); // r0 = new run count = TRUE if nonzero
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__JUMP(,lr);
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}
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//
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// Wait (allowing interrupts and preemption) until run count = 0 and EWait clear
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// Then atomically set EWait and return with interrupts disabled
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//
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__NAKED__ void NIrq::Wait()
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{
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asm("add r3, r0, #%a0" : : "i" _FOFF(NIrq,iIState));
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asm("0: ");
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__ASM_CLI();
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asm("1: ");
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LDREX(0,3);
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asm("mov r1, r0, ror #1 "); // bit 31 = wait, bits 15-30 = run count
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asm("cmp r1, #0x8000 "); // run count and EWait both zero?
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asm("bcs 2f "); // if not, must wait
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asm("orr r1, r0, #1 "); // else try to set EWait
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STREX(2,1,3);
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asm("cmp r2, #0 ");
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asm("bne 1b ");
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__DATA_MEMORY_BARRIER__(r2);
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__JUMP(,lr); // success - return with interrupts disabled
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// spin, allowing interrupts, while we wait for run count and EWait both zero
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asm("2: ");
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__ASM_STI();
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asm("nop ");
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ARM_WFE;
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asm("nop ");
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asm("b 0b ");
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}
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//
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// Atomically clear EWait and reenable interrupts
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//
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__NAKED__ void NIrq::Done()
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{
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asm("add r3, r0, #%a0" : : "i" _FOFF(NIrq,iIState));
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__DATA_MEMORY_BARRIER_Z__(r2);
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asm("1: ");
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LDREX(0,3);
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asm("bic r0, r0, #1 "); // clear EWait
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STREX(2,0,3);
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asm("cmp r2, #0 ");
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asm("bne 1b ");
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__DATA_SYNC_BARRIER__(r2); // ensure completion before SEV
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ARM_SEV; // kick any waiting processors
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__ASM_STI(); // interrupts back on
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__JUMP(,lr);
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}
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//
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// atomic { if !EUnbind && !ENotReady clear EDisable }
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// Return the initial value of iHState
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//
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__NAKED__ TUint32 NIrqHandler::DoSetEnabled()
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{
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asm("add r3, r0, #%a0" : : "i" _FOFF(NIrqHandler,iHState));
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__DATA_MEMORY_BARRIER_Z__(r2);
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asm("1: ");
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LDREX(0,3);
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asm("tst r0, #%a0" : : "i" (NIrqHandler::EUnbind|NIrqHandler::ENotReady));
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asm("bne 2f "); // if EUnbind or ENotReady, finished
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asm("bic r1, r0, #%a0" : : "i" (NIrqHandler::EDisable|NIrqHandler::EBind));
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STREX(2,1,3);
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asm("cmp r2, #0 ");
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asm("bne 1b ");
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asm("2: ");
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__DATA_MEMORY_BARRIER__(r2);
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__JUMP(,lr);
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}
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//
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// Atomically increment run count by aCount if ECount set or run count initially zero.
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// If !EDisable and !EUnbind set EActive
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// Return initial iHState
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//
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__NAKED__ TUint32 NIrqHandler::DoActivate(TInt /*aCount*/)
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{
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asm("add r3, r0, #%a0" : : "i" _FOFF(NIrqHandler,iHState));
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asm("1: ");
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LDREX(0,3);
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asm("mov r2, r0 ");
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asm("cmp r0, #0x10000 ");
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asm("blo 2f "); // if run count initially zero, skip
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asm("tst r0, #%a0" : : "i" (NIrqHandler::ECount));
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asm("beq 3f "); // else if !ECount, don't increment
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asm("2: ");
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asm("add r2, r2, r1, lsl #16 "); // add aCount to run count
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asm("3: ");
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asm("tst r2, #%a0" : : "i" (NIrqHandler::EUnbind|NIrqHandler::EDisable));
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asm("orreq r2, r2, #%a0" : : "i" (NIrqHandler::EActive)); // if !EUnbind && !EDisable, set EActive
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STREX(12,2,3);
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asm("cmp r12, #0 ");
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asm("bne 1b ");
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__DATA_MEMORY_BARRIER__(r12);
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__JUMP(,lr);
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}
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//
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// Decrement run count
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// Return initial iHState
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//
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__NAKED__ TUint32 NIrqHandler::EventBegin()
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{
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asm("add r3, r0, #%a0" : : "i" _FOFF(NIrqHandler,iHState));
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asm("1: ");
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LDREX(0,3);
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asm("sub r2, r0, #0x10000 ");
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STREX(12,2,3);
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asm("cmp r12, #0 ");
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asm("bne 1b ");
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__DATA_MEMORY_BARRIER__(r12);
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__JUMP(,lr);
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}
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//
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// If count is zero or EDisable or EUnbind
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// are set, clear EActive.
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// Return initial iHState, except for new EActive bit
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//
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__NAKED__ TUint32 NIrqHandler::EventDone()
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{
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asm("add r3, r0, #%a0" : : "i" _FOFF(NIrqHandler,iHState));
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__DATA_MEMORY_BARRIER_Z__(r12);
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asm("1: ");
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LDREX(0,3);
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asm("mov r2, r0 ");
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asm("cmp r0, #0x10000 "); // run count zero ?
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asm("tsths r2, #%a0" : : "i" (NIrqHandler::EUnbind|NIrqHandler::EDisable)); // if so, test EUnbind and EDisable
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asm("bicne r2, r2, #%a0" : : "i" (NIrqHandler::EActive)); // if runcount==0 or EUnbind or EDisable set, clear EActive
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STREX(12,2,3);
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asm("cmp r12, #0 ");
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asm("bne 1b ");
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asm("tst r2, #%a0" : : "i" (NIrqHandler::EActive)); // EActive now clear in new value ?
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asm("biceq r0, r0, #%a0" : : "i" (NIrqHandler::EActive)); // if so, clear it in return value
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__JUMP(,lr);
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}
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