author | Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com> |
Wed, 18 Aug 2010 11:08:29 +0300 | |
changeset 247 | d8d70de2bd36 |
parent 201 | 43365a9b78a3 |
permissions | -rw-r--r-- |
0 | 1 |
// Copyright (c) 1998-2009 Nokia Corporation and/or its subsidiary(-ies). |
2 |
// All rights reserved. |
|
3 |
// This component and the accompanying materials are made available |
|
4 |
// under the terms of the License "Eclipse Public License v1.0" |
|
5 |
// which accompanies this distribution, and is available |
|
6 |
// at the URL "http://www.eclipse.org/legal/epl-v10.html". |
|
7 |
// |
|
8 |
// Initial Contributors: |
|
9 |
// Nokia Corporation - initial contribution. |
|
10 |
// |
|
11 |
// Contributors: |
|
12 |
// |
|
13 |
// Description: |
|
14 |
// |
|
15 |
||
16 |
#include "memmodel.h" |
|
17 |
#include "kernel/cache_maintenance.inl" |
|
18 |
#include <kernel/cache.h> |
|
19 |
#include <ramalloc.h> |
|
20 |
#include <defrag.h> |
|
21 |
#include "mm.h" |
|
22 |
#include "mmu.h" |
|
23 |
#include "mpager.h" |
|
24 |
#include "mmapping.h" |
|
25 |
#include "mobject.h" |
|
26 |
#include "mmanager.h" |
|
27 |
#include "mpagearray.h" |
|
28 |
||
29 |
||
30 |
// |
|
31 |
// SPageInfo |
|
32 |
// |
|
33 |
||
34 |
// check enough space for page infos... |
|
35 |
__ASSERT_COMPILE((KPageInfoLinearEnd-KPageInfoLinearBase)/sizeof(SPageInfo)==(1<<(32-KPageShift))); |
|
36 |
||
37 |
// check KPageInfoShift... |
|
38 |
__ASSERT_COMPILE(sizeof(SPageInfo)==(1<<KPageInfoShift)); |
|
39 |
||
40 |
||
41 |
SPageInfo* SPageInfo::SafeFromPhysAddr(TPhysAddr aAddress) |
|
42 |
{ |
|
43 |
__NK_ASSERT_DEBUG((aAddress&KPageMask)==0); |
|
44 |
TUint index = aAddress>>(KPageShift+KPageShift-KPageInfoShift); |
|
45 |
TUint flags = ((TUint8*)KPageInfoMap)[index>>3]; |
|
46 |
TUint mask = 1<<(index&7); |
|
47 |
if(!(flags&mask)) |
|
48 |
return 0; // no SPageInfo for aAddress |
|
49 |
SPageInfo* info = FromPhysAddr(aAddress); |
|
50 |
if(info->iType==SPageInfo::EInvalid) |
|
51 |
return 0; |
|
52 |
return info; |
|
53 |
} |
|
54 |
||
55 |
||
56 |
#ifdef _DEBUG |
|
57 |
||
58 |
void SPageInfo::CheckAccess(const char* aMessage, TUint aFlags) |
|
59 |
{ |
|
60 |
if(K::Initialising || NKern::Crashed()) |
|
61 |
return; |
|
62 |
||
63 |
if((aFlags&ECheckNotAllocated) && (iType!=EUnknown)) |
|
64 |
{ |
|
65 |
Kern::Printf("SPageInfo[0x%08x]::CheckAccess failed, PhysAddr()=0x%08x, iType==%d : %s",this,PhysAddr(),iType,aMessage); |
|
66 |
__NK_ASSERT_DEBUG(0); |
|
67 |
goto fail; |
|
68 |
} |
|
69 |
||
70 |
if((aFlags&ECheckNotUnused) && (iType==EUnused)) |
|
71 |
{ |
|
72 |
Kern::Printf("SPageInfo[0x%08x]::CheckAccess failed, PhysAddr()=0x%08x, iType==%d : %s",this,PhysAddr(),iType,aMessage); |
|
73 |
__NK_ASSERT_DEBUG(0); |
|
74 |
goto fail; |
|
75 |
} |
|
76 |
||
77 |
if((aFlags&ECheckUnused) && (iType!=EUnused)) |
|
78 |
{ |
|
79 |
Kern::Printf("SPageInfo[0x%08x]::CheckAccess failed, PhysAddr()=0x%08x, iType==%d : %s",this,PhysAddr(),iType,aMessage); |
|
80 |
__NK_ASSERT_DEBUG(0); |
|
81 |
goto fail; |
|
82 |
} |
|
83 |
||
84 |
if((aFlags&ECheckNotPaged) && (iPagedState!=EUnpaged)) |
|
85 |
{ |
|
86 |
Kern::Printf("SPageInfo[0x%08x]::CheckAccess failed, PhysAddr()=0x%08x, iPagedState=%d : %s",this,PhysAddr(),iPagedState,aMessage); |
|
87 |
__NK_ASSERT_DEBUG(0); |
|
88 |
goto fail; |
|
89 |
} |
|
90 |
||
91 |
if((aFlags&ECheckRamAllocLock) && !RamAllocLock::IsHeld()) |
|
92 |
{ |
|
93 |
Kern::Printf("SPageInfo[0x%08x]::CheckAccess failed, PhysAddr()=0x%08x, iType==%d : %s",this,PhysAddr(),iType,aMessage); |
|
94 |
__NK_ASSERT_DEBUG(0); |
|
95 |
goto fail; |
|
96 |
} |
|
97 |
||
98 |
if((aFlags&ENoCheckMmuLock) || MmuLock::IsHeld()) |
|
99 |
return; |
|
100 |
fail: |
|
101 |
Kern::Printf("SPageInfo[0x%08x]::CheckAccess failed, PhysAddr()=0x%08x : %s",this,PhysAddr(),aMessage); |
|
102 |
Mmu::Panic(Mmu::EUnsafePageInfoAccess); |
|
103 |
} |
|
104 |
||
105 |
||
106 |
void SPageInfo::Dump() |
|
107 |
{ |
|
108 |
Kern::Printf("SPageInfo for page %x = %d,%d,%02x,0x%08x,0x%x,%d",PhysAddr(),iType,iPagedState,iFlags,iOwner,iIndex,iPinCount); |
|
109 |
} |
|
110 |
||
111 |
#endif |
|
112 |
||
113 |
||
114 |
||
115 |
// |
|
116 |
// SPageTableInfo |
|
117 |
// |
|
118 |
||
119 |
// check enough space for page table infos... |
|
120 |
__ASSERT_COMPILE((KPageTableInfoEnd-KPageTableInfoBase)/sizeof(SPageTableInfo) |
|
121 |
>=(KPageTableEnd-KPageTableBase)/KPageTableSize); |
|
122 |
||
123 |
// check KPtBlockShift... |
|
124 |
__ASSERT_COMPILE((sizeof(SPageTableInfo)<<KPtBlockShift)==KPageSize); |
|
125 |
||
126 |
||
127 |
#ifdef _DEBUG |
|
128 |
||
129 |
TBool SPageTableInfo::CheckPageCount() |
|
130 |
{ |
|
131 |
__NK_ASSERT_DEBUG(MmuLock::IsHeld()); |
|
132 |
TPte* pt = PageTable(); |
|
133 |
TUint realCount = 0; |
|
134 |
do if(*pt++) ++realCount; |
|
135 |
while(TLinAddr(pt)&(KPageTableMask/sizeof(TPte)*sizeof(TPte))); |
|
136 |
if(iPageCount==realCount) |
|
137 |
return true; |
|
138 |
Kern::Printf("CheckPageCount Failed: pt=0x%08x count=%d realCount=%d",TLinAddr(pt)-KPageTableSize,iPageCount,realCount); |
|
139 |
return false; |
|
140 |
} |
|
141 |
||
142 |
||
143 |
void SPageTableInfo::CheckChangeUse(const char* aName) |
|
144 |
{ |
|
145 |
if(K::Initialising) |
|
146 |
return; |
|
147 |
if(PageTablesLockIsHeld() && MmuLock::IsHeld()) |
|
148 |
return; |
|
149 |
Kern::Printf("SPageTableInfo::CheckChangeUse failed : %s",aName); |
|
150 |
Mmu::Panic(Mmu::EUnsafePageTableInfoAccess); |
|
151 |
} |
|
152 |
||
153 |
||
154 |
void SPageTableInfo::CheckCheckUse(const char* aName) |
|
155 |
{ |
|
156 |
if(K::Initialising) |
|
157 |
return; |
|
158 |
if(PageTablesLockIsHeld() || MmuLock::IsHeld()) |
|
159 |
return; |
|
160 |
Kern::Printf("SPageTableInfo::CheckCheckUse failed : %s",aName); |
|
161 |
Mmu::Panic(Mmu::EUnsafePageTableInfoAccess); |
|
162 |
} |
|
163 |
||
164 |
||
165 |
void SPageTableInfo::CheckAccess(const char* aName) |
|
166 |
{ |
|
167 |
if(K::Initialising) |
|
168 |
return; |
|
169 |
if(MmuLock::IsHeld()) |
|
170 |
return; |
|
171 |
Kern::Printf("SPageTableInfo::CheckAccess failed : %s",aName); |
|
172 |
Mmu::Panic(Mmu::EUnsafePageTableInfoAccess); |
|
173 |
} |
|
174 |
||
175 |
||
176 |
void SPageTableInfo::CheckInit(const char* aName) |
|
177 |
{ |
|
178 |
if(K::Initialising) |
|
179 |
return; |
|
180 |
if(PageTablesLockIsHeld() && iType==EUnused) |
|
181 |
return; |
|
182 |
Kern::Printf("SPageTableInfo::CheckInit failed : %s",aName); |
|
183 |
Mmu::Panic(Mmu::EUnsafePageTableInfoAccess); |
|
184 |
} |
|
185 |
||
186 |
#endif |
|
187 |
||
188 |
||
189 |
||
190 |
// |
|
191 |
// RamAllocLock |
|
192 |
// |
|
193 |
||
194 |
_LIT(KLitRamAlloc,"RamAlloc"); |
|
195 |
_LIT(KLitPhysMemSync,"PhysMemSync"); |
|
196 |
||
197 |
void RamAllocLock::Lock() |
|
198 |
{ |
|
199 |
Mmu& m = TheMmu; |
|
200 |
Kern::MutexWait(*m.iRamAllocatorMutex); |
|
201 |
if(!m.iRamAllocLockCount++) |
|
202 |
{ |
|
203 |
// first lock, so setup memory fail data... |
|
204 |
m.iRamAllocFailed = EFalse; |
|
205 |
__NK_ASSERT_DEBUG(m.iRamAllocInitialFreePages==m.FreeRamInPages()); // free RAM shouldn't have changed whilst lock was held |
|
206 |
} |
|
207 |
} |
|
208 |
||
209 |
||
210 |
void RamAllocLock::Unlock() |
|
211 |
{ |
|
212 |
Mmu& m = TheMmu; |
|
213 |
if(--m.iRamAllocLockCount) |
|
214 |
{ |
|
215 |
Kern::MutexSignal(*m.iRamAllocatorMutex); |
|
216 |
return; |
|
217 |
} |
|
218 |
TBool failed = m.iRamAllocFailed; |
|
219 |
TUint initial = m.iRamAllocInitialFreePages; |
|
220 |
TUint final = m.FreeRamInPages(); |
|
221 |
m.iRamAllocInitialFreePages = final; // new baseline value |
|
222 |
TUint changes = K::CheckFreeMemoryLevel(initial*KPageSize,final*KPageSize,failed); |
|
223 |
if(changes) |
|
224 |
{ |
|
225 |
__KTRACE_OPT(KMMU,Kern::Printf("RamAllocLock::Unlock() changes=%x",changes)); |
|
226 |
} |
|
227 |
Kern::MutexSignal(*m.iRamAllocatorMutex); |
|
228 |
} |
|
229 |
||
230 |
||
231 |
TBool RamAllocLock::Flash() |
|
232 |
{ |
|
233 |
Unlock(); |
|
234 |
Lock(); |
|
235 |
return true; // lock was released |
|
236 |
} |
|
237 |
||
238 |
||
239 |
TBool RamAllocLock::IsHeld() |
|
240 |
{ |
|
241 |
Mmu& m = TheMmu; |
|
242 |
return m.iRamAllocatorMutex->iCleanup.iThread == &Kern::CurrentThread() && m.iRamAllocLockCount; |
|
243 |
} |
|
244 |
||
245 |
||
246 |
||
247 |
// |
|
248 |
// MmuLock |
|
249 |
// |
|
250 |
||
251 |
#ifdef _DEBUG |
|
252 |
TUint MmuLock::UnlockGuardNest =0; |
|
253 |
TUint MmuLock::UnlockGuardFail =0; |
|
254 |
#endif |
|
255 |
||
256 |
NFastMutex MmuLock::iLock; |
|
257 |
||
258 |
void MmuLock::Lock() |
|
259 |
{ |
|
260 |
NKern::FMWait(&iLock); |
|
261 |
} |
|
262 |
||
263 |
void MmuLock::Unlock() |
|
264 |
{ |
|
265 |
UnlockGuardCheck(); |
|
266 |
NKern::FMSignal(&iLock); |
|
267 |
} |
|
268 |
||
269 |
TBool MmuLock::Flash() |
|
270 |
{ |
|
271 |
UnlockGuardCheck(); |
|
272 |
return NKern::FMFlash(&iLock); |
|
273 |
} |
|
274 |
||
275 |
TBool MmuLock::IsHeld() |
|
276 |
{ |
|
277 |
NFastMutex& m = iLock; |
|
278 |
return m.HeldByCurrentThread(); |
|
279 |
} |
|
280 |
||
281 |
||
282 |
||
283 |
// |
|
284 |
// Initialisation |
|
285 |
// |
|
286 |
||
287 |
Mmu TheMmu; |
|
288 |
||
289 |
void Mmu::Init1Common() |
|
290 |
{ |
|
291 |
__KTRACE_OPT2(KBOOT,KMMU,Kern::Printf("Mmu::Init1Common")); |
|
292 |
||
293 |
// Mmu data |
|
294 |
TUint pteType = PteType(ESupervisorReadWrite,true); |
|
295 |
iTempPteCached = BlankPte((TMemoryAttributes)(EMemoryAttributeNormalCached|EMemoryAttributeDefaultShareable),pteType); |
|
296 |
iTempPteUncached = BlankPte((TMemoryAttributes)(EMemoryAttributeNormalUncached|EMemoryAttributeDefaultShareable),pteType); |
|
297 |
iTempPteCacheMaintenance = BlankPte((TMemoryAttributes)(CacheMaintenance::TemporaryMapping()|EMemoryAttributeDefaultShareable),pteType); |
|
298 |
||
299 |
// other |
|
300 |
PP::MaxUserThreadStack=0x14000; // 80K - STDLIB asks for 64K for PosixServer!!!! |
|
301 |
PP::UserThreadStackGuard=0x2000; // 8K |
|
302 |
PP::MaxStackSpacePerProcess=0x200000; // 2Mb |
|
303 |
K::SupervisorThreadStackSize=0x1000; // 4K |
|
304 |
PP::SupervisorThreadStackGuard=0x1000; // 4K |
|
305 |
K::MachineConfig=(TMachineConfig*)KMachineConfigLinAddr; |
|
306 |
PP::RamDriveStartAddress=0; |
|
307 |
PP::RamDriveRange=0; |
|
308 |
PP::RamDriveMaxSize=0x20000000; // 512MB, probably will be reduced later |
|
309 |
K::MemModelAttributes=EMemModelTypeFlexible|EMemModelAttrNonExProt|EMemModelAttrKernProt|EMemModelAttrWriteProt| |
|
310 |
EMemModelAttrVA|EMemModelAttrProcessProt|EMemModelAttrSameVA|EMemModelAttrSvKernProt| |
|
311 |
EMemModelAttrIPCKernProt|EMemModelAttrRamCodeProt; |
|
312 |
} |
|
313 |
||
314 |
||
102
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
315 |
#ifdef FMM_VERIFY_RAM |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
316 |
// Attempt to write to each unused RAM page and verify the contents. |
0 | 317 |
void Mmu::VerifyRam() |
318 |
{ |
|
319 |
Kern::Printf("Mmu::VerifyRam() pass 1"); |
|
320 |
RamAllocLock::Lock(); |
|
321 |
||
322 |
TPhysAddr p = 0; |
|
323 |
do |
|
324 |
{ |
|
325 |
SPageInfo* pi = SPageInfo::SafeFromPhysAddr(p); |
|
326 |
if(pi) |
|
327 |
{ |
|
328 |
Kern::Printf("%08x %d",p,pi->Type()); |
|
329 |
if(pi->Type()==SPageInfo::EUnused) |
|
330 |
{ |
|
331 |
volatile TPhysAddr* b = (volatile TPhysAddr*)MapTemp(p,0); |
|
332 |
b[0] = p; |
|
333 |
b[1] = ~p; |
|
334 |
__NK_ASSERT_DEBUG(b[0]==p); |
|
335 |
__NK_ASSERT_DEBUG(b[1]==~p); |
|
336 |
UnmapTemp(); |
|
337 |
} |
|
338 |
} |
|
339 |
p += KPageSize; |
|
340 |
} |
|
341 |
while(p); |
|
342 |
||
343 |
TBool fail = false; |
|
344 |
Kern::Printf("Mmu::VerifyRam() pass 2"); |
|
345 |
do |
|
346 |
{ |
|
347 |
SPageInfo* pi = SPageInfo::SafeFromPhysAddr(p); |
|
348 |
if(pi) |
|
349 |
{ |
|
350 |
if(pi->Type()==SPageInfo::EUnused) |
|
351 |
{ |
|
352 |
volatile TPhysAddr* b = (volatile TPhysAddr*)MapTemp(p,0); |
|
353 |
if(b[0]!=p || b[1]!=~p) |
|
354 |
{ |
|
355 |
fail = true; |
|
356 |
Kern::Printf("%08x FAILED %x %x",b[0],b[1]); |
|
357 |
} |
|
358 |
UnmapTemp(); |
|
359 |
} |
|
360 |
} |
|
361 |
p += KPageSize; |
|
362 |
} |
|
363 |
while(p); |
|
364 |
||
365 |
__NK_ASSERT_DEBUG(!fail); |
|
366 |
RamAllocLock::Unlock(); |
|
367 |
} |
|
368 |
#endif |
|
369 |
||
370 |
||
371 |
void Mmu::Init2Common() |
|
372 |
{ |
|
373 |
__KTRACE_OPT2(KBOOT,KMMU,Kern::Printf("Mmu::Init2Common")); |
|
374 |
||
375 |
// create allocator... |
|
376 |
const SRamInfo& info = *(const SRamInfo*)TheSuperPage().iRamBootData; |
|
377 |
iRamPageAllocator = DRamAllocator::New(info, iRamZones, iRamZoneCallback); |
|
378 |
||
379 |
// initialise all pages in banks as unused... |
|
380 |
const SRamBank* bank = info.iBanks; |
|
381 |
while(bank->iSize) |
|
382 |
{ |
|
383 |
TUint32 base = bank->iBase; |
|
384 |
TUint32 size = bank->iSize; |
|
385 |
__KTRACE_OPT2(KBOOT,KMMU,Kern::Printf("Found RAM bank 0x%08x size %d",base,size)); |
|
386 |
if(base+size<=base || ((base|size)&KPageMask)) |
|
387 |
Panic(EInvalidRamBankAtBoot); |
|
388 |
||
389 |
SPageInfo* pi = SPageInfo::FromPhysAddr(base); |
|
390 |
SPageInfo* piEnd = pi+(size>>KPageShift); |
|
391 |
while(pi<piEnd) |
|
392 |
(pi++)->SetUnused(); |
|
393 |
++bank; |
|
394 |
} |
|
395 |
// step over the last bank to get to the reserved banks. |
|
396 |
++bank; |
|
397 |
// mark any reserved regions as allocated... |
|
398 |
while(bank->iSize) |
|
399 |
{ |
|
400 |
TUint32 base = bank->iBase; |
|
401 |
TUint32 size = bank->iSize; |
|
402 |
__KTRACE_OPT2(KBOOT,KMMU,Kern::Printf("Found reserved bank 0x%08x size %d",base,size)); |
|
403 |
if(base+size<=base || ((base|size)&KPageMask)) |
|
404 |
Panic(EInvalidReservedBankAtBoot); |
|
405 |
||
406 |
SPageInfo* pi = SPageInfo::FromPhysAddr(base); |
|
407 |
SPageInfo* piEnd = pi+(size>>KPageShift); |
|
408 |
while(pi<piEnd) |
|
409 |
(pi++)->SetPhysAlloc(); |
|
410 |
++bank; |
|
411 |
} |
|
412 |
||
413 |
// Clear the inital (and only so far) page table info page so all unused |
|
414 |
// page tables infos will be marked as unused. |
|
415 |
__ASSERT_COMPILE(SPageTableInfo::EUnused == 0); |
|
416 |
memclr((TAny*)KPageTableInfoBase, KPageSize); |
|
417 |
||
418 |
// look for page tables - assume first page table maps page tables |
|
419 |
TPte* pPte = (TPte*)KPageTableBase; |
|
420 |
TInt i; |
|
421 |
for(i=0; i<KChunkSize/KPageSize; ++i) |
|
422 |
{ |
|
423 |
TPte pte = *pPte++; |
|
424 |
if(pte==KPteUnallocatedEntry) // after boot, page tables are contiguous |
|
425 |
break; |
|
426 |
TPhysAddr ptpgPhys = Mmu::PtePhysAddr(pte,i); |
|
427 |
__KTRACE_OPT(KBOOT,Kern::Printf("Page Table Group %08x -> Phys %08x", KPageTableBase+i*KPageSize, ptpgPhys)); |
|
428 |
SPageInfo* pi = SPageInfo::SafeFromPhysAddr(ptpgPhys); |
|
429 |
__ASSERT_ALWAYS(pi, Panic(EInvalidPageTableAtBoot)); |
|
430 |
pi->SetFixed(i); // this also sets the SPageInfo::iOffset so that linear-to-physical works |
|
431 |
} |
|
432 |
||
433 |
// look for mapped pages |
|
434 |
TPde* pd = Mmu::PageDirectory(KKernelOsAsid); |
|
435 |
for(i=0; i<(1<<(32-KChunkShift)); ++i) |
|
436 |
{ |
|
437 |
TPde pde = pd[i]; |
|
438 |
if(pde==KPdeUnallocatedEntry) |
|
439 |
continue; |
|
440 |
TPhysAddr pdePhys = Mmu::PdePhysAddr(pde); |
|
441 |
TPte* pt = 0; |
|
442 |
if(pdePhys!=KPhysAddrInvalid) |
|
443 |
{ |
|
444 |
__KTRACE_OPT(KBOOT,Kern::Printf("Addr %08x -> Whole PDE Phys %08x", i<<KChunkShift, pdePhys)); |
|
445 |
} |
|
446 |
else |
|
447 |
{ |
|
448 |
pt = Mmu::PageTableFromPde(pde); |
|
449 |
__KTRACE_OPT(KBOOT,Kern::Printf("Addr %08x -> page table %08x", i<<KChunkShift, pt)); |
|
450 |
__ASSERT_ALWAYS(pt,Panic(EInvalidPdeAtBoot)); // bad PDE |
|
451 |
} |
|
452 |
||
453 |
TInt j; |
|
454 |
TInt np = 0; |
|
455 |
for(j=0; j<KChunkSize/KPageSize; ++j) |
|
456 |
{ |
|
457 |
TBool present = ETrue; // all pages present if whole PDE mapping |
|
458 |
TPte pte = 0; |
|
459 |
if(pt) |
|
460 |
{ |
|
461 |
pte = pt[j]; |
|
462 |
present = pte!=KPteUnallocatedEntry; |
|
463 |
} |
|
464 |
if(present) |
|
465 |
{ |
|
466 |
++np; |
|
467 |
TPhysAddr pa = pt ? Mmu::PtePhysAddr(pte,j) : (pdePhys + (j<<KPageShift)); |
|
468 |
SPageInfo* pi = SPageInfo::SafeFromPhysAddr(pa); |
|
469 |
__KTRACE_OPT(KBOOT,Kern::Printf("Addr: %08x PA=%08x", |
|
470 |
(i<<KChunkShift)+(j<<KPageShift), pa)); |
|
471 |
if(pi) // ignore non-RAM mappings |
|
472 |
{ |
|
473 |
TInt r = iRamPageAllocator->MarkPageAllocated(pa, EPageFixed); |
|
474 |
// allow KErrAlreadyExists since it's possible that a page is doubly mapped |
|
475 |
__ASSERT_ALWAYS(r==KErrNone || r==KErrAlreadyExists, Panic(EBadMappedPageAfterBoot)); |
|
476 |
if(pi->Type()==SPageInfo::EUnused) |
|
477 |
pi->SetFixed(); |
|
102
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
478 |
#ifdef BTRACE_KERNEL_MEMORY |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
479 |
if(r == KErrNone) |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
480 |
++Epoc::KernelMiscPages; |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
481 |
#endif |
0 | 482 |
} |
483 |
} |
|
484 |
} |
|
485 |
__KTRACE_OPT(KBOOT,Kern::Printf("Addr: %08x #PTEs=%d",(i<<KChunkShift),np)); |
|
486 |
if(pt) |
|
487 |
{ |
|
488 |
SPageTableInfo* pti = SPageTableInfo::FromPtPtr(pt); |
|
489 |
pti->Boot(np); |
|
490 |
} |
|
491 |
} |
|
492 |
||
493 |
TInt r = K::MutexCreate(iRamAllocatorMutex, KLitRamAlloc, NULL, EFalse, KMutexOrdRamAlloc); |
|
494 |
if(r!=KErrNone) |
|
495 |
Panic(ERamAllocMutexCreateFailed); |
|
496 |
iRamAllocLockCount = 0; |
|
497 |
iRamAllocInitialFreePages = FreeRamInPages(); |
|
498 |
||
499 |
__KTRACE_OPT2(KBOOT,KMMU,Kern::Printf("Mmu::DoInit2")); |
|
500 |
||
501 |
for(i=0; i<KNumTempMappingSlots; ++i) |
|
502 |
iTempMap[i].Alloc(1); |
|
503 |
||
504 |
iPhysMemSyncTemp.Alloc(1); |
|
505 |
r = K::MutexCreate(iPhysMemSyncMutex, KLitPhysMemSync, NULL, EFalse, KMutexOrdSyncPhysMem); |
|
506 |
if(r!=KErrNone) |
|
507 |
Panic(EPhysMemSyncMutexCreateFailed); |
|
102
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
508 |
|
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
509 |
#ifdef FMM_VERIFY_RAM |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
510 |
VerifyRam(); |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
511 |
#endif |
0 | 512 |
} |
513 |
||
514 |
||
515 |
void Mmu::Init2FinalCommon() |
|
516 |
{ |
|
517 |
__KTRACE_OPT2(KBOOT,KMMU,Kern::Printf("Mmu::Init2FinalCommon")); |
|
102
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
518 |
// Reduce free memory to <2GB... |
0 | 519 |
while(FreeRamInPages()>=0x80000000/KPageSize) |
520 |
{ |
|
521 |
TPhysAddr dummyPage; |
|
522 |
TInt r = iRamPageAllocator->AllocRamPages(&dummyPage,1, EPageFixed); |
|
523 |
__NK_ASSERT_ALWAYS(r==KErrNone); |
|
524 |
} |
|
102
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
525 |
// Reduce total RAM to <2GB... |
0 | 526 |
if(TheSuperPage().iTotalRamSize<0) |
527 |
TheSuperPage().iTotalRamSize = 0x80000000-KPageSize; |
|
528 |
||
529 |
// Save current free RAM size - there can never be more free RAM than this |
|
530 |
TUint maxFreePages = FreeRamInPages(); |
|
531 |
K::MaxFreeRam = maxFreePages*KPageSize; |
|
532 |
if(maxFreePages < (TUint(PP::RamDriveMaxSize)>>KPageShift)) |
|
533 |
PP::RamDriveMaxSize = maxFreePages*KPageSize; |
|
534 |
||
535 |
// update this to stop assert triggering in RamAllocLock::Lock() |
|
536 |
iRamAllocInitialFreePages = maxFreePages; |
|
90
947f0dc9f7a8
Revision: 201015
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
39
diff
changeset
|
537 |
|
947f0dc9f7a8
Revision: 201015
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
39
diff
changeset
|
538 |
// Get the allocator to signal to the variant which RAM zones are in use so far |
947f0dc9f7a8
Revision: 201015
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
39
diff
changeset
|
539 |
iRamPageAllocator->InitialCallback(); |
0 | 540 |
} |
541 |
||
542 |
||
543 |
void Mmu::Init3() |
|
544 |
{ |
|
545 |
iDefrag = new Defrag; |
|
546 |
if (!iDefrag) |
|
547 |
Panic(EDefragAllocFailed); |
|
548 |
iDefrag->Init3(TheMmu.iRamPageAllocator); |
|
549 |
} |
|
550 |
||
102
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
551 |
|
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
552 |
void Mmu::BTracePrime(TUint aCategory) |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
553 |
{ |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
554 |
(void)aCategory; |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
555 |
|
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
556 |
#ifdef BTRACE_RAM_ALLOCATOR |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
557 |
// Must check for -1 as that is the default value of aCategory for |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
558 |
// BTrace::Prime() which is intended to prime all categories that are |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
559 |
// currently enabled via a single invocation of BTrace::Prime(). |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
560 |
if(aCategory==BTrace::ERamAllocator || (TInt)aCategory == -1) |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
561 |
{ |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
562 |
NKern::ThreadEnterCS(); |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
563 |
RamAllocLock::Lock(); |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
564 |
iRamPageAllocator->DoBTracePrime(); |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
565 |
RamAllocLock::Unlock(); |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
566 |
NKern::ThreadLeaveCS(); |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
567 |
} |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
568 |
#endif |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
569 |
} |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
570 |
|
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
571 |
|
0 | 572 |
// |
573 |
// Utils |
|
574 |
// |
|
575 |
||
576 |
void Mmu::Panic(TPanic aPanic) |
|
577 |
{ |
|
578 |
Kern::Fault("MMU",aPanic); |
|
579 |
} |
|
580 |
||
581 |
||
582 |
TUint Mmu::FreeRamInPages() |
|
583 |
{ |
|
584 |
return iRamPageAllocator->FreeRamInPages()+ThePager.NumberOfFreePages(); |
|
585 |
} |
|
586 |
||
587 |
||
588 |
TUint Mmu::TotalPhysicalRamPages() |
|
589 |
{ |
|
590 |
return iRamPageAllocator->TotalPhysicalRamPages(); |
|
591 |
} |
|
592 |
||
593 |
||
594 |
const SRamZone* Mmu::RamZoneConfig(TRamZoneCallback& aCallback) const |
|
595 |
{ |
|
596 |
aCallback = iRamZoneCallback; |
|
597 |
return iRamZones; |
|
598 |
} |
|
599 |
||
600 |
||
601 |
void Mmu::SetRamZoneConfig(const SRamZone* aZones, TRamZoneCallback aCallback) |
|
602 |
{ |
|
603 |
iRamZones = aZones; |
|
604 |
iRamZoneCallback = aCallback; |
|
605 |
} |
|
606 |
||
607 |
||
608 |
TInt Mmu::ModifyRamZoneFlags(TUint aId, TUint aClearMask, TUint aSetMask) |
|
609 |
{ |
|
610 |
return iRamPageAllocator->ModifyZoneFlags(aId, aClearMask, aSetMask); |
|
611 |
} |
|
612 |
||
613 |
||
614 |
TInt Mmu::GetRamZonePageCount(TUint aId, SRamZonePageCount& aPageData) |
|
615 |
{ |
|
616 |
return iRamPageAllocator->GetZonePageCount(aId, aPageData); |
|
617 |
} |
|
618 |
||
619 |
||
620 |
TInt Mmu::ZoneAllocPhysicalRam(TUint* aZoneIdList, TUint aZoneIdCount, TInt aBytes, TPhysAddr& aPhysAddr, TInt aAlign) |
|
621 |
{ |
|
622 |
__KTRACE_OPT(KMMU,Kern::Printf("Mmu::ZoneAllocPhysicalRam(?,%d,%d,?,%d)", aZoneIdCount, aBytes, aPhysAddr, aAlign)); |
|
623 |
__NK_ASSERT_DEBUG(RamAllocLock::IsHeld()); |
|
624 |
||
152
657f875b013e
Revision: 201023
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
102
diff
changeset
|
625 |
TInt r = iRamPageAllocator->ZoneAllocContiguousRam(aZoneIdList, aZoneIdCount, aBytes, aPhysAddr, aAlign); |
0 | 626 |
if(r!=KErrNone) |
627 |
iRamAllocFailed = ETrue; |
|
628 |
else |
|
629 |
{ |
|
630 |
TUint pages = MM::RoundToPageCount(aBytes); |
|
631 |
AllocatedPhysicalRam(aPhysAddr, pages, (Mmu::TRamAllocFlags)EMemAttStronglyOrdered); |
|
632 |
} |
|
633 |
__KTRACE_OPT(KMMU,Kern::Printf("Mmu::ZoneAllocPhysicalRam returns %d and aPhysAddr=0x%08x",r,aPhysAddr)); |
|
634 |
return r; |
|
635 |
} |
|
636 |
||
637 |
||
638 |
TInt Mmu::ZoneAllocPhysicalRam(TUint* aZoneIdList, TUint aZoneIdCount, TInt aNumPages, TPhysAddr* aPageList) |
|
639 |
{ |
|
640 |
__KTRACE_OPT(KMMU,Kern::Printf("Mmu::ZoneAllocPhysicalRam(?,%d,%d,?)", aZoneIdCount, aNumPages)); |
|
641 |
__NK_ASSERT_DEBUG(RamAllocLock::IsHeld()); |
|
642 |
||
643 |
TInt r = iRamPageAllocator->ZoneAllocRamPages(aZoneIdList, aZoneIdCount, aPageList, aNumPages, EPageFixed); |
|
644 |
if(r!=KErrNone) |
|
645 |
iRamAllocFailed = ETrue; |
|
646 |
else |
|
647 |
{ |
|
648 |
PagesAllocated(aPageList, aNumPages, (Mmu::TRamAllocFlags)EMemAttStronglyOrdered); |
|
649 |
||
650 |
// update page infos... |
|
102
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
651 |
SetAllocPhysRam(aPageList, aNumPages); |
0 | 652 |
} |
653 |
__KTRACE_OPT(KMMU,Kern::Printf("Mmu::ZoneAllocPhysicalRam returns %d",r)); |
|
654 |
return r; |
|
655 |
} |
|
656 |
||
657 |
||
658 |
TInt Mmu::RamHalFunction(TInt aFunction, TAny* a1, TAny* a2) |
|
659 |
{ |
|
660 |
// This function should only be registered with hal and therefore can only |
|
661 |
// be invoked after the ram allocator has been created. |
|
662 |
__NK_ASSERT_DEBUG(iRamPageAllocator); |
|
663 |
return iRamPageAllocator->HalFunction(aFunction, a1, a2); |
|
664 |
} |
|
665 |
||
666 |
||
667 |
void Mmu::ChangePageType(SPageInfo* aPageInfo, TZonePageType aOldPageType, TZonePageType aNewPageType) |
|
668 |
{ |
|
669 |
iRamPageAllocator->ChangePageType(aPageInfo, aOldPageType, aNewPageType); |
|
670 |
} |
|
671 |
||
672 |
TInt Mmu::HandlePageFault(TLinAddr aPc, TLinAddr aFaultAddress, TUint aAccessPermissions, TAny* aExceptionInfo) |
|
673 |
{ |
|
674 |
TRACE(("Mmu::HandlePageFault(0x%08x,0x%08x,%d)",aPc,aFaultAddress,aAccessPermissions)); |
|
675 |
||
676 |
DMemModelThread* thread = (DMemModelThread*)TheCurrentThread; |
|
677 |
// Get the os asid of the process taking the fault, no need to open a reference |
|
678 |
// as it is the current thread's process so can't be freed. |
|
679 |
TUint faultOsAsid = ((DMemModelProcess*)thread->iNThread.iAddressSpace)->OsAsid(); |
|
680 |
||
681 |
// check if any fast mutexes held... |
|
682 |
NFastMutex* fm = NKern::HeldFastMutex(); |
|
683 |
TPagingExcTrap* trap = thread->iPagingExcTrap; |
|
684 |
if(fm) |
|
685 |
{ |
|
686 |
// check there is an XTRAP_PAGING in effect... |
|
687 |
if(!trap) |
|
688 |
{ |
|
689 |
// oops, kill system... |
|
690 |
__KTRACE_OPT2(KPAGING,KPANIC,Kern::Printf("Fault with FM Held! addr=0x%08x (%O pc=%x)",aFaultAddress,thread,aPc)); |
|
691 |
Exc::Fault(aExceptionInfo); |
|
692 |
} |
|
693 |
||
694 |
// release the fast mutex... |
|
695 |
NKern::FMSignal(fm); |
|
696 |
} |
|
697 |
||
698 |
NKern::ThreadEnterCS(); |
|
699 |
||
700 |
// work out address space for aFaultAddress... |
|
701 |
TUint osAsid = faultOsAsid; |
|
702 |
TLinAddr addr = aFaultAddress; |
|
703 |
if(thread->iAliasLinAddr && TUint(addr - thread->iAliasLinAddr) < TUint(KPageSize)) |
|
704 |
{ |
|
705 |
// Address in aliased memory... |
|
706 |
addr = (addr - thread->iAliasLinAddr) + thread->iAliasTarget; |
|
707 |
// Get the os asid of the process thread is aliasing, no need to open |
|
708 |
// a reference on it as one was already opened when the alias was created. |
|
709 |
osAsid = thread->iAliasProcess->OsAsid(); |
|
710 |
} |
|
711 |
else if(addr>=KGlobalMemoryBase) |
|
712 |
{ |
|
713 |
// Address in global region, so look it up in kernel's address space... |
|
714 |
osAsid = KKernelOsAsid; |
|
715 |
} |
|
716 |
||
717 |
// NOTE, osAsid will remain valid for duration of this function because it is either |
|
718 |
// - The current thread's address space, which can't go away whilst the thread |
|
719 |
// is running. |
|
720 |
// - The address space of another thread which we are aliasing memory from, |
|
721 |
// and we would only do this if we have a reference on this other thread, |
|
722 |
// which has a reference on it's process, which should own the address space! |
|
723 |
||
724 |
#ifdef __BROADCAST_CACHE_MAINTENANCE__ |
|
36
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
31
diff
changeset
|
725 |
TInt aliasAsid = -1; |
0 | 726 |
if (thread->iAliasLinAddr) |
727 |
{ |
|
728 |
// If an alias is in effect, the the thread will be locked to the current CPU, |
|
729 |
// but we need to be able to migrate between CPUs for cache maintainance. This |
|
730 |
// must be dealt with by removing the alias and restoring it with a paging trap |
|
731 |
// handler. |
|
732 |
if(!trap) |
|
733 |
{ |
|
734 |
// oops, kill system... |
|
735 |
__KTRACE_OPT2(KPAGING,KPANIC,Kern::Printf("Fault with thread locked to current CPU! addr=0x%08x (%O pc=%x)",aFaultAddress,thread,aPc)); |
|
736 |
Exc::Fault(aExceptionInfo); |
|
737 |
} |
|
36
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
31
diff
changeset
|
738 |
// Open a reference on the aliased process's os asid before removing the alias |
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
31
diff
changeset
|
739 |
// so that the address space can't be freed while we try to access its members. |
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
31
diff
changeset
|
740 |
aliasAsid = thread->iAliasProcess->TryOpenOsAsid(); |
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
31
diff
changeset
|
741 |
// This should never fail as until we remove the alias there will |
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
31
diff
changeset
|
742 |
// always be at least one reference on the os asid. |
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
31
diff
changeset
|
743 |
__NK_ASSERT_DEBUG(aliasAsid >= 0); |
0 | 744 |
thread->RemoveAlias(); |
745 |
} |
|
746 |
#endif |
|
747 |
||
748 |
// find mapping... |
|
749 |
TUint offsetInMapping; |
|
750 |
TUint mapInstanceCount; |
|
751 |
DMemoryMapping* mapping = MM::FindMappingInAddressSpace(osAsid, addr, 1, offsetInMapping, mapInstanceCount); |
|
752 |
// TRACE(("%O mapping=0x%08x",TheCurrentThread,mapping)); |
|
753 |
TInt r = KErrNotFound; |
|
754 |
||
755 |
if(mapping) |
|
756 |
{ |
|
757 |
MmuLock::Lock(); |
|
758 |
||
759 |
// check if we need to process page fault... |
|
760 |
if(!Mmu::CheckPteTypePermissions(mapping->PteType(),aAccessPermissions) || |
|
761 |
mapInstanceCount != mapping->MapInstanceCount()) |
|
762 |
{ |
|
763 |
// Invalid access to the page. |
|
764 |
MmuLock::Unlock(); |
|
765 |
r = KErrAbort; |
|
766 |
} |
|
767 |
else |
|
768 |
{ |
|
39
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
769 |
// Should not be able to take a fault on a pinned mapping if accessing it |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
770 |
// with the correct permissions. |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
771 |
__NK_ASSERT_DEBUG(!mapping->IsPinned()); |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
772 |
|
0 | 773 |
// we do need to handle fault so is this a demand paging or page moving fault |
774 |
DMemoryObject* memory = mapping->Memory(); |
|
775 |
if(!memory) |
|
776 |
MmuLock::Unlock(); |
|
777 |
else |
|
778 |
{ |
|
779 |
TUint faultIndex = (offsetInMapping >> KPageShift) + mapping->iStartIndex; |
|
780 |
memory->Open(); |
|
781 |
||
782 |
// This is safe as we have the instance count so can detect the mapping |
|
783 |
// being reused and we have a reference to the memory object so it can't |
|
784 |
// be deleted. |
|
785 |
MmuLock::Unlock(); |
|
786 |
||
787 |
if(memory->IsDemandPaged()) |
|
788 |
{ |
|
789 |
// Let the pager handle the fault... |
|
790 |
r = ThePager.HandlePageFault( aPc, aFaultAddress, faultOsAsid, faultIndex, |
|
791 |
aAccessPermissions, memory, mapping, mapInstanceCount, |
|
792 |
thread, aExceptionInfo); |
|
793 |
} |
|
794 |
else |
|
795 |
{// The page could be being moved so verify that with its manager. |
|
796 |
DMemoryManager* manager = memory->iManager; |
|
797 |
r = manager->HandleFault(memory, faultIndex, mapping, mapInstanceCount, aAccessPermissions); |
|
798 |
} |
|
799 |
if (r == KErrNone) |
|
800 |
{// alias PDE needs updating because page tables have changed... |
|
801 |
thread->RefreshAlias(); |
|
802 |
} |
|
803 |
memory->Close(); |
|
804 |
} |
|
805 |
} |
|
806 |
mapping->Close(); |
|
807 |
} |
|
808 |
||
809 |
if (trap) |
|
810 |
{ |
|
811 |
// restore address space (because the trap will bypass any code |
|
812 |
// which would have done this.)... |
|
813 |
DMemModelThread::RestoreAddressSpace(); |
|
814 |
} |
|
815 |
||
36
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
31
diff
changeset
|
816 |
#ifdef __BROADCAST_CACHE_MAINTENANCE__ |
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
31
diff
changeset
|
817 |
// Close any reference on the aliased process's os asid before we leave the |
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
31
diff
changeset
|
818 |
// critical section. |
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
31
diff
changeset
|
819 |
if (aliasAsid >= 0) |
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
31
diff
changeset
|
820 |
{ |
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
31
diff
changeset
|
821 |
thread->iAliasProcess->CloseOsAsid(); |
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
31
diff
changeset
|
822 |
} |
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
31
diff
changeset
|
823 |
#endif |
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
31
diff
changeset
|
824 |
|
0 | 825 |
NKern::ThreadLeaveCS(); // thread will die now if CheckRealtimeThreadFault caused a panic |
826 |
||
827 |
// deal with XTRAP_PAGING... |
|
828 |
if(trap) |
|
829 |
{ |
|
830 |
// re-acquire any fast mutex which was held before the page fault... |
|
831 |
if(fm) |
|
832 |
NKern::FMWait(fm); |
|
833 |
if (r == KErrNone) |
|
834 |
{ |
|
835 |
trap->Exception(1); // return from exception trap with result '1' (value>0) |
|
836 |
// code doesn't continue beyond this point. |
|
837 |
__NK_ASSERT_DEBUG(0); |
|
838 |
} |
|
839 |
} |
|
840 |
||
841 |
return r; |
|
842 |
} |
|
843 |
||
844 |
||
845 |
// |
|
846 |
// Memory allocation |
|
847 |
// |
|
848 |
||
849 |
TInt Mmu::AllocRam( TPhysAddr* aPages, TUint aCount, TRamAllocFlags aFlags, TZonePageType aZonePageType, |
|
850 |
TUint aBlockZoneId, TBool aBlockRest) |
|
851 |
{ |
|
852 |
__KTRACE_OPT(KMMU,Kern::Printf("Mmu::AllocRam(?,%d,%x)",aCount,aFlags)); |
|
853 |
__NK_ASSERT_DEBUG(RamAllocLock::IsHeld()); |
|
854 |
#ifdef _DEBUG |
|
855 |
if(K::CheckForSimulatedAllocFail()) |
|
856 |
{ |
|
857 |
__KTRACE_OPT(KMMU,Kern::Printf("Mmu::AllocRam returns simulated OOM %d",KErrNoMemory)); |
|
858 |
return KErrNoMemory; |
|
859 |
} |
|
860 |
#endif |
|
861 |
TInt missing = iRamPageAllocator->AllocRamPages(aPages, aCount, aZonePageType, aBlockZoneId, aBlockRest); |
|
201
43365a9b78a3
Revision: 201027
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
152
diff
changeset
|
862 |
if(missing && !(aFlags&EAllocNoPagerReclaim)) |
43365a9b78a3
Revision: 201027
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
152
diff
changeset
|
863 |
{ |
43365a9b78a3
Revision: 201027
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
152
diff
changeset
|
864 |
// taking the page cleaning lock here prevents the pager releasing the ram alloc lock |
43365a9b78a3
Revision: 201027
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
152
diff
changeset
|
865 |
PageCleaningLock::Lock(); |
43365a9b78a3
Revision: 201027
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
152
diff
changeset
|
866 |
if (ThePager.GetFreePages(missing)) |
43365a9b78a3
Revision: 201027
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
152
diff
changeset
|
867 |
missing = iRamPageAllocator->AllocRamPages(aPages, aCount, aZonePageType, aBlockZoneId, aBlockRest); |
43365a9b78a3
Revision: 201027
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
152
diff
changeset
|
868 |
PageCleaningLock::Unlock(); |
43365a9b78a3
Revision: 201027
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
152
diff
changeset
|
869 |
} |
0 | 870 |
TInt r = missing ? KErrNoMemory : KErrNone; |
871 |
if(r!=KErrNone) |
|
872 |
iRamAllocFailed = ETrue; |
|
873 |
else |
|
874 |
PagesAllocated(aPages,aCount,aFlags); |
|
875 |
__KTRACE_OPT(KMMU,Kern::Printf("Mmu::AllocRam returns %d",r)); |
|
876 |
return r; |
|
877 |
} |
|
878 |
||
879 |
||
152
657f875b013e
Revision: 201023
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
102
diff
changeset
|
880 |
/** |
657f875b013e
Revision: 201023
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
102
diff
changeset
|
881 |
Mark a page as being allocated to a particular page type. |
657f875b013e
Revision: 201023
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
102
diff
changeset
|
882 |
|
657f875b013e
Revision: 201023
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
102
diff
changeset
|
883 |
NOTE - This page should not be used until PagesAllocated() has been invoked on it. |
657f875b013e
Revision: 201023
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
102
diff
changeset
|
884 |
|
657f875b013e
Revision: 201023
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
102
diff
changeset
|
885 |
@param aPhysAddr The physical address of the page to mark as allocated. |
657f875b013e
Revision: 201023
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
102
diff
changeset
|
886 |
@param aZonePageType The type of the page to mark as allocated. |
657f875b013e
Revision: 201023
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
102
diff
changeset
|
887 |
*/ |
657f875b013e
Revision: 201023
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
102
diff
changeset
|
888 |
void Mmu::MarkPageAllocated(TPhysAddr aPhysAddr, TZonePageType aZonePageType) |
657f875b013e
Revision: 201023
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
102
diff
changeset
|
889 |
{ |
657f875b013e
Revision: 201023
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
102
diff
changeset
|
890 |
__KTRACE_OPT(KMMU,Kern::Printf("Mmu::MarkPageAllocated(0x%x, %d)", aPhysAddr, aZonePageType)); |
657f875b013e
Revision: 201023
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
102
diff
changeset
|
891 |
__NK_ASSERT_DEBUG(RamAllocLock::IsHeld()); |
657f875b013e
Revision: 201023
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
102
diff
changeset
|
892 |
iRamPageAllocator->MarkPageAllocated(aPhysAddr, aZonePageType); |
657f875b013e
Revision: 201023
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
102
diff
changeset
|
893 |
} |
657f875b013e
Revision: 201023
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
102
diff
changeset
|
894 |
|
657f875b013e
Revision: 201023
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
102
diff
changeset
|
895 |
|
0 | 896 |
void Mmu::FreeRam(TPhysAddr* aPages, TUint aCount, TZonePageType aZonePageType) |
897 |
{ |
|
898 |
__KTRACE_OPT(KMMU,Kern::Printf("Mmu::FreeRam(?,%d)",aCount)); |
|
899 |
__NK_ASSERT_DEBUG(RamAllocLock::IsHeld()); |
|
900 |
||
901 |
// update page infos... |
|
902 |
TPhysAddr* pages = aPages; |
|
903 |
TPhysAddr* pagesEnd = pages+aCount; |
|
904 |
TPhysAddr* pagesOut = aPages; |
|
905 |
MmuLock::Lock(); |
|
906 |
TUint flash = 0; |
|
907 |
while(pages<pagesEnd) |
|
908 |
{ |
|
909 |
MmuLock::Flash(flash,KMaxPageInfoUpdatesInOneGo/2); |
|
910 |
TPhysAddr pagePhys = *pages++; |
|
911 |
__NK_ASSERT_DEBUG(pagePhys!=KPhysAddrInvalid); |
|
912 |
SPageInfo* pi = SPageInfo::FromPhysAddr(pagePhys); |
|
913 |
PageFreed(pi); |
|
914 |
||
152
657f875b013e
Revision: 201023
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
102
diff
changeset
|
915 |
switch (ThePager.PageFreed(pi)) |
0 | 916 |
{ |
152
657f875b013e
Revision: 201023
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
102
diff
changeset
|
917 |
case KErrNone: |
657f875b013e
Revision: 201023
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
102
diff
changeset
|
918 |
--aCount; // pager has dealt with this page, so one less for us |
657f875b013e
Revision: 201023
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
102
diff
changeset
|
919 |
break; |
657f875b013e
Revision: 201023
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
102
diff
changeset
|
920 |
case KErrCompletion: |
657f875b013e
Revision: 201023
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
102
diff
changeset
|
921 |
// This was a pager controlled page but it is no longer required. |
657f875b013e
Revision: 201023
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
102
diff
changeset
|
922 |
__NK_ASSERT_DEBUG(aZonePageType == EPageMovable || aZonePageType == EPageDiscard); |
657f875b013e
Revision: 201023
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
102
diff
changeset
|
923 |
__NK_ASSERT_DEBUG(pi->PagedState() == SPageInfo::EUnpaged); |
657f875b013e
Revision: 201023
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
102
diff
changeset
|
924 |
if (aZonePageType == EPageMovable) |
657f875b013e
Revision: 201023
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
102
diff
changeset
|
925 |
{// This page was donated to the pager so have to free it here |
657f875b013e
Revision: 201023
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
102
diff
changeset
|
926 |
// as aZonePageType is incorrect for this page but aPages may |
657f875b013e
Revision: 201023
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
102
diff
changeset
|
927 |
// contain a mixture of movable and discardable pages. |
657f875b013e
Revision: 201023
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
102
diff
changeset
|
928 |
MmuLock::Unlock(); |
657f875b013e
Revision: 201023
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
102
diff
changeset
|
929 |
iRamPageAllocator->FreeRamPages(&pagePhys, 1, EPageDiscard); |
657f875b013e
Revision: 201023
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
102
diff
changeset
|
930 |
aCount--; // We've freed this page here so one less to free later |
657f875b013e
Revision: 201023
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
102
diff
changeset
|
931 |
flash = 0; // reset flash count as we released the mmulock. |
657f875b013e
Revision: 201023
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
102
diff
changeset
|
932 |
MmuLock::Lock(); |
657f875b013e
Revision: 201023
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
102
diff
changeset
|
933 |
break; |
657f875b013e
Revision: 201023
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
102
diff
changeset
|
934 |
} |
657f875b013e
Revision: 201023
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
102
diff
changeset
|
935 |
// fall through.. |
657f875b013e
Revision: 201023
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
102
diff
changeset
|
936 |
default: |
657f875b013e
Revision: 201023
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
102
diff
changeset
|
937 |
// Free this page.. |
657f875b013e
Revision: 201023
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
102
diff
changeset
|
938 |
__NK_ASSERT_DEBUG(pi->PagedState() == SPageInfo::EUnpaged); |
657f875b013e
Revision: 201023
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
102
diff
changeset
|
939 |
*pagesOut++ = pagePhys; // store page address for freeing later |
0 | 940 |
} |
941 |
} |
|
942 |
MmuLock::Unlock(); |
|
943 |
||
944 |
iRamPageAllocator->FreeRamPages(aPages, aCount, aZonePageType); |
|
945 |
} |
|
946 |
||
947 |
||
948 |
TInt Mmu::AllocContiguousRam(TPhysAddr& aPhysAddr, TUint aCount, TUint aAlign, TRamAllocFlags aFlags) |
|
949 |
{ |
|
950 |
__KTRACE_OPT(KMMU,Kern::Printf("Mmu::AllocContiguousRam(?,0x%x,%d,%x)",aCount,aAlign,aFlags)); |
|
951 |
__NK_ASSERT_DEBUG(RamAllocLock::IsHeld()); |
|
952 |
#ifdef _DEBUG |
|
953 |
if(K::CheckForSimulatedAllocFail()) |
|
954 |
{ |
|
955 |
__KTRACE_OPT(KMMU,Kern::Printf("Mmu::AllocContiguousRam returns simulated OOM %d",KErrNoMemory)); |
|
956 |
return KErrNoMemory; |
|
957 |
} |
|
152
657f875b013e
Revision: 201023
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
102
diff
changeset
|
958 |
// Only the pager sets EAllocNoPagerReclaim and it shouldn't allocate contiguous ram. |
0 | 959 |
__NK_ASSERT_DEBUG(!(aFlags&EAllocNoPagerReclaim)); |
960 |
#endif |
|
152
657f875b013e
Revision: 201023
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
102
diff
changeset
|
961 |
TInt r = iRamPageAllocator->AllocContiguousRam(aCount, aPhysAddr, aAlign+KPageShift); |
0 | 962 |
if(r!=KErrNone) |
963 |
iRamAllocFailed = ETrue; |
|
964 |
else |
|
965 |
PagesAllocated((TPhysAddr*)(aPhysAddr|1), aCount, aFlags); |
|
152
657f875b013e
Revision: 201023
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
102
diff
changeset
|
966 |
__KTRACE_OPT(KMMU,Kern::Printf("AllocContiguousRam returns %d and aPhysAddr=0x%08x",r,aPhysAddr)); |
0 | 967 |
return r; |
968 |
} |
|
969 |
||
970 |
||
971 |
void Mmu::FreeContiguousRam(TPhysAddr aPhysAddr, TUint aCount) |
|
972 |
{ |
|
973 |
__KTRACE_OPT(KMMU,Kern::Printf("Mmu::FreeContiguousRam(0x%08x,0x%x)",aPhysAddr,aCount)); |
|
974 |
__NK_ASSERT_DEBUG(RamAllocLock::IsHeld()); |
|
975 |
__NK_ASSERT_DEBUG((aPhysAddr&KPageMask)==0); |
|
976 |
||
977 |
TUint pageCount = aCount; |
|
978 |
||
979 |
// update page infos... |
|
980 |
SPageInfo* pi = SPageInfo::FromPhysAddr(aPhysAddr); |
|
981 |
SPageInfo* piEnd = pi+pageCount; |
|
982 |
TUint flash = 0; |
|
983 |
MmuLock::Lock(); |
|
984 |
while(pi<piEnd) |
|
985 |
{ |
|
986 |
MmuLock::Flash(flash,KMaxPageInfoUpdatesInOneGo); |
|
987 |
PageFreed(pi++); |
|
988 |
} |
|
989 |
MmuLock::Unlock(); |
|
990 |
||
991 |
// free pages... |
|
992 |
while(pageCount) |
|
993 |
{ |
|
994 |
iRamPageAllocator->FreeRamPage(aPhysAddr, EPageFixed); |
|
995 |
aPhysAddr += KPageSize; |
|
996 |
--pageCount; |
|
997 |
} |
|
998 |
} |
|
999 |
||
1000 |
||
1001 |
TInt Mmu::AllocPhysicalRam(TPhysAddr* aPages, TUint aCount, TRamAllocFlags aFlags) |
|
1002 |
{ |
|
1003 |
__KTRACE_OPT(KMMU,Kern::Printf("Mmu::AllocPhysicalRam(?,%d,%x)",aCount,aFlags)); |
|
1004 |
__NK_ASSERT_DEBUG(RamAllocLock::IsHeld()); |
|
1005 |
// Allocate fixed pages as physically allocated pages aren't movable or discardable. |
|
1006 |
TInt r = AllocRam(aPages, aCount, aFlags, EPageFixed); |
|
1007 |
if (r!=KErrNone) |
|
1008 |
return r; |
|
1009 |
||
1010 |
// update page infos... |
|
102
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1011 |
SetAllocPhysRam(aPages, aCount); |
0 | 1012 |
|
1013 |
return KErrNone; |
|
1014 |
} |
|
1015 |
||
1016 |
||
1017 |
void Mmu::FreePhysicalRam(TPhysAddr* aPages, TUint aCount) |
|
1018 |
{ |
|
1019 |
__KTRACE_OPT(KMMU,Kern::Printf("Mmu::FreePhysicalRam(?,%d)",aCount)); |
|
1020 |
__NK_ASSERT_DEBUG(RamAllocLock::IsHeld()); |
|
1021 |
||
1022 |
// update page infos... |
|
1023 |
TPhysAddr* pages = aPages; |
|
1024 |
TPhysAddr* pagesEnd = pages+aCount; |
|
1025 |
MmuLock::Lock(); |
|
1026 |
TUint flash = 0; |
|
1027 |
while(pages<pagesEnd) |
|
1028 |
{ |
|
1029 |
MmuLock::Flash(flash,KMaxPageInfoUpdatesInOneGo/2); |
|
1030 |
TPhysAddr pagePhys = *pages++; |
|
1031 |
__NK_ASSERT_DEBUG(pagePhys!=KPhysAddrInvalid); |
|
1032 |
SPageInfo* pi = SPageInfo::FromPhysAddr(pagePhys); |
|
1033 |
__ASSERT_ALWAYS(pi->Type()==SPageInfo::EPhysAlloc, Panic(EBadFreePhysicalRam)); |
|
1034 |
__ASSERT_ALWAYS(!pi->UseCount(), Panic(EBadFreePhysicalRam)); |
|
1035 |
pi->SetUnused(); |
|
1036 |
} |
|
1037 |
MmuLock::Unlock(); |
|
1038 |
||
1039 |
iRamPageAllocator->FreeRamPages(aPages,aCount, EPageFixed); |
|
102
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1040 |
|
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1041 |
#ifdef BTRACE_KERNEL_MEMORY |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1042 |
if (BTrace::CheckFilter(BTrace::EKernelMemory)) |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1043 |
{// Only loop round each page if EKernelMemory tracing is enabled |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1044 |
pages = aPages; |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1045 |
pagesEnd = aPages + aCount; |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1046 |
while (pages < pagesEnd) |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1047 |
{ |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1048 |
BTrace8(BTrace::EKernelMemory, BTrace::EKernelMemoryDrvPhysFree, KPageSize, *pages++); |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1049 |
Epoc::DriverAllocdPhysRam -= KPageSize; |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1050 |
} |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1051 |
} |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1052 |
#endif |
0 | 1053 |
} |
1054 |
||
1055 |
||
1056 |
TInt Mmu::AllocPhysicalRam(TPhysAddr& aPhysAddr, TUint aCount, TUint aAlign, TRamAllocFlags aFlags) |
|
1057 |
{ |
|
1058 |
__KTRACE_OPT(KMMU,Kern::Printf("Mmu::AllocPhysicalRam(?,0x%x,d,%x)",aCount,aAlign,aFlags)); |
|
1059 |
TInt r = AllocContiguousRam(aPhysAddr,aCount,aAlign,aFlags); |
|
1060 |
if (r!=KErrNone) |
|
1061 |
return r; |
|
1062 |
||
1063 |
// update page infos... |
|
102
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1064 |
SetAllocPhysRam(aPhysAddr, aCount); |
0 | 1065 |
|
1066 |
return KErrNone; |
|
1067 |
} |
|
1068 |
||
1069 |
||
1070 |
void Mmu::FreePhysicalRam(TPhysAddr aPhysAddr, TUint aCount) |
|
1071 |
{ |
|
1072 |
__KTRACE_OPT(KMMU,Kern::Printf("Mmu::FreePhysicalRam(0x%08x,0x%x)",aPhysAddr,aCount)); |
|
1073 |
||
1074 |
// update page infos... |
|
1075 |
SPageInfo* pi = SPageInfo::FromPhysAddr(aPhysAddr); |
|
1076 |
SPageInfo* piEnd = pi+aCount; |
|
1077 |
TUint flash = 0; |
|
1078 |
MmuLock::Lock(); |
|
1079 |
while(pi<piEnd) |
|
1080 |
{ |
|
1081 |
MmuLock::Flash(flash,KMaxPageInfoUpdatesInOneGo); |
|
1082 |
__ASSERT_ALWAYS(pi->Type()==SPageInfo::EPhysAlloc, Panic(EBadFreePhysicalRam)); |
|
1083 |
__ASSERT_ALWAYS(!pi->UseCount(), Panic(EBadFreePhysicalRam)); |
|
1084 |
pi->SetUnused(); |
|
1085 |
++pi; |
|
1086 |
} |
|
1087 |
MmuLock::Unlock(); |
|
1088 |
||
102
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1089 |
TUint bytes = aCount << KPageShift; |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1090 |
iRamPageAllocator->FreePhysicalRam(aPhysAddr, bytes); |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1091 |
|
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1092 |
#ifdef BTRACE_KERNEL_MEMORY |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1093 |
BTrace8(BTrace::EKernelMemory, BTrace::EKernelMemoryDrvPhysFree, bytes, aPhysAddr); |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1094 |
Epoc::DriverAllocdPhysRam -= bytes; |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1095 |
#endif |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1096 |
} |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1097 |
|
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1098 |
|
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1099 |
TInt Mmu::FreeRamZone(TUint aZoneId) |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1100 |
{ |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1101 |
TPhysAddr zoneBase; |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1102 |
TUint zonePages; |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1103 |
TInt r = iRamPageAllocator->GetZoneAddress(aZoneId, zoneBase, zonePages); |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1104 |
if (r != KErrNone) |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1105 |
return r; |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1106 |
FreePhysicalRam(zoneBase, zonePages); |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1107 |
return KErrNone; |
0 | 1108 |
} |
1109 |
||
1110 |
||
1111 |
TInt Mmu::ClaimPhysicalRam(TPhysAddr aPhysAddr, TUint aCount, TRamAllocFlags aFlags) |
|
1112 |
{ |
|
1113 |
__KTRACE_OPT(KMMU,Kern::Printf("Mmu::ClaimPhysicalRam(0x%08x,0x%x,0x%08x)",aPhysAddr,aCount,aFlags)); |
|
1114 |
aPhysAddr &= ~KPageMask; |
|
102
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1115 |
TInt r = iRamPageAllocator->ClaimPhysicalRam(aPhysAddr, aCount << KPageShift); |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1116 |
if(r != KErrNone) |
0 | 1117 |
return r; |
1118 |
||
102
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1119 |
AllocatedPhysicalRam(aPhysAddr, aCount, aFlags); |
0 | 1120 |
return KErrNone; |
1121 |
} |
|
1122 |
||
1123 |
||
1124 |
void Mmu::AllocatedPhysicalRam(TPhysAddr aPhysAddr, TUint aCount, TRamAllocFlags aFlags) |
|
1125 |
{ |
|
1126 |
__KTRACE_OPT(KMMU,Kern::Printf("Mmu::AllocatedPhysicalRam(0x%08x,0x%x,d,%x)",aPhysAddr,aCount,aFlags)); |
|
1127 |
||
1128 |
PagesAllocated((TPhysAddr*)(aPhysAddr|1), aCount, aFlags); |
|
1129 |
||
1130 |
// update page infos... |
|
102
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1131 |
SetAllocPhysRam(aPhysAddr, aCount); |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1132 |
} |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1133 |
|
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1134 |
|
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1135 |
void Mmu::SetAllocPhysRam(TPhysAddr aPhysAddr, TUint aCount) |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1136 |
{ |
0 | 1137 |
SPageInfo* pi = SPageInfo::FromPhysAddr(aPhysAddr); |
1138 |
SPageInfo* piEnd = pi+aCount; |
|
1139 |
TUint flash = 0; |
|
1140 |
MmuLock::Lock(); |
|
1141 |
while(pi<piEnd) |
|
1142 |
{ |
|
102
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1143 |
MmuLock::Flash(flash, KMaxPageInfoUpdatesInOneGo); |
0 | 1144 |
pi->SetPhysAlloc(); |
1145 |
++pi; |
|
1146 |
} |
|
1147 |
MmuLock::Unlock(); |
|
102
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1148 |
|
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1149 |
#ifdef BTRACE_KERNEL_MEMORY |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1150 |
TUint bytes = aCount << KPageShift; |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1151 |
BTrace8(BTrace::EKernelMemory, BTrace::EKernelMemoryDrvPhysAlloc, bytes, aPhysAddr); |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1152 |
Epoc::DriverAllocdPhysRam += bytes; |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1153 |
#endif |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1154 |
} |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1155 |
|
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1156 |
|
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1157 |
void Mmu::SetAllocPhysRam(TPhysAddr* aPageList, TUint aNumPages) |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1158 |
{ |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1159 |
TPhysAddr* page = aPageList; |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1160 |
TPhysAddr* pageEnd = aPageList + aNumPages; |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1161 |
TUint flash = 0; |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1162 |
MmuLock::Lock(); |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1163 |
while (page < pageEnd) |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1164 |
{ |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1165 |
MmuLock::Flash(flash, KMaxPageInfoUpdatesInOneGo / 2); |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1166 |
TPhysAddr pagePhys = *page++; |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1167 |
__NK_ASSERT_DEBUG(pagePhys != KPhysAddrInvalid); |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1168 |
SPageInfo::FromPhysAddr(pagePhys)->SetPhysAlloc(); |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1169 |
} |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1170 |
MmuLock::Unlock(); |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1171 |
|
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1172 |
#ifdef BTRACE_KERNEL_MEMORY |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1173 |
if (BTrace::CheckFilter(BTrace::EKernelMemory)) |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1174 |
{// Only loop round each page if EKernelMemory tracing is enabled |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1175 |
TPhysAddr* pAddr = aPageList; |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1176 |
TPhysAddr* pAddrEnd = aPageList + aNumPages; |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1177 |
while (pAddr < pAddrEnd) |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1178 |
{ |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1179 |
BTrace8(BTrace::EKernelMemory, BTrace::EKernelMemoryDrvPhysAlloc, KPageSize, *pAddr++); |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1180 |
Epoc::DriverAllocdPhysRam += KPageSize; |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1181 |
} |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1182 |
} |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1183 |
#endif |
0 | 1184 |
} |
1185 |
||
1186 |
||
1187 |
// |
|
1188 |
// Misc |
|
1189 |
// |
|
1190 |
||
1191 |
#ifdef _DEBUG |
|
1192 |
/** |
|
1193 |
Perform a page table walk to return the physical address of |
|
1194 |
the memory mapped at virtual address \a aLinAddr in the |
|
1195 |
address space \a aOsAsid. |
|
1196 |
||
1197 |
If the page table used was not one allocated by the kernel |
|
1198 |
then the results are unpredictable and may cause a system fault. |
|
1199 |
||
1200 |
@pre #MmuLock held. |
|
1201 |
*/ |
|
1202 |
TPhysAddr Mmu::LinearToPhysical(TLinAddr aLinAddr, TInt aOsAsid) |
|
1203 |
{ |
|
1204 |
__NK_ASSERT_DEBUG(MmuLock::IsHeld() || K::Initialising); |
|
1205 |
return UncheckedLinearToPhysical(aLinAddr,aOsAsid); |
|
1206 |
} |
|
1207 |
#endif |
|
1208 |
||
1209 |
||
1210 |
/** |
|
1211 |
Next virtual address available for allocation by TTempMapping. |
|
1212 |
This is initialised to #KTempAddr and addresses may be allocated |
|
1213 |
until they reach #KTempAddrEnd. |
|
1214 |
*/ |
|
1215 |
TLinAddr Mmu::TTempMapping::iNextLinAddr = KTempAddr; |
|
1216 |
||
1217 |
||
1218 |
/** |
|
1219 |
Allocate virtual address space required to map a given number of memory pages. |
|
1220 |
||
1221 |
The actual size of allocated virtual allocated needs to accommodate \a aNumPages |
|
1222 |
number of pages of any colour. For example: if \a aNumPages == 4 and #KPageColourCount == 4, |
|
1223 |
then at least 7 pages are required. |
|
1224 |
||
1225 |
@param aNumPages Maximum number of pages that can be mapped into this temporary mapping. |
|
1226 |
||
1227 |
@pre Called in single threaded content (boot) only. |
|
1228 |
||
1229 |
@pre #iNextLinAddr points to virtual page with zero colour. |
|
1230 |
@post #iNextLinAddr points to virtual page with zero colour. |
|
1231 |
*/ |
|
1232 |
void Mmu::TTempMapping::Alloc(TUint aNumPages) |
|
1233 |
{ |
|
1234 |
__NK_ASSERT_DEBUG(aNumPages<=(KTempAddrEnd-KTempAddr)/KPageSize); |
|
1235 |
||
1236 |
// This runs during the boot only (single threaded context) so the access to iNextLinAddr is not guarded by any mutex. |
|
1237 |
TLinAddr tempAddr = iNextLinAddr; |
|
1238 |
TUint numPages = (KPageColourMask+aNumPages+KPageColourMask)&~KPageColourMask; |
|
1239 |
iNextLinAddr = tempAddr+numPages*KPageSize; |
|
1240 |
||
1241 |
__NK_ASSERT_ALWAYS(iNextLinAddr<=KTempAddrEnd); |
|
1242 |
||
1243 |
__NK_ASSERT_DEBUG(iSize==0); |
|
1244 |
iLinAddr = tempAddr; |
|
1245 |
MmuLock::Lock(); |
|
1246 |
iPtePtr = Mmu::PtePtrFromLinAddr(tempAddr,KKernelOsAsid); |
|
1247 |
__NK_ASSERT_DEBUG(iPtePtr); |
|
1248 |
MmuLock::Unlock(); |
|
1249 |
iBlankPte = TheMmu.iTempPteCached; |
|
1250 |
iSize = aNumPages; |
|
1251 |
iCount = 0; |
|
1252 |
||
1253 |
TRACEB(("Mmu::TTempMapping::Alloc(%d) iLinAddr=0x%08x, iPtePtr=0x%08x",aNumPages,iLinAddr,iPtePtr)); |
|
1254 |
} |
|
1255 |
||
1256 |
||
1257 |
/** |
|
1258 |
Map a single physical page into this temporary mapping. |
|
1259 |
||
1260 |
Supervisor read/write access and EMemoryAttributeStandard memory attributes apply. |
|
1261 |
||
1262 |
@param aPage The physical page to map. |
|
1263 |
@param aColour The required colour for the mapping. |
|
1264 |
||
1265 |
@return The linear address at which the page is mapped. |
|
1266 |
*/ |
|
1267 |
TLinAddr Mmu::TTempMapping::Map(TPhysAddr aPage, TUint aColour) |
|
1268 |
{ |
|
1269 |
__NK_ASSERT_DEBUG(iSize>=1); |
|
1270 |
__NK_ASSERT_DEBUG(iCount==0); |
|
1271 |
||
102
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1272 |
return Map(aPage, aColour, iBlankPte); |
0 | 1273 |
} |
1274 |
||
102
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1275 |
|
0 | 1276 |
/** |
1277 |
Map a single physical page into this temporary mapping using the given page table entry (PTE) value. |
|
1278 |
||
1279 |
@param aPage The physical page to map. |
|
1280 |
@param aColour The required colour for the mapping. |
|
1281 |
@param aBlankPte The PTE value to use for mapping the page, |
|
1282 |
with the physical address component equal to zero. |
|
1283 |
||
1284 |
@return The linear address at which the page is mapped. |
|
1285 |
*/ |
|
1286 |
TLinAddr Mmu::TTempMapping::Map(TPhysAddr aPage, TUint aColour, TPte aBlankPte) |
|
1287 |
{ |
|
1288 |
__NK_ASSERT_DEBUG(iSize>=1); |
|
1289 |
__NK_ASSERT_DEBUG(iCount==0); |
|
102
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1290 |
__NK_ASSERT_DEBUG(!(aBlankPte & ~KPageMask)); |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1291 |
|
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1292 |
TUint colour = aColour & KPageColourMask; |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1293 |
TLinAddr addr = iLinAddr + (colour << KPageShift); |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1294 |
TPte* pPte = iPtePtr + colour; |
0 | 1295 |
iColour = colour; |
1296 |
||
102
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1297 |
__ASSERT_DEBUG(*pPte == KPteUnallocatedEntry, MM::Panic(MM::ETempMappingAlreadyInUse)); |
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1298 |
*pPte = (aPage & ~KPageMask) | aBlankPte; |
0 | 1299 |
CacheMaintenance::SinglePteUpdated((TLinAddr)pPte); |
102
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1300 |
InvalidateTLBForPage(addr | KKernelOsAsid); |
0 | 1301 |
|
1302 |
iCount = 1; |
|
1303 |
return addr; |
|
1304 |
} |
|
1305 |
||
1306 |
||
1307 |
/** |
|
1308 |
Map a number of physical pages into this temporary mapping. |
|
1309 |
||
1310 |
Supervisor read/write access and EMemoryAttributeStandard memory attributes apply. |
|
1311 |
||
1312 |
@param aPages The array of physical pages to map. |
|
1313 |
@param aCount The number of pages to map. |
|
1314 |
@param aColour The required colour for the first page. |
|
1315 |
Consecutive pages will be coloured accordingly. |
|
1316 |
||
1317 |
@return The linear address at which the first page is mapped. |
|
1318 |
*/ |
|
1319 |
TLinAddr Mmu::TTempMapping::Map(TPhysAddr* aPages, TUint aCount, TUint aColour) |
|
1320 |
{ |
|
1321 |
__NK_ASSERT_DEBUG(iSize>=aCount); |
|
1322 |
__NK_ASSERT_DEBUG(iCount==0); |
|
1323 |
||
1324 |
TUint colour = aColour&KPageColourMask; |
|
1325 |
TLinAddr addr = iLinAddr+(colour<<KPageShift); |
|
1326 |
TPte* pPte = iPtePtr+colour; |
|
1327 |
iColour = colour; |
|
1328 |
||
1329 |
for(TUint i=0; i<aCount; ++i) |
|
1330 |
{ |
|
1331 |
__ASSERT_DEBUG(pPte[i]==KPteUnallocatedEntry,MM::Panic(MM::ETempMappingAlreadyInUse)); |
|
1332 |
pPte[i] = (aPages[i]&~KPageMask) | iBlankPte; |
|
1333 |
CacheMaintenance::SinglePteUpdated((TLinAddr)&pPte[i]); |
|
1334 |
InvalidateTLBForPage((addr+i*KPageSize)|KKernelOsAsid); |
|
1335 |
} |
|
1336 |
||
1337 |
iCount = aCount; |
|
1338 |
return addr; |
|
1339 |
} |
|
1340 |
||
1341 |
||
1342 |
/** |
|
1343 |
Unmap all pages from this temporary mapping. |
|
1344 |
||
1345 |
@param aIMBRequired True if IMB barrier is required prior unmapping. |
|
1346 |
*/ |
|
1347 |
void Mmu::TTempMapping::Unmap(TBool aIMBRequired) |
|
1348 |
{ |
|
1349 |
__NK_ASSERT_DEBUG(iSize>=1); |
|
1350 |
if(aIMBRequired) |
|
1351 |
CacheMaintenance::CodeChanged(iLinAddr+iColour*KPageSize,iCount*KPageSize); |
|
1352 |
Unmap(); |
|
1353 |
} |
|
1354 |
||
1355 |
||
1356 |
/** |
|
1357 |
Unmap all pages from this temporary mapping. |
|
1358 |
*/ |
|
1359 |
void Mmu::TTempMapping::Unmap() |
|
1360 |
{ |
|
1361 |
__NK_ASSERT_DEBUG(iSize>=1); |
|
1362 |
||
1363 |
TUint colour = iColour; |
|
1364 |
TLinAddr addr = iLinAddr+(colour<<KPageShift); |
|
1365 |
TPte* pPte = iPtePtr+colour; |
|
102
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1366 |
|
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1367 |
while(iCount) |
0 | 1368 |
{ |
1369 |
*pPte = KPteUnallocatedEntry; |
|
1370 |
CacheMaintenance::SinglePteUpdated((TLinAddr)pPte); |
|
1371 |
InvalidateTLBForPage(addr|KKernelOsAsid); |
|
1372 |
addr += KPageSize; |
|
1373 |
++pPte; |
|
102
ef2a444a7410
Revision: 201018
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
90
diff
changeset
|
1374 |
--iCount; |
0 | 1375 |
} |
1376 |
} |
|
1377 |
||
36
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
31
diff
changeset
|
1378 |
#ifdef __SMP__ |
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
31
diff
changeset
|
1379 |
/** |
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
31
diff
changeset
|
1380 |
Dummy IPI to be invoked when a thread's alias pde members are updated remotely |
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
31
diff
changeset
|
1381 |
by another thread. |
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
31
diff
changeset
|
1382 |
|
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
31
diff
changeset
|
1383 |
@internalComponent |
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
31
diff
changeset
|
1384 |
*/ |
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
31
diff
changeset
|
1385 |
class TAliasIPI : public TGenericIPI |
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
31
diff
changeset
|
1386 |
{ |
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
31
diff
changeset
|
1387 |
public: |
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
31
diff
changeset
|
1388 |
static void RefreshIsr(TGenericIPI*); |
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
31
diff
changeset
|
1389 |
void RefreshAlias(); |
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
31
diff
changeset
|
1390 |
}; |
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
31
diff
changeset
|
1391 |
|
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
31
diff
changeset
|
1392 |
|
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
31
diff
changeset
|
1393 |
/** |
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
31
diff
changeset
|
1394 |
Dummy isr method. |
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
31
diff
changeset
|
1395 |
*/ |
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
31
diff
changeset
|
1396 |
void TAliasIPI::RefreshIsr(TGenericIPI*) |
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
31
diff
changeset
|
1397 |
{ |
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
31
diff
changeset
|
1398 |
TRACE2(("TAliasIPI")); |
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
31
diff
changeset
|
1399 |
} |
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
31
diff
changeset
|
1400 |
|
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
31
diff
changeset
|
1401 |
|
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
31
diff
changeset
|
1402 |
/** |
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
31
diff
changeset
|
1403 |
Queue the dummy IPI on all other processors. This ensures that DoProcessSwitch will |
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
31
diff
changeset
|
1404 |
have completed updating iAliasPdePtr once this method returns. |
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
31
diff
changeset
|
1405 |
*/ |
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
31
diff
changeset
|
1406 |
void TAliasIPI::RefreshAlias() |
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
31
diff
changeset
|
1407 |
{ |
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
31
diff
changeset
|
1408 |
NKern::Lock(); |
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
31
diff
changeset
|
1409 |
QueueAllOther(&RefreshIsr); |
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
31
diff
changeset
|
1410 |
NKern::Unlock(); |
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
31
diff
changeset
|
1411 |
WaitCompletion(); |
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
31
diff
changeset
|
1412 |
} |
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
31
diff
changeset
|
1413 |
|
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
31
diff
changeset
|
1414 |
|
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
31
diff
changeset
|
1415 |
/** |
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
31
diff
changeset
|
1416 |
Perform a dummy ipi on all the other processors to ensure if any of them are |
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
31
diff
changeset
|
1417 |
executing DoProcessSwitch they will see the new value of iAliasPde before they |
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
31
diff
changeset
|
1418 |
update iAliasPdePtr or will finish updating iAliasPdePtr before we continue. |
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
31
diff
changeset
|
1419 |
This works as DoProcessSwitch() has interrupts disabled while reading iAliasPde |
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
31
diff
changeset
|
1420 |
and updating iAliasPdePtr. |
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
31
diff
changeset
|
1421 |
*/ |
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
31
diff
changeset
|
1422 |
void BroadcastAliasRefresh() |
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
31
diff
changeset
|
1423 |
{ |
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
31
diff
changeset
|
1424 |
TAliasIPI ipi; |
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
31
diff
changeset
|
1425 |
ipi.RefreshAlias(); |
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
31
diff
changeset
|
1426 |
} |
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
31
diff
changeset
|
1427 |
#endif //__SMP__ |
0 | 1428 |
|
1429 |
/** |
|
1430 |
Remove any thread IPC aliases which use the specified page table. |
|
1431 |
This is used by the page table allocator when a page table is freed. |
|
1432 |
||
1433 |
@pre #PageTablesLockIsHeld |
|
1434 |
*/ |
|
1435 |
void Mmu::RemoveAliasesForPageTable(TPhysAddr aPageTable) |
|
1436 |
{ |
|
1437 |
__NK_ASSERT_DEBUG(PageTablesLockIsHeld()); |
|
1438 |
||
1439 |
MmuLock::Lock(); |
|
1440 |
||
1441 |
SDblQue checkedList; |
|
1442 |
||
1443 |
TUint ptId = aPageTable>>KPageTableShift; |
|
1444 |
while(!iAliasList.IsEmpty()) |
|
1445 |
{ |
|
1446 |
SDblQueLink* next = iAliasList.First()->Deque(); |
|
1447 |
checkedList.Add(next); |
|
1448 |
DMemModelThread* thread = (DMemModelThread*)((TInt)next-_FOFF(DMemModelThread,iAliasLink)); |
|
1449 |
if((thread->iAliasPde>>KPageTableShift)==ptId) |
|
1450 |
{ |
|
1451 |
// the page table is being aliased by the thread, so remove it... |
|
1452 |
TRACE2(("Thread %O RemoveAliasesForPageTable", this)); |
|
1453 |
thread->iAliasPde = KPdeUnallocatedEntry; |
|
1454 |
#ifdef __SMP__ // we need to also unmap the page table in case thread is running on another core... |
|
36
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
31
diff
changeset
|
1455 |
|
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
31
diff
changeset
|
1456 |
// Ensure other processors see the update to iAliasPde. |
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
31
diff
changeset
|
1457 |
BroadcastAliasRefresh(); |
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
31
diff
changeset
|
1458 |
|
0 | 1459 |
*thread->iAliasPdePtr = KPdeUnallocatedEntry; |
36
538db54a451d
Revision: 201003
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
31
diff
changeset
|
1460 |
|
0 | 1461 |
SinglePdeUpdated(thread->iAliasPdePtr); |
1462 |
__NK_ASSERT_DEBUG((thread->iAliasLinAddr&KPageMask)==0); |
|
1463 |
// Invalidate the tlb for the page using os asid of the process that created the alias |
|
1464 |
// this is safe as the os asid will be valid as thread must be running otherwise the alias |
|
1465 |
// would have been removed. |
|
1466 |
InvalidateTLBForPage(thread->iAliasLinAddr | ((DMemModelProcess*)thread->iOwningProcess)->OsAsid()); |
|
1467 |
// note, race condition with 'thread' updating its iAliasLinAddr is |
|
1468 |
// not a problem because 'thread' will not the be accessing the aliased |
|
1469 |
// region and will take care of invalidating the TLB. |
|
1470 |
#endif |
|
1471 |
} |
|
1472 |
MmuLock::Flash(); |
|
1473 |
} |
|
1474 |
||
1475 |
// copy checkedList back to iAliasList |
|
1476 |
iAliasList.MoveFrom(&checkedList); |
|
1477 |
||
1478 |
MmuLock::Unlock(); |
|
1479 |
} |
|
1480 |
||
1481 |
||
1482 |
void DMemModelThread::RefreshAlias() |
|
1483 |
{ |
|
1484 |
if(iAliasLinAddr) |
|
1485 |
{ |
|
1486 |
TRACE2(("Thread %O RefreshAlias", this)); |
|
1487 |
// Get the os asid, this is the current thread so no need to open a reference. |
|
1488 |
TUint thisAsid = ((DMemModelProcess*)iOwningProcess)->OsAsid(); |
|
1489 |
MmuLock::Lock(); |
|
1490 |
TInt osAsid = iAliasProcess->OsAsid(); |
|
1491 |
TPde pde = *Mmu::PageDirectoryEntry(osAsid,iAliasTarget); |
|
1492 |
iAliasPde = pde; |
|
1493 |
*iAliasPdePtr = pde; |
|
1494 |
SinglePdeUpdated(iAliasPdePtr); |
|
1495 |
InvalidateTLBForPage(iAliasLinAddr|thisAsid); |
|
1496 |
MmuLock::Unlock(); |
|
1497 |
} |
|
1498 |
} |
|
1499 |
||
1500 |
||
1501 |
||
1502 |
// |
|
1503 |
// Mapping/unmapping functions |
|
1504 |
// |
|
1505 |
||
1506 |
||
1507 |
/** |
|
1508 |
Modify page table entries (PTEs) so they map the given memory pages. |
|
1509 |
Entries are only updated if the current state of the corresponding page |
|
1510 |
is RPageArray::ECommitted. |
|
1511 |
||
1512 |
@param aPtePtr Pointer into a page table for the PTE of the first page. |
|
1513 |
@param aCount The number of pages to modify. |
|
1514 |
@param aPages Pointer to the entry for the first page in a memory object's #RPageArray. |
|
1515 |
Each entry contains the physical address of a page together with its |
|
1516 |
current state (RPageArray::TState). |
|
1517 |
@param aBlankPte The value to use for each PTE, with the physical address component equal |
|
1518 |
to zero. |
|
1519 |
||
1520 |
@return False, if the page table no longer maps any entries and may be freed. |
|
1521 |
True otherwise, to indicate that the page table is still needed. |
|
1522 |
||
1523 |
@pre #MmuLock held. |
|
1524 |
@post #MmuLock held and has not been released by this function. |
|
1525 |
*/ |
|
1526 |
TBool Mmu::MapPages(TPte* const aPtePtr, const TUint aCount, TPhysAddr* aPages, TPte aBlankPte) |
|
1527 |
{ |
|
1528 |
__NK_ASSERT_DEBUG(MmuLock::IsHeld()); |
|
1529 |
__NK_ASSERT_DEBUG(aCount); |
|
1530 |
__NK_ASSERT_DEBUG(aBlankPte!=KPteUnallocatedEntry); |
|
1531 |
||
1532 |
TUint count = 0; |
|
1533 |
if(aCount==1) |
|
1534 |
{ |
|
1535 |
// get page to map... |
|
1536 |
TPhysAddr pagePhys = *aPages; |
|
1537 |
TPte pte = *aPtePtr; |
|
1538 |
if(!RPageArray::TargetStateIsCommitted(pagePhys)) |
|
1539 |
goto done; // page no longer needs mapping |
|
1540 |
||
1541 |
// clear type flags... |
|
1542 |
pagePhys &= ~KPageMask; |
|
1543 |
||
1544 |
// check nobody has already mapped the page... |
|
1545 |
if(pte!=KPteUnallocatedEntry) |
|
1546 |
{ |
|
1547 |
// already mapped... |
|
1548 |
#ifdef _DEBUG |
|
1549 |
if((pte^pagePhys)>=TPte(KPageSize)) |
|
1550 |
{ |
|
1551 |
// but different! |
|
1552 |
Kern::Printf("Mmu::MapPages already mapped %x->%x",pagePhys,pte); |
|
1553 |
__NK_ASSERT_DEBUG(0); |
|
1554 |
} |
|
1555 |
#endif |
|
1556 |
return true; // return true to keep page table (it already had at least page mapped) |
|
1557 |
} |
|
1558 |
||
1559 |
// map page... |
|
1560 |
pte = pagePhys|aBlankPte; |
|
1561 |
TRACE2(("!PTE %x=%x",aPtePtr,pte)); |
|
1562 |
*aPtePtr = pte; |
|
1563 |
count = 1; |
|
1564 |
||
1565 |
// clean cache... |
|
1566 |
CacheMaintenance::SinglePteUpdated((TLinAddr)aPtePtr); |
|
1567 |
} |
|
1568 |
else |
|
1569 |
{ |
|
1570 |
// check we are only updating a single page table... |
|
1571 |
__NK_ASSERT_DEBUG(((TLinAddr(aPtePtr)^TLinAddr(aPtePtr+aCount-1))>>KPageTableShift)==0); |
|
1572 |
||
1573 |
// map pages... |
|
1574 |
TPte* pPte = aPtePtr; |
|
1575 |
TPte* pPteEnd = aPtePtr+aCount; |
|
1576 |
do |
|
1577 |
{ |
|
1578 |
// map page... |
|
1579 |
TPhysAddr pagePhys = *aPages++; |
|
1580 |
TPte pte = *pPte++; |
|
1581 |
if(RPageArray::TargetStateIsCommitted(pagePhys)) |
|
1582 |
{ |
|
1583 |
// clear type flags... |
|
1584 |
pagePhys &= ~KPageMask; |
|
1585 |
||
1586 |
// page not being freed, so try and map it... |
|
1587 |
if(pte!=KPteUnallocatedEntry) |
|
1588 |
{ |
|
1589 |
// already mapped... |
|
1590 |
#ifdef _DEBUG |
|
1591 |
if((pte^pagePhys)>=TPte(KPageSize)) |
|
1592 |
{ |
|
1593 |
// but different! |
|
1594 |
Kern::Printf("Mmu::MapPages already mapped %x->%x",pagePhys,pte); |
|
1595 |
__NK_ASSERT_DEBUG(0); |
|
1596 |
} |
|
1597 |
#endif |
|
1598 |
} |
|
1599 |
else |
|
1600 |
{ |
|
1601 |
// map page... |
|
1602 |
pte = pagePhys|aBlankPte; |
|
1603 |
TRACE2(("!PTE %x=%x",pPte-1,pte)); |
|
1604 |
pPte[-1] = pte; |
|
1605 |
++count; |
|
1606 |
} |
|
1607 |
} |
|
1608 |
} |
|
1609 |
while(pPte!=pPteEnd); |
|
1610 |
||
1611 |
// clean cache... |
|
1612 |
CacheMaintenance::MultiplePtesUpdated((TLinAddr)aPtePtr,(TLinAddr)pPte-(TLinAddr)aPtePtr); |
|
1613 |
} |
|
1614 |
||
1615 |
done: |
|
1616 |
// update page counts... |
|
1617 |
SPageTableInfo* pti = SPageTableInfo::FromPtPtr(aPtePtr); |
|
1618 |
count = pti->IncPageCount(count); |
|
1619 |
TRACE2(("pt %x page count=%d",TLinAddr(aPtePtr)&~KPageTableMask,pti->PageCount())); |
|
1620 |
__NK_ASSERT_DEBUG(pti->CheckPageCount()); |
|
1621 |
||
1622 |
// see if page table needs freeing... |
|
1623 |
TUint keepPt = count | pti->PermanenceCount(); |
|
1624 |
||
1625 |
__NK_ASSERT_DEBUG(!pti->IsDemandPaged()); // check not demand paged page table |
|
1626 |
||
1627 |
return keepPt; |
|
1628 |
} |
|
1629 |
||
1630 |
||
1631 |
/** |
|
1632 |
Modify page table entries (PTEs) so they map a new page. |
|
1633 |
Entries are only updated if the current state of the corresponding page |
|
1634 |
is RPageArray::ECommitted or RPageArray::EMoving. |
|
1635 |
||
1636 |
@param aPtePtr Pointer into a page table for the PTE of the page. |
|
1637 |
@param aPage Pointer to the entry for the page in a memory object's #RPageArray. |
|
1638 |
The entry contains the physical address of a page together with its |
|
1639 |
current state (RPageArray::TState). |
|
1640 |
@param aBlankPte The value to use for each PTE, with the physical address component equal |
|
1641 |
to zero. |
|
1642 |
||
1643 |
@pre #MmuLock held. |
|
1644 |
@post #MmuLock held and has not been released by this function. |
|
1645 |
*/ |
|
1646 |
void Mmu::RemapPage(TPte* const aPtePtr, TPhysAddr& aPage, TPte aBlankPte) |
|
1647 |
{ |
|
1648 |
__NK_ASSERT_DEBUG(MmuLock::IsHeld()); |
|
1649 |
__NK_ASSERT_DEBUG(aBlankPte!=KPteUnallocatedEntry); |
|
1650 |
||
1651 |
// get page to remap... |
|
1652 |
TPhysAddr pagePhys = aPage; |
|
201
43365a9b78a3
Revision: 201027
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
152
diff
changeset
|
1653 |
|
0 | 1654 |
// Only remap the page if it is committed or it is being moved and |
1655 |
// no other operation has been performed on the page. |
|
1656 |
if(!RPageArray::TargetStateIsCommitted(pagePhys)) |
|
1657 |
return; // page no longer needs mapping |
|
201
43365a9b78a3
Revision: 201027
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
152
diff
changeset
|
1658 |
|
0 | 1659 |
// Only remap the page if it is currently mapped, i.e. doesn't have an unallocated pte. |
1660 |
// This will only be true if a new mapping is being added but it hasn't yet updated |
|
1661 |
// all the ptes for the pages that it maps. |
|
1662 |
TPte pte = *aPtePtr; |
|
1663 |
if (pte == KPteUnallocatedEntry) |
|
1664 |
return; |
|
201
43365a9b78a3
Revision: 201027
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
152
diff
changeset
|
1665 |
|
0 | 1666 |
// clear type flags... |
1667 |
pagePhys &= ~KPageMask; |
|
1668 |
||
201
43365a9b78a3
Revision: 201027
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
152
diff
changeset
|
1669 |
// Get the SPageInfo of the page to map. Allow pages without SPageInfos to |
43365a9b78a3
Revision: 201027
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
152
diff
changeset
|
1670 |
// be mapped as when freeing a shadow page may need to remap an unpaged ROM |
43365a9b78a3
Revision: 201027
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
152
diff
changeset
|
1671 |
// page which won't have an SPageInfo. |
0 | 1672 |
SPageInfo* pi = SPageInfo::SafeFromPhysAddr(pagePhys); |
1673 |
if (pi) |
|
1674 |
{ |
|
1675 |
SPageInfo::TPagedState pagedState = pi->PagedState(); |
|
1676 |
if (pagedState != SPageInfo::EUnpaged) |
|
1677 |
{ |
|
201
43365a9b78a3
Revision: 201027
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
152
diff
changeset
|
1678 |
// For paged pages only update the pte if the pte points to the wrong physical |
43365a9b78a3
Revision: 201027
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
152
diff
changeset
|
1679 |
// address or the page is pinned. |
43365a9b78a3
Revision: 201027
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
152
diff
changeset
|
1680 |
if (pagedState != SPageInfo::EPagedPinned) |
0 | 1681 |
{ |
201
43365a9b78a3
Revision: 201027
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
152
diff
changeset
|
1682 |
if ((pte^pagePhys) < TPte(KPageSize)) |
43365a9b78a3
Revision: 201027
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
152
diff
changeset
|
1683 |
return; |
43365a9b78a3
Revision: 201027
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
152
diff
changeset
|
1684 |
if (Mmu::IsPteInaccessible(pte)) |
43365a9b78a3
Revision: 201027
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
152
diff
changeset
|
1685 |
{ |
43365a9b78a3
Revision: 201027
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
152
diff
changeset
|
1686 |
// Updating this pte shouldn't be necessary but it stops random data |
43365a9b78a3
Revision: 201027
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
152
diff
changeset
|
1687 |
// corruption in stressed cases??? |
43365a9b78a3
Revision: 201027
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
152
diff
changeset
|
1688 |
Mmu::MakePteInaccessible(aBlankPte, EFalse); |
43365a9b78a3
Revision: 201027
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
152
diff
changeset
|
1689 |
} |
43365a9b78a3
Revision: 201027
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
152
diff
changeset
|
1690 |
else if (!pi->IsDirty()) |
43365a9b78a3
Revision: 201027
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
152
diff
changeset
|
1691 |
{ |
43365a9b78a3
Revision: 201027
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
152
diff
changeset
|
1692 |
// Ensure that the page is mapped as read only to prevent pages being writable |
43365a9b78a3
Revision: 201027
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
152
diff
changeset
|
1693 |
// without having been marked dirty. |
43365a9b78a3
Revision: 201027
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
152
diff
changeset
|
1694 |
Mmu::MakePteInaccessible(aBlankPte, ETrue); |
43365a9b78a3
Revision: 201027
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
152
diff
changeset
|
1695 |
} |
43365a9b78a3
Revision: 201027
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
152
diff
changeset
|
1696 |
} |
43365a9b78a3
Revision: 201027
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
152
diff
changeset
|
1697 |
else if (!pi->IsDirty()) |
43365a9b78a3
Revision: 201027
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
152
diff
changeset
|
1698 |
{ |
43365a9b78a3
Revision: 201027
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
152
diff
changeset
|
1699 |
// Ensure that the page is mapped as read only to prevent pages being writable |
43365a9b78a3
Revision: 201027
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
152
diff
changeset
|
1700 |
// without having been marked dirty. |
43365a9b78a3
Revision: 201027
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
152
diff
changeset
|
1701 |
Mmu::MakePteInaccessible(aBlankPte, ETrue); |
0 | 1702 |
} |
1703 |
} |
|
1704 |
} |
|
201
43365a9b78a3
Revision: 201027
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
152
diff
changeset
|
1705 |
|
0 | 1706 |
// Map the page in the page array entry as this is always the physical |
1707 |
// page that the memory object's page should be mapped to. |
|
1708 |
pte = pagePhys|aBlankPte; |
|
1709 |
TRACE2(("!PTE %x=%x",aPtePtr,pte)); |
|
1710 |
*aPtePtr = pte; |
|
201
43365a9b78a3
Revision: 201027
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
152
diff
changeset
|
1711 |
|
0 | 1712 |
// clean cache... |
1713 |
CacheMaintenance::SinglePteUpdated((TLinAddr)aPtePtr); |
|
1714 |
} |
|
1715 |
||
1716 |
||
1717 |
/** |
|
1718 |
Modify page table entries (PTEs) so they no longer map any memory pages. |
|
1719 |
||
1720 |
@param aPtePtr Pointer into a page table for the PTE of the first page. |
|
1721 |
@param aCount The number of pages to modify. |
|
1722 |
||
1723 |
@return False, if the page table no longer maps any entries and may be freed. |
|
1724 |
True otherwise, to indicate that the page table is still needed. |
|
1725 |
||
1726 |
@pre #MmuLock held. |
|
1727 |
@post #MmuLock held and has not been released by this function. |
|
1728 |
*/ |
|
1729 |
TBool Mmu::UnmapPages(TPte* const aPtePtr, TUint aCount) |
|
1730 |
{ |
|
1731 |
__NK_ASSERT_DEBUG(MmuLock::IsHeld()); |
|
1732 |
__NK_ASSERT_DEBUG(aCount); |
|
1733 |
||
1734 |
TUint count = 0; |
|
1735 |
if(aCount==1) |
|
1736 |
{ |
|
1737 |
if(*aPtePtr==KPteUnallocatedEntry) |
|
1738 |
return true; // page already unmapped |
|
1739 |
||
1740 |
// unmap page... |
|
1741 |
++count; |
|
1742 |
TPte pte = KPteUnallocatedEntry; |
|
1743 |
TRACE2(("!PTE %x=%x",aPtePtr,pte)); |
|
1744 |
*aPtePtr = pte; |
|
1745 |
||
1746 |
// clean cache... |
|
1747 |
CacheMaintenance::SinglePteUpdated((TLinAddr)aPtePtr); |
|
1748 |
} |
|
1749 |
else |
|
1750 |
{ |
|
1751 |
// check we are only updating a single page table... |
|
1752 |
__NK_ASSERT_DEBUG(((TLinAddr(aPtePtr)^TLinAddr(aPtePtr+aCount-1))>>KPageTableShift)==0); |
|
1753 |
||
1754 |
// unmap pages... |
|
1755 |
TPte* pPte = aPtePtr; |
|
1756 |
TPte* pPteEnd = aPtePtr+aCount; |
|
1757 |
do |
|
1758 |
{ |
|
1759 |
if(*pPte!=KPteUnallocatedEntry) |
|
1760 |
{ |
|
1761 |
// unmap page... |
|
1762 |
++count; |
|
1763 |
TPte pte = KPteUnallocatedEntry; |
|
1764 |
TRACE2(("!PTE %x=%x",pPte,pte)); |
|
1765 |
*pPte = pte; |
|
1766 |
} |
|
1767 |
} |
|
1768 |
while(++pPte<pPteEnd); |
|
1769 |
||
1770 |
if(!count) |
|
1771 |
return true; // no PTEs changed, so nothing more to do |
|
1772 |
||
1773 |
// clean cache... |
|
1774 |
CacheMaintenance::MultiplePtesUpdated((TLinAddr)aPtePtr,(TLinAddr)pPte-(TLinAddr)aPtePtr); |
|
1775 |
} |
|
1776 |
||
1777 |
// update page table info... |
|
1778 |
SPageTableInfo* pti = SPageTableInfo::FromPtPtr(aPtePtr); |
|
1779 |
count = pti->DecPageCount(count); |
|
1780 |
TRACE2(("pt %x page count=%d",TLinAddr(aPtePtr)&~KPageTableMask,count)); |
|
1781 |
__NK_ASSERT_DEBUG(pti->CheckPageCount()); |
|
1782 |
||
1783 |
// see if page table needs freeing... |
|
1784 |
TUint keepPt = count | pti->PermanenceCount(); |
|
1785 |
||
1786 |
return keepPt; |
|
1787 |
} |
|
1788 |
||
1789 |
||
1790 |
/** |
|
1791 |
Modify page table entries (PTEs) so they no longer map the given memory pages. |
|
1792 |
Entries are only updated if the current state of the corresponding page |
|
1793 |
is 'decommitted' i.e. RPageArray::TargetStateIsDecommitted returns true. |
|
1794 |
||
1795 |
@param aPtePtr Pointer into a page table for the PTE of the first page. |
|
1796 |
@param aCount The number of pages to modify. |
|
1797 |
@param aPages Pointer to the entry for the first page in a memory object's #RPageArray. |
|
1798 |
Each entry contains the physical address of a page together with its |
|
1799 |
current state (RPageArray::TState). |
|
1800 |
||
1801 |
@return False, if the page table no longer maps any entries and may be freed. |
|
1802 |
True otherwise, to indicate that the page table is still needed. |
|
1803 |
||
1804 |
@pre #MmuLock held. |
|
1805 |
@post #MmuLock held and has not been released by this function. |
|
1806 |
*/ |
|
1807 |
TBool Mmu::UnmapPages(TPte* const aPtePtr, TUint aCount, TPhysAddr* aPages) |
|
1808 |
{ |
|
1809 |
__NK_ASSERT_DEBUG(MmuLock::IsHeld()); |
|
1810 |
__NK_ASSERT_DEBUG(aCount); |
|
1811 |
||
1812 |
TUint count = 0; |
|
1813 |
if(aCount==1) |
|
1814 |
{ |
|
1815 |
if(*aPtePtr==KPteUnallocatedEntry) |
|
1816 |
return true; // page already unmapped |
|
1817 |
||
1818 |
if(!RPageArray::TargetStateIsDecommitted(*aPages)) |
|
1819 |
return true; // page has been reallocated |
|
1820 |
||
1821 |
// unmap page... |
|
1822 |
++count; |
|
1823 |
TPte pte = KPteUnallocatedEntry; |
|
1824 |
TRACE2(("!PTE %x=%x",aPtePtr,pte)); |
|
1825 |
*aPtePtr = pte; |
|
1826 |
||
1827 |
// clean cache... |
|
1828 |
CacheMaintenance::SinglePteUpdated((TLinAddr)aPtePtr); |
|
1829 |
} |
|
1830 |
else |
|
1831 |
{ |
|
1832 |
// check we are only updating a single page table... |
|
1833 |
__NK_ASSERT_DEBUG(((TLinAddr(aPtePtr)^TLinAddr(aPtePtr+aCount-1))>>KPageTableShift)==0); |
|
1834 |
||
1835 |
// unmap pages... |
|
1836 |
TPte* pPte = aPtePtr; |
|
1837 |
TPte* pPteEnd = aPtePtr+aCount; |
|
1838 |
do |
|
1839 |
{ |
|
1840 |
if(RPageArray::TargetStateIsDecommitted(*aPages++) && *pPte!=KPteUnallocatedEntry) |
|
1841 |
{ |
|
1842 |
// unmap page... |
|
1843 |
++count; |
|
1844 |
TPte pte = KPteUnallocatedEntry; |
|
1845 |
TRACE2(("!PTE %x=%x",pPte,pte)); |
|
1846 |
*pPte = pte; |
|
1847 |
} |
|
1848 |
} |
|
1849 |
while(++pPte<pPteEnd); |
|
1850 |
||
1851 |
if(!count) |
|
1852 |
return true; // no PTEs changed, so nothing more to do |
|
1853 |
||
1854 |
// clean cache... |
|
1855 |
CacheMaintenance::MultiplePtesUpdated((TLinAddr)aPtePtr,(TLinAddr)pPte-(TLinAddr)aPtePtr); |
|
1856 |
} |
|
1857 |
||
1858 |
// update page table info... |
|
1859 |
SPageTableInfo* pti = SPageTableInfo::FromPtPtr(aPtePtr); |
|
1860 |
count = pti->DecPageCount(count); |
|
1861 |
TRACE2(("pt %x page count=%d",TLinAddr(aPtePtr)&~KPageTableMask,count)); |
|
1862 |
__NK_ASSERT_DEBUG(pti->CheckPageCount()); |
|
1863 |
||
1864 |
// see if page table needs freeing... |
|
1865 |
TUint keepPt = count | pti->PermanenceCount(); |
|
1866 |
||
1867 |
return keepPt; |
|
1868 |
} |
|
1869 |
||
1870 |
||
1871 |
/** |
|
1872 |
Modify page table entries (PTEs) so the given memory pages are not accessible. |
|
1873 |
Entries are only updated if the current state of the corresponding page |
|
1874 |
is RPageArray::ERestrictingNA. |
|
1875 |
||
1876 |
@param aPtePtr Pointer into a page table for the PTE of the first page. |
|
1877 |
@param aCount The number of pages to modify. |
|
1878 |
@param aPages Pointer to the entry for the first page in a memory object's #RPageArray. |
|
1879 |
Each entry contains the physical address of a page together with its |
|
1880 |
current state (RPageArray::TState). |
|
1881 |
||
1882 |
@pre #MmuLock held. |
|
1883 |
@post #MmuLock held and has not been released by this function. |
|
1884 |
*/ |
|
1885 |
void Mmu::RestrictPagesNA(TPte* const aPtePtr, TUint aCount, TPhysAddr* aPages) |
|
1886 |
{ |
|
1887 |
__NK_ASSERT_DEBUG(MmuLock::IsHeld()); |
|
1888 |
__NK_ASSERT_DEBUG(aCount); |
|
1889 |
||
1890 |
if(aCount==1) |
|
1891 |
{ |
|
1892 |
TPhysAddr page = *aPages; |
|
1893 |
TPte pte = *aPtePtr; |
|
1894 |
RPageArray::TState state = RPageArray::State(page); |
|
1895 |
if(state != RPageArray::ERestrictingNA && state != RPageArray::EMoving) |
|
1896 |
return; // page no longer needs restricting |
|
1897 |
||
1898 |
if(pte==KPteUnallocatedEntry) |
|
1899 |
return; // page gone |
|
1900 |
||
1901 |
// restrict page... |
|
1902 |
pte = Mmu::MakePteInaccessible(pte,false); |
|
1903 |
TRACE2(("!PTE %x=%x",aPtePtr,pte)); |
|
1904 |
*aPtePtr = pte; |
|
1905 |
||
1906 |
// clean cache... |
|
1907 |
CacheMaintenance::SinglePteUpdated((TLinAddr)aPtePtr); |
|
1908 |
} |
|
1909 |
else |
|
1910 |
{ |
|
1911 |
// check we are only updating a single page table... |
|
1912 |
__NK_ASSERT_DEBUG(((TLinAddr(aPtePtr)^TLinAddr(aPtePtr+aCount-1))>>KPageTableShift)==0); |
|
1913 |
||
1914 |
// restrict pages... |
|
1915 |
TPte* pPte = aPtePtr; |
|
1916 |
TPte* pPteEnd = aPtePtr+aCount; |
|
1917 |
do |
|
1918 |
{ |
|
1919 |
TPhysAddr page = *aPages++; |
|
1920 |
TPte pte = *pPte++; |
|
1921 |
if(RPageArray::State(page)==RPageArray::ERestrictingNA && pte!=KPteUnallocatedEntry) |
|
1922 |
{ |
|
1923 |
pte = Mmu::MakePteInaccessible(pte,false); |
|
1924 |
TRACE2(("!PTE %x=%x",pPte-1,pte)); |
|
1925 |
pPte[-1] = pte; |
|
1926 |
} |
|
1927 |
} |
|
1928 |
while(pPte<pPteEnd); |
|
1929 |
||
1930 |
// clean cache... |
|
1931 |
CacheMaintenance::MultiplePtesUpdated((TLinAddr)aPtePtr,(TLinAddr)pPte-(TLinAddr)aPtePtr); |
|
1932 |
} |
|
1933 |
} |
|
1934 |
||
1935 |
||
1936 |
/** |
|
1937 |
Modify page table entries (PTEs) so they map the given demand paged memory pages. |
|
1938 |
||
1939 |
Entries are only updated if the current state of the corresponding page |
|
1940 |
is RPageArray::ECommitted. |
|
1941 |
||
1942 |
This function is used for demand paged memory when handling a page fault or |
|
1943 |
memory pinning operation. It will widen the access permission of existing entries |
|
1944 |
if required to match \a aBlankPte and will 'rejuvenate' the page table. |
|
1945 |
||
1946 |
@param aPtePtr Pointer into a page table for the PTE of the first page. |
|
1947 |
@param aCount The number of pages to modify. |
|
1948 |
@param aPages Pointer to the entry for the first page in a memory object's #RPageArray. |
|
1949 |
Each entry contains the physical address of a page together with its |
|
1950 |
current state (RPageArray::TState). |
|
1951 |
@param aBlankPte The value to use for each PTE, with the physical address component equal |
|
1952 |
to zero. |
|
1953 |
||
1954 |
@return False, if the page table no longer maps any entries and may be freed. |
|
1955 |
True otherwise, to indicate that the page table is still needed. |
|
1956 |
||
1957 |
@pre #MmuLock held. |
|
1958 |
@post MmuLock held (but may have been released by this function) |
|
1959 |
*/ |
|
1960 |
TBool Mmu::PageInPages(TPte* const aPtePtr, const TUint aCount, TPhysAddr* aPages, TPte aBlankPte) |
|
1961 |
{ |
|
1962 |
__NK_ASSERT_DEBUG(MmuLock::IsHeld()); |
|
1963 |
__NK_ASSERT_DEBUG(aCount); |
|
1964 |
__NK_ASSERT_DEBUG(aBlankPte!=KPteUnallocatedEntry); |
|
1965 |
||
1966 |
TUint count = 0; |
|
1967 |
||
1968 |
if(aCount==1) |
|
1969 |
{ |
|
1970 |
// get page to map... |
|
1971 |
TPhysAddr page = *aPages; |
|
1972 |
TPte pte = *aPtePtr; |
|
1973 |
if(!RPageArray::TargetStateIsCommitted(page)) |
|
1974 |
goto done; // page no longer needs mapping |
|
1975 |
||
1976 |
#ifdef _DEBUG |
|
1977 |
if(pte!=KPteUnallocatedEntry) |
|
1978 |
{ |
|
1979 |
if ((pte^page)>=TPte(KPageSize) && !Mmu::IsPteInaccessible(pte) && |
|
1980 |
!Mmu::IsPteReadOnly(pte)) |
|
1981 |
{ |
|
1982 |
// Page has been mapped before but the physical address is different |
|
1983 |
// and the page hasn't been moved as it is not inaccessible. |
|
1984 |
Kern::Printf("Mmu::PageInPages already mapped %x->%x",page,pte); |
|
1985 |
__NK_ASSERT_DEBUG(0); |
|
1986 |
} |
|
1987 |
} |
|
1988 |
#endif |
|
1989 |
if(!Mmu::IsPteMoreAccessible(aBlankPte,pte)) |
|
201
43365a9b78a3
Revision: 201027
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
152
diff
changeset
|
1990 |
{ |
43365a9b78a3
Revision: 201027
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
152
diff
changeset
|
1991 |
__NK_ASSERT_DEBUG((pte^page) < (TUint)KPageSize); // Must be the same physical addr. |
0 | 1992 |
return true; // return true to keep page table (it already had at least page mapped) |
201
43365a9b78a3
Revision: 201027
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
152
diff
changeset
|
1993 |
} |
0 | 1994 |
|
1995 |
// remap page with new increased permissions... |
|
1996 |
if(pte==KPteUnallocatedEntry) |
|
1997 |
count = 1; // we'll be adding a new pte entry, count it |
|
1998 |
if(!Mmu::IsPteReadOnly(aBlankPte)) |
|
1999 |
ThePager.SetWritable(*SPageInfo::FromPhysAddr(page)); |
|
2000 |
pte = (page&~KPageMask)|aBlankPte; |
|
2001 |
TRACE2(("!PTE %x=%x",aPtePtr,pte)); |
|
2002 |
*aPtePtr = pte; |
|
2003 |
||
2004 |
// clean cache... |
|
2005 |
CacheMaintenance::SinglePteUpdated((TLinAddr)aPtePtr); |
|
2006 |
} |
|
2007 |
else |
|
2008 |
{ |
|
2009 |
// check we are only updating a single page table... |
|
2010 |
__NK_ASSERT_DEBUG(((TLinAddr(aPtePtr)^TLinAddr(aPtePtr+aCount-1))>>KPageTableShift)==0); |
|
2011 |
||
2012 |
// map pages... |
|
2013 |
TPte* pPte = aPtePtr; |
|
2014 |
TPte* pPteEnd = aPtePtr+aCount; |
|
2015 |
do |
|
2016 |
{ |
|
2017 |
// map page... |
|
2018 |
TPhysAddr page = *aPages++; |
|
2019 |
TPte pte = *pPte++; |
|
2020 |
if(RPageArray::TargetStateIsCommitted(page)) |
|
2021 |
{ |
|
2022 |
#ifdef _DEBUG |
|
2023 |
if(pte!=KPteUnallocatedEntry) |
|
2024 |
{ |
|
2025 |
if ((pte^page)>=TPte(KPageSize) && !Mmu::IsPteInaccessible(pte) && |
|
2026 |
!Mmu::IsPteReadOnly(pte)) |
|
2027 |
{ |
|
2028 |
// Page has been mapped before but the physical address is different |
|
2029 |
// and the page hasn't been moved as it is not inaccessible. |
|
2030 |
Kern::Printf("Mmu::PageInPages already mapped %x->%x",page,pte); |
|
2031 |
__NK_ASSERT_DEBUG(0); |
|
2032 |
} |
|
2033 |
} |
|
2034 |
#endif |
|
2035 |
if(Mmu::IsPteMoreAccessible(aBlankPte,pte)) |
|
2036 |
{ |
|
2037 |
// remap page with new increased permissions... |
|
2038 |
if(pte==KPteUnallocatedEntry) |
|
2039 |
++count; // we'll be adding a new pte entry, count it |
|
2040 |
if(!Mmu::IsPteReadOnly(aBlankPte)) |
|
2041 |
ThePager.SetWritable(*SPageInfo::FromPhysAddr(page)); |
|
2042 |
pte = (page&~KPageMask)|aBlankPte; |
|
2043 |
TRACE2(("!PTE %x=%x",pPte-1,pte)); |
|
2044 |
pPte[-1] = pte; |
|
2045 |
} |
|
201
43365a9b78a3
Revision: 201027
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
152
diff
changeset
|
2046 |
else |
43365a9b78a3
Revision: 201027
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
152
diff
changeset
|
2047 |
__NK_ASSERT_DEBUG((pte^page) < (TUint)KPageSize); // Must be the same physical addr. |
0 | 2048 |
} |
2049 |
} |
|
2050 |
while(pPte!=pPteEnd); |
|
2051 |
||
2052 |
// clean cache... |
|
2053 |
CacheMaintenance::MultiplePtesUpdated((TLinAddr)aPtePtr,(TLinAddr)pPte-(TLinAddr)aPtePtr); |
|
2054 |
} |
|
2055 |
||
2056 |
done: |
|
2057 |
// update page counts... |
|
2058 |
SPageTableInfo* pti = SPageTableInfo::FromPtPtr(aPtePtr); |
|
2059 |
count = pti->IncPageCount(count); |
|
2060 |
TRACE2(("pt %x page count=%d",TLinAddr(aPtePtr)&~KPageTableMask,pti->PageCount())); |
|
2061 |
__NK_ASSERT_DEBUG(pti->CheckPageCount()); |
|
2062 |
||
2063 |
// see if page table needs freeing... |
|
2064 |
TUint keepPt = count | pti->PermanenceCount(); |
|
2065 |
||
2066 |
// rejuvenate demand paged page tables... |
|
2067 |
ThePager.RejuvenatePageTable(aPtePtr); |
|
2068 |
||
2069 |
return keepPt; |
|
2070 |
} |
|
2071 |
||
2072 |
||
2073 |
// |
|
2074 |
// CodeModifier |
|
2075 |
// |
|
2076 |
||
2077 |
#ifdef __DEBUGGER_SUPPORT__ |
|
2078 |
||
2079 |
void DoWriteCode(TUint32* aAddress, TUint32 aValue); |
|
2080 |
||
2081 |
#ifdef __SMP__ |
|
2082 |
||
2083 |
extern "C" void __e32_instruction_barrier(); |
|
2084 |
||
2085 |
class TCodeModifierBroadcast : public TGenericIPI |
|
2086 |
{ |
|
2087 |
public: |
|
2088 |
TCodeModifierBroadcast(TUint32* aAddress, TUint32 aValue); |
|
2089 |
static void Isr(TGenericIPI*); |
|
2090 |
void Go(); |
|
2091 |
public: |
|
2092 |
TUint32* iAddress; |
|
2093 |
TUint32 iValue; |
|
2094 |
volatile TInt iFlag; |
|
2095 |
}; |
|
2096 |
||
2097 |
TCodeModifierBroadcast::TCodeModifierBroadcast(TUint32* aAddress, TUint32 aValue) |
|
2098 |
: iAddress(aAddress), iValue(aValue), iFlag(0) |
|
2099 |
{ |
|
2100 |
} |
|
2101 |
||
2102 |
void TCodeModifierBroadcast::Isr(TGenericIPI* aPtr) |
|
2103 |
{ |
|
2104 |
TCodeModifierBroadcast& a = *(TCodeModifierBroadcast*)aPtr; |
|
2105 |
while (!__e32_atomic_load_acq32(&a.iFlag)) |
|
2106 |
__chill(); |
|
2107 |
#ifdef __BROADCAST_CACHE_MAINTENANCE__ |
|
2108 |
CacheMaintenance::CodeChanged((TLinAddr)a.iAddress, sizeof (TInt), CacheMaintenance::ECodeModifier); // need to do separate Clean-D, Purge-I on each core |
|
2109 |
#else |
|
2110 |
__e32_instruction_barrier(); // synchronize instruction execution |
|
2111 |
#endif |
|
2112 |
} |
|
2113 |
||
2114 |
void TCodeModifierBroadcast::Go() |
|
2115 |
{ |
|
2116 |
NKern::Lock(); |
|
2117 |
QueueAllOther(&Isr); |
|
2118 |
WaitEntry(); // wait for other cores to stop |
|
2119 |
DoWriteCode(iAddress, iValue); |
|
2120 |
iFlag = 1; |
|
2121 |
__e32_instruction_barrier(); // synchronize instruction execution |
|
2122 |
WaitCompletion(); // wait for other cores to resume |
|
2123 |
NKern::Unlock(); |
|
2124 |
} |
|
2125 |
#endif |
|
2126 |
||
2127 |
/** |
|
2128 |
@pre Calling thread must be in critical section |
|
2129 |
@pre CodeSeg mutex held |
|
2130 |
*/ |
|
2131 |
TInt CodeModifier::SafeWriteCode(DProcess* aProcess, TLinAddr aAddress, TInt aSize, TUint aValue, void* aOldValue) |
|
2132 |
{ |
|
2133 |
__ASSERT_CRITICAL; |
|
2134 |
Mmu& m=TheMmu; |
|
2135 |
RamAllocLock::Lock(); |
|
2136 |
MmuLock::Lock(); |
|
2137 |
__UNLOCK_GUARD_START(MmuLock); |
|
2138 |
||
2139 |
// Check aProcess is still alive by opening a reference on its os asid. |
|
2140 |
TInt osAsid = ((DMemModelProcess*)aProcess)->TryOpenOsAsid(); |
|
2141 |
if (osAsid < 0) |
|
2142 |
{ |
|
2143 |
__KTRACE_OPT(KDEBUGGER,Kern::Printf("CodeModifier::SafeWriteCode - zombie process")); |
|
2144 |
__UNLOCK_GUARD_END(MmuLock); |
|
2145 |
MmuLock::Unlock(); |
|
2146 |
RamAllocLock::Unlock(); |
|
2147 |
return KErrBadDescriptor; |
|
2148 |
} |
|
2149 |
||
2150 |
// Find physical address of the page, the breakpoint belongs to |
|
2151 |
TPhysAddr physAddr = Mmu::LinearToPhysical(aAddress, osAsid); |
|
2152 |
__KTRACE_OPT(KDEBUGGER,Kern::Printf("CodeModifier::SafeWriteCode - PA:%x", physAddr)); |
|
2153 |
||
2154 |
||
2155 |
if (physAddr==KPhysAddrInvalid) |
|
2156 |
{ |
|
2157 |
__KTRACE_OPT(KDEBUGGER,Kern::Printf("CodeModifier::SafeWriteCode - invalid VA")); |
|
2158 |
__UNLOCK_GUARD_END(MmuLock); |
|
2159 |
MmuLock::Unlock(); |
|
2160 |
RamAllocLock::Unlock(); |
|
2161 |
// The os asid is no longer required. |
|
2162 |
((DMemModelProcess*)aProcess)->CloseOsAsid(); |
|
2163 |
return KErrBadDescriptor; |
|
2164 |
} |
|
2165 |
||
2166 |
// Temporary map physical page |
|
2167 |
TLinAddr tempAddr = m.MapTemp(physAddr&~KPageMask, aAddress>>KPageShift); |
|
2168 |
tempAddr |= aAddress & KPageMask; |
|
2169 |
__KTRACE_OPT(KDEBUGGER,Kern::Printf("CodeModifier::SafeWriteCode - tempAddr:%x",tempAddr)); |
|
2170 |
||
2171 |
TInt r = KErrBadDescriptor; |
|
2172 |
TUint32* ptr = (TUint32*)(tempAddr&~3); |
|
2173 |
TUint32 oldWord; |
|
2174 |
||
2175 |
if(Kern::SafeRead(ptr,&oldWord,sizeof(oldWord))==0 // safely read the original value... |
|
2176 |
&& Kern::SafeWrite(ptr,&oldWord,sizeof(oldWord))==0 ) // and write it back |
|
2177 |
{ |
|
2178 |
// We have successfully probed the memory by reading and writing to it |
|
2179 |
// so we assume it is now safe to access without generating exceptions. |
|
2180 |
// If this is wrong it will kill the system horribly. |
|
2181 |
||
2182 |
TUint32 newWord; |
|
2183 |
TUint badAlign; |
|
2184 |
TUint shift = (aAddress&3)*8; |
|
2185 |
||
2186 |
switch(aSize) |
|
2187 |
{ |
|
2188 |
case 1: // 1 byte value |
|
2189 |
badAlign = 0; |
|
2190 |
*(TUint8*)aOldValue = oldWord>>shift; |
|
2191 |
newWord = (oldWord&~(0xff<<shift)) | ((aValue&0xff)<<shift); |
|
2192 |
break; |
|
2193 |
||
2194 |
case 2: // 2 byte value |
|
2195 |
badAlign = tempAddr&1; |
|
2196 |
if(!badAlign) |
|
2197 |
*(TUint16*)aOldValue = oldWord>>shift; |
|
2198 |
newWord = (oldWord&~(0xffff<<shift)) | ((aValue&0xffff)<<shift); |
|
2199 |
break; |
|
2200 |
||
2201 |
default: // 4 byte value |
|
2202 |
badAlign = tempAddr&3; |
|
2203 |
if(!badAlign) |
|
2204 |
*(TUint32*)aOldValue = oldWord; |
|
2205 |
newWord = aValue; |
|
2206 |
break; |
|
2207 |
} |
|
2208 |
||
2209 |
if(!badAlign) |
|
2210 |
{ |
|
2211 |
// write the new value... |
|
2212 |
#ifdef __SMP__ |
|
2213 |
TCodeModifierBroadcast b(ptr, newWord); |
|
2214 |
b.Go(); |
|
2215 |
#else |
|
2216 |
DoWriteCode(ptr, newWord); |
|
2217 |
#endif |
|
2218 |
r = KErrNone; |
|
2219 |
} |
|
2220 |
} |
|
2221 |
||
2222 |
__UNLOCK_GUARD_END(MmuLock); |
|
2223 |
m.UnmapTemp(); |
|
2224 |
MmuLock::Unlock(); |
|
2225 |
RamAllocLock::Unlock(); |
|
2226 |
// The os asid is no longer required. |
|
2227 |
((DMemModelProcess*)aProcess)->CloseOsAsid(); |
|
2228 |
return r; |
|
2229 |
} |
|
2230 |
||
2231 |
/** |
|
2232 |
@pre Calling thread must be in critical section |
|
2233 |
@pre CodeSeg mutex held |
|
2234 |
*/ |
|
2235 |
void DoWriteCode(TUint32* aAddress, TUint32 aValue) |
|
2236 |
{ |
|
2237 |
// We do not want to be interrupted by e.g. ISR that will run altered code before IMB-Range. |
|
2238 |
// Therefore, copy data and clean/invalidate caches with interrupts disabled. |
|
2239 |
TInt irq = NKern::DisableAllInterrupts(); |
|
2240 |
*aAddress = aValue; |
|
2241 |
CacheMaintenance::CodeChanged((TLinAddr)aAddress, sizeof(TUint32), CacheMaintenance::ECodeModifier); |
|
2242 |
NKern::RestoreInterrupts(irq); |
|
2243 |
} |
|
2244 |
||
2245 |
#endif //__DEBUGGER_SUPPORT__ |
|
2246 |
||
2247 |
||
2248 |
||
2249 |
// |
|
2250 |
// Virtual pinning |
|
2251 |
// |
|
2252 |
||
2253 |
TInt M::CreateVirtualPinObject(TVirtualPinObject*& aPinObject) |
|
2254 |
{ |
|
2255 |
aPinObject = (TVirtualPinObject*)new DVirtualPinMapping; |
|
2256 |
return aPinObject != NULL ? KErrNone : KErrNoMemory; |
|
2257 |
} |
|
2258 |
||
2259 |
TInt M::PinVirtualMemory(TVirtualPinObject* aPinObject, TLinAddr aStart, TUint aSize, DThread* aThread) |
|
2260 |
{ |
|
39
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2261 |
__ASSERT_CRITICAL; |
0 | 2262 |
TUint offsetInMapping; |
2263 |
TUint mapInstanceCount; |
|
2264 |
DMemoryMapping* mapping = MM::FindMappingInThread( (DMemModelThread*)aThread, |
|
2265 |
aStart, |
|
2266 |
aSize, |
|
2267 |
offsetInMapping, |
|
2268 |
mapInstanceCount); |
|
2269 |
TInt r = KErrBadDescriptor; |
|
2270 |
if (mapping) |
|
2271 |
{ |
|
2272 |
TInt count = ((aStart & KPageMask) + aSize + KPageMask) >> KPageShift; |
|
2273 |
if(mapping->IsPinned()) |
|
2274 |
{ |
|
2275 |
// Mapping for specified virtual address is pinned so we don't need to |
|
2276 |
// do anything. Also, we can't safely pin the memory in this case |
|
2277 |
// anyway, as pinned mappings may move between memory objects |
|
2278 |
r = KErrNone; |
|
2279 |
} |
|
2280 |
else |
|
2281 |
{ |
|
2282 |
MmuLock::Lock(); |
|
2283 |
DMemoryObject* memory = mapping->Memory(); |
|
2284 |
if (mapInstanceCount != mapping->MapInstanceCount() || |
|
2285 |
!memory || !memory->IsDemandPaged()) |
|
2286 |
{ |
|
2287 |
// mapping has been reused, no memory, or it's not paged, so no need to pin... |
|
2288 |
MmuLock::Unlock(); |
|
2289 |
r = KErrNone; |
|
2290 |
} |
|
2291 |
else |
|
2292 |
{ |
|
2293 |
// paged memory needs pinning... |
|
2294 |
// Open a reference on the memory so it doesn't get deleted. |
|
2295 |
memory->Open(); |
|
2296 |
MmuLock::Unlock(); |
|
2297 |
||
2298 |
TUint startInMemory = (offsetInMapping >> KPageShift) + mapping->iStartIndex; |
|
2299 |
r = ((DVirtualPinMapping*)aPinObject)->Pin( memory, startInMemory, count, mapping->Permissions(), |
|
2300 |
mapping, mapInstanceCount); |
|
2301 |
memory->Close(); |
|
2302 |
} |
|
2303 |
} |
|
2304 |
mapping->Close(); |
|
39
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2305 |
} |
0 | 2306 |
return r; |
2307 |
} |
|
2308 |
||
2309 |
TInt M::CreateAndPinVirtualMemory(TVirtualPinObject*& aPinObject, TLinAddr aStart, TUint aSize) |
|
2310 |
{ |
|
39
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2311 |
__ASSERT_CRITICAL; |
0 | 2312 |
aPinObject = 0; |
2313 |
TUint offsetInMapping; |
|
2314 |
TUint mapInstanceCount; |
|
2315 |
DMemoryMapping* mapping = MM::FindMappingInThread( (DMemModelThread*)&Kern::CurrentThread(), |
|
2316 |
aStart, |
|
2317 |
aSize, |
|
2318 |
offsetInMapping, |
|
2319 |
mapInstanceCount); |
|
2320 |
TInt r = KErrBadDescriptor; |
|
2321 |
if (mapping) |
|
2322 |
{ |
|
2323 |
TInt count = ((aStart & KPageMask) + aSize + KPageMask) >> KPageShift; |
|
2324 |
if(mapping->IsPinned()) |
|
2325 |
{ |
|
2326 |
// Mapping for specified virtual address is pinned so we don't need to |
|
2327 |
// do anything. Also, we can't safely pin the memory in this case |
|
2328 |
// anyway, as pinned mappings may move between memory objects |
|
2329 |
r = KErrNone; |
|
2330 |
} |
|
2331 |
else |
|
2332 |
{ |
|
2333 |
MmuLock::Lock(); |
|
2334 |
DMemoryObject* memory = mapping->Memory(); |
|
2335 |
if (mapInstanceCount != mapping->MapInstanceCount() || |
|
2336 |
!memory || !memory->IsDemandPaged()) |
|
2337 |
{ |
|
2338 |
// mapping has been reused, no memory, or it's not paged, so no need to pin... |
|
2339 |
MmuLock::Unlock(); |
|
2340 |
r = KErrNone; |
|
2341 |
} |
|
2342 |
else |
|
2343 |
{// The memory is demand paged so create a pin object and pin it. |
|
2344 |
// Open a reference on the memory so it doesn't get deleted. |
|
2345 |
memory->Open(); |
|
2346 |
MmuLock::Unlock(); |
|
2347 |
r = CreateVirtualPinObject(aPinObject); |
|
2348 |
if (r == KErrNone) |
|
2349 |
{ |
|
2350 |
TUint startInMemory = (offsetInMapping >> KPageShift) + mapping->iStartIndex; |
|
2351 |
r = ((DVirtualPinMapping*)aPinObject)->Pin( memory, startInMemory, count, mapping->Permissions(), |
|
2352 |
mapping, mapInstanceCount); |
|
2353 |
if (r != KErrNone) |
|
2354 |
{// Failed to pin the memory so pin object is not required. |
|
2355 |
DestroyVirtualPinObject(aPinObject); |
|
2356 |
} |
|
2357 |
} |
|
2358 |
memory->Close(); |
|
2359 |
} |
|
2360 |
} |
|
2361 |
mapping->Close(); |
|
39
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2362 |
} |
0 | 2363 |
return r; |
2364 |
} |
|
2365 |
||
2366 |
void M::UnpinVirtualMemory(TVirtualPinObject* aPinObject) |
|
2367 |
{ |
|
2368 |
DVirtualPinMapping* mapping = (DVirtualPinMapping*)aPinObject; |
|
2369 |
if (mapping->IsAttached()) |
|
2370 |
mapping->Unpin(); |
|
2371 |
} |
|
2372 |
||
2373 |
void M::DestroyVirtualPinObject(TVirtualPinObject*& aPinObject) |
|
2374 |
{ |
|
2375 |
DVirtualPinMapping* mapping = (DVirtualPinMapping*)__e32_atomic_swp_ord_ptr(&aPinObject, 0); |
|
2376 |
if (mapping) |
|
2377 |
{ |
|
2378 |
if (mapping->IsAttached()) |
|
2379 |
mapping->Unpin(); |
|
2380 |
mapping->AsyncClose(); |
|
2381 |
} |
|
2382 |
} |
|
2383 |
||
39
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2384 |
// |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2385 |
// Physical pinning |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2386 |
// |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2387 |
|
0 | 2388 |
TInt M::CreatePhysicalPinObject(TPhysicalPinObject*& aPinObject) |
2389 |
{ |
|
2390 |
aPinObject = (TPhysicalPinObject*)new DPhysicalPinMapping; |
|
2391 |
return aPinObject != NULL ? KErrNone : KErrNoMemory; |
|
2392 |
} |
|
2393 |
||
2394 |
TInt M::PinPhysicalMemory(TPhysicalPinObject* aPinObject, TLinAddr aStart, TUint aSize, TBool aReadOnly, |
|
2395 |
TPhysAddr& aAddress, TPhysAddr* aPages, TUint32& aMapAttr, TUint& aColour, DThread* aThread) |
|
2396 |
{ |
|
39
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2397 |
__ASSERT_CRITICAL; |
0 | 2398 |
TUint offsetInMapping; |
2399 |
TUint mapInstanceCount; |
|
2400 |
DMemoryMapping* mapping = MM::FindMappingInThread( (DMemModelThread*)aThread, |
|
2401 |
aStart, |
|
2402 |
aSize, |
|
2403 |
offsetInMapping, |
|
2404 |
mapInstanceCount); |
|
2405 |
TInt r = KErrBadDescriptor; |
|
2406 |
if (mapping) |
|
2407 |
{ |
|
2408 |
TInt count = ((aStart & KPageMask) + aSize + KPageMask) >> KPageShift; |
|
2409 |
||
2410 |
MmuLock::Lock(); |
|
2411 |
DMemoryObject* memory = mapping->Memory(); |
|
2412 |
if (mapInstanceCount == mapping->MapInstanceCount() && memory) |
|
2413 |
{ |
|
2414 |
memory->Open(); |
|
2415 |
MmuLock::Unlock(); |
|
2416 |
||
2417 |
TUint startInMemory = (offsetInMapping >> KPageShift) + mapping->iStartIndex; |
|
2418 |
TMappingPermissions permissions = aReadOnly ? ESupervisorReadOnly : ESupervisorReadWrite; |
|
2419 |
r = ((DPhysicalPinMapping*)aPinObject)->Pin(memory, startInMemory, count, permissions); |
|
2420 |
if (r == KErrNone) |
|
2421 |
{ |
|
2422 |
r = ((DPhysicalPinMapping*)aPinObject)->PhysAddr(0, count, aAddress, aPages); |
|
2423 |
if (r>=KErrNone) |
|
2424 |
{ |
|
2425 |
r = KErrNone; //Do not report discontiguous memory in return value. |
|
2426 |
const TMappingAttributes2& mapAttr2 = |
|
2427 |
MM::LegacyMappingAttributes(memory->Attributes(), mapping->Permissions()); |
|
2428 |
*(TMappingAttributes2*)&aMapAttr = mapAttr2; |
|
2429 |
} |
|
2430 |
else |
|
2431 |
UnpinPhysicalMemory(aPinObject); |
|
2432 |
} |
|
2433 |
memory->Close(); |
|
2434 |
} |
|
2435 |
else // mapping has been reused or no memory... |
|
2436 |
{ |
|
2437 |
MmuLock::Unlock(); |
|
2438 |
} |
|
2439 |
mapping->Close(); |
|
2440 |
} |
|
2441 |
aColour = (aStart >>KPageShift) & KPageColourMask; |
|
2442 |
return r; |
|
2443 |
} |
|
2444 |
||
2445 |
void M::UnpinPhysicalMemory(TPhysicalPinObject* aPinObject) |
|
2446 |
{ |
|
2447 |
DPhysicalPinMapping* mapping = (DPhysicalPinMapping*)aPinObject; |
|
2448 |
if (mapping->IsAttached()) |
|
2449 |
mapping->Unpin(); |
|
2450 |
} |
|
2451 |
||
2452 |
void M::DestroyPhysicalPinObject(TPhysicalPinObject*& aPinObject) |
|
2453 |
{ |
|
2454 |
DPhysicalPinMapping* mapping = (DPhysicalPinMapping*)__e32_atomic_swp_ord_ptr(&aPinObject, 0); |
|
2455 |
if (mapping) |
|
2456 |
{ |
|
2457 |
if (mapping->IsAttached()) |
|
2458 |
mapping->Unpin(); |
|
2459 |
mapping->AsyncClose(); |
|
2460 |
} |
|
2461 |
} |
|
2462 |
||
2463 |
||
39
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2464 |
// |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2465 |
// Kernel map and pin. |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2466 |
// |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2467 |
|
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2468 |
TInt M::CreateKernelMapObject(TKernelMapObject*& aMapObject, TUint aMaxReserveSize) |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2469 |
{ |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2470 |
DKernelPinMapping* pinObject = new DKernelPinMapping(); |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2471 |
aMapObject = (TKernelMapObject*) pinObject; |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2472 |
if (pinObject == NULL) |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2473 |
{ |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2474 |
return KErrNoMemory; |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2475 |
} |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2476 |
// Ensure we reserve enough bytes for all possible alignments of the start and |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2477 |
// end of the region to map. |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2478 |
TUint reserveBytes = aMaxReserveSize? ((aMaxReserveSize + KPageMask) & ~KPageMask) + KPageSize : 0; |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2479 |
TInt r = pinObject->Construct(reserveBytes); |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2480 |
if (r != KErrNone) |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2481 |
{// Failed so delete the kernel mapping object. |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2482 |
pinObject->Close(); |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2483 |
aMapObject = NULL; |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2484 |
} |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2485 |
return r; |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2486 |
} |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2487 |
|
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2488 |
|
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2489 |
TInt M::MapAndPinMemory(TKernelMapObject* aMapObject, DThread* aThread, TLinAddr aStart, |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2490 |
TUint aSize, TUint aMapAttributes, TLinAddr& aKernelAddr, TPhysAddr* aPages) |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2491 |
{ |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2492 |
__ASSERT_CRITICAL; |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2493 |
TUint offsetInMapping; |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2494 |
TUint mapInstanceCount; |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2495 |
DMemoryMapping* mapping = MM::FindMappingInThread( (DMemModelThread*)aThread, |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2496 |
aStart, |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2497 |
aSize, |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2498 |
offsetInMapping, |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2499 |
mapInstanceCount); |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2500 |
TInt r = KErrBadDescriptor; |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2501 |
if (mapping) |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2502 |
{ |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2503 |
DKernelPinMapping* kernelMap = (DKernelPinMapping*)aMapObject; |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2504 |
TInt count = (((aStart + aSize + KPageMask) & ~KPageMask) - (aStart & ~KPageMask)) >> KPageShift; |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2505 |
if (kernelMap->iReservePages && kernelMap->iReservePages < count) |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2506 |
{ |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2507 |
mapping->Close(); |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2508 |
return KErrArgument; |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2509 |
} |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2510 |
|
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2511 |
MmuLock::Lock(); |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2512 |
DMemoryObject* memory = mapping->Memory(); |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2513 |
if (mapInstanceCount == mapping->MapInstanceCount() && memory) |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2514 |
{ |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2515 |
memory->Open(); |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2516 |
MmuLock::Unlock(); |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2517 |
|
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2518 |
TUint startInMemory = (offsetInMapping >> KPageShift) + mapping->iStartIndex; |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2519 |
TBool readOnly = aMapAttributes & Kern::EKernelMap_ReadOnly; |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2520 |
TMappingPermissions permissions = readOnly ? ESupervisorReadOnly : ESupervisorReadWrite; |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2521 |
r = kernelMap->MapAndPin(memory, startInMemory, count, permissions); |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2522 |
if (r == KErrNone) |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2523 |
{ |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2524 |
__NK_ASSERT_DEBUG(!kernelMap->IsUserMapping()); |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2525 |
aKernelAddr = kernelMap->Base(); |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2526 |
TPhysAddr contigAddr; // Ignore this value as aPages will be populated |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2527 |
// whether the memory is contiguous or not. |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2528 |
r = kernelMap->PhysAddr(0, count, contigAddr, aPages); |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2529 |
if (r>=KErrNone) |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2530 |
{ |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2531 |
r = KErrNone; //Do not report discontiguous memory in return value. |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2532 |
} |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2533 |
else |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2534 |
{ |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2535 |
UnmapAndUnpinMemory((TKernelMapObject*)kernelMap); |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2536 |
} |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2537 |
} |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2538 |
memory->Close(); |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2539 |
} |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2540 |
else // mapping has been reused or no memory... |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2541 |
{ |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2542 |
MmuLock::Unlock(); |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2543 |
} |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2544 |
mapping->Close(); |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2545 |
} |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2546 |
return r; |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2547 |
} |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2548 |
|
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2549 |
|
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2550 |
void M::UnmapAndUnpinMemory(TKernelMapObject* aMapObject) |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2551 |
{ |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2552 |
DKernelPinMapping* mapping = (DKernelPinMapping*)aMapObject; |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2553 |
if (mapping->IsAttached()) |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2554 |
mapping->UnmapAndUnpin(); |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2555 |
} |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2556 |
|
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2557 |
|
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2558 |
void M::DestroyKernelMapObject(TKernelMapObject*& aMapObject) |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2559 |
{ |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2560 |
DKernelPinMapping* mapping = (DKernelPinMapping*)__e32_atomic_swp_ord_ptr(&aMapObject, 0); |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2561 |
if (mapping) |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2562 |
{ |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2563 |
if (mapping->IsAttached()) |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2564 |
mapping->UnmapAndUnpin(); |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2565 |
mapping->AsyncClose(); |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2566 |
} |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2567 |
} |
5d2844f35677
Revision: 201004
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
36
diff
changeset
|
2568 |
|
0 | 2569 |
|
2570 |
// |
|
2571 |
// Cache sync operations |
|
2572 |
// |
|
2573 |
||
2574 |
//@pre As for MASK_THREAD_STANDARD |
|
2575 |
void Mmu::SyncPhysicalMemoryBeforeDmaWrite(TPhysAddr* aPages, TUint aColour, TUint aOffset, TUint aSize, TUint32 aMapAttr) |
|
2576 |
{ |
|
2577 |
//Jump over the pages we do not have to sync |
|
2578 |
aPages += aOffset>>KPageShift; |
|
2579 |
aOffset &=KPageMask; |
|
2580 |
aColour = (aColour + (aOffset>>KPageShift)) & KPageColourMask; |
|
2581 |
||
2582 |
//Calculate page table entry for the temporary mapping. |
|
2583 |
TUint pteType = PteType(ESupervisorReadWrite,true); |
|
2584 |
TMappingAttributes2 mapAttr2(aMapAttr); |
|
2585 |
TPte pte = Mmu::BlankPte((TMemoryAttributes)mapAttr2.Type(), pteType); |
|
2586 |
||
2587 |
while (aSize) //A single pass of loop operates within page boundaries. |
|
2588 |
{ |
|
2589 |
TUint sizeInLoopPass = Min (KPageSize, aOffset+aSize) - aOffset; //The size of the region in this pass. |
|
2590 |
||
2591 |
NKern::ThreadEnterCS(); |
|
2592 |
Kern::MutexWait(*iPhysMemSyncMutex); |
|
2593 |
||
2594 |
TLinAddr linAddr = iPhysMemSyncTemp.Map(*aPages, aColour, pte); |
|
2595 |
CacheMaintenance::MakeCPUChangesVisible(linAddr+aOffset, sizeInLoopPass, aMapAttr, *aPages+aOffset); |
|
2596 |
iPhysMemSyncTemp.Unmap(); |
|
2597 |
||
2598 |
Kern::MutexSignal(*iPhysMemSyncMutex); |
|
2599 |
NKern::ThreadLeaveCS(); |
|
2600 |
||
2601 |
aSize-=sizeInLoopPass; // Remaining bytes to sync |
|
2602 |
aOffset=0; // In all the pages after the first, sync will always start with zero offset. |
|
2603 |
aPages++; // Point to the next page |
|
2604 |
aColour = (aColour+1) & KPageColourMask; |
|
2605 |
} |
|
2606 |
} |
|
2607 |
||
2608 |
//@pre As for MASK_THREAD_STANDARD |
|
2609 |
void Mmu::SyncPhysicalMemoryBeforeDmaRead(TPhysAddr* aPages, TUint aColour, TUint aOffset, TUint aSize, TUint32 aMapAttr) |
|
2610 |
{ |
|
2611 |
//Jump over the pages we do not have to sync |
|
2612 |
aPages += aOffset>>KPageShift; |
|
2613 |
aOffset &=KPageMask; |
|
2614 |
aColour = (aColour + (aOffset>>KPageShift)) & KPageColourMask; |
|
2615 |
||
2616 |
//Calculate page table entry for the temporary mapping. |
|
2617 |
TUint pteType = PteType(ESupervisorReadWrite,true); |
|
2618 |
TMappingAttributes2 mapAttr2(aMapAttr); |
|
2619 |
TPte pte = Mmu::BlankPte((TMemoryAttributes)mapAttr2.Type(), pteType); |
|
2620 |
||
2621 |
while (aSize) //A single pass of loop operates within page boundaries. |
|
2622 |
{ |
|
2623 |
TUint sizeInLoopPass = Min (KPageSize, aOffset+aSize) - aOffset; //The size of the region in this pass. |
|
2624 |
||
2625 |
NKern::ThreadEnterCS(); |
|
2626 |
Kern::MutexWait(*iPhysMemSyncMutex); |
|
2627 |
||
2628 |
TLinAddr linAddr = iPhysMemSyncTemp.Map(*aPages, aColour, pte); |
|
2629 |
CacheMaintenance::PrepareMemoryForExternalWrites(linAddr+aOffset, sizeInLoopPass, aMapAttr, *aPages+aOffset); |
|
2630 |
iPhysMemSyncTemp.Unmap(); |
|
2631 |
||
2632 |
Kern::MutexSignal(*iPhysMemSyncMutex); |
|
2633 |
NKern::ThreadLeaveCS(); |
|
2634 |
||
2635 |
aSize-=sizeInLoopPass; // Remaining bytes to sync |
|
2636 |
aOffset=0; // In all the pages after the first, sync will always start with zero offset. |
|
2637 |
aPages++; // Point to the next page |
|
2638 |
aColour = (aColour+1) & KPageColourMask; |
|
2639 |
} |
|
2640 |
} |
|
2641 |
||
2642 |
//@pre As for MASK_THREAD_STANDARD |
|
2643 |
void Mmu::SyncPhysicalMemoryAfterDmaRead(TPhysAddr* aPages, TUint aColour, TUint aOffset, TUint aSize, TUint32 aMapAttr) |
|
2644 |
{ |
|
2645 |
//Jump over the pages we do not have to sync |
|
2646 |
aPages += aOffset>>KPageShift; |
|
2647 |
aOffset &=KPageMask; |
|
2648 |
aColour = (aColour + (aOffset>>KPageShift)) & KPageColourMask; |
|
2649 |
||
2650 |
//Calculate page table entry for the temporary mapping. |
|
2651 |
TUint pteType = PteType(ESupervisorReadWrite,true); |
|
2652 |
TMappingAttributes2 mapAttr2(aMapAttr); |
|
2653 |
TPte pte = Mmu::BlankPte((TMemoryAttributes)mapAttr2.Type(), pteType); |
|
2654 |
||
2655 |
while (aSize) //A single pass of loop operates within page boundaries. |
|
2656 |
{ |
|
2657 |
TUint sizeInLoopPass = Min (KPageSize, aOffset+aSize) - aOffset; //The size of the region in this pass. |
|
2658 |
||
2659 |
NKern::ThreadEnterCS(); |
|
2660 |
Kern::MutexWait(*iPhysMemSyncMutex); |
|
2661 |
||
2662 |
TLinAddr linAddr = iPhysMemSyncTemp.Map(*aPages, aColour, pte); |
|
2663 |
CacheMaintenance::MakeExternalChangesVisible(linAddr+aOffset, sizeInLoopPass, aMapAttr, *aPages+aOffset); |
|
2664 |
iPhysMemSyncTemp.Unmap(); |
|
2665 |
||
2666 |
Kern::MutexSignal(*iPhysMemSyncMutex); |
|
2667 |
NKern::ThreadLeaveCS(); |
|
2668 |
||
2669 |
aSize-=sizeInLoopPass; // Remaining bytes to sync |
|
2670 |
aOffset=0; // In all the pages after the first, sync will always start with zero offset. |
|
2671 |
aPages++; // Point to the next page |
|
2672 |
aColour = (aColour+1) & KPageColourMask; |
|
2673 |
} |
|
2674 |
} |
|
2675 |
||
2676 |
EXPORT_C TInt Cache::SyncPhysicalMemoryBeforeDmaWrite(TPhysAddr* aPages, TUint aColour, TUint aOffset, TUint aSize, TUint32 aMapAttr) |
|
2677 |
{ |
|
2678 |
CHECK_PRECONDITIONS(MASK_THREAD_STANDARD,"Cache::SyncPhysicalMemoryBeforeDmaWrite"); |
|
2679 |
TheMmu.SyncPhysicalMemoryBeforeDmaWrite(aPages, aColour, aOffset, aSize, aMapAttr); |
|
2680 |
return KErrNone; |
|
2681 |
} |
|
2682 |
||
2683 |
EXPORT_C TInt Cache::SyncPhysicalMemoryBeforeDmaRead(TPhysAddr* aPages, TUint aColour, TUint aOffset, TUint aSize, TUint32 aMapAttr) |
|
2684 |
{ |
|
2685 |
CHECK_PRECONDITIONS(MASK_THREAD_STANDARD,"Cache::SyncPhysicalMemoryBeforeDmaRead"); |
|
2686 |
TheMmu.SyncPhysicalMemoryBeforeDmaRead(aPages, aColour, aOffset, aSize, aMapAttr); |
|
2687 |
return KErrNone; |
|
2688 |
} |
|
2689 |
||
2690 |
EXPORT_C TInt Cache::SyncPhysicalMemoryAfterDmaRead(TPhysAddr* aPages, TUint aColour, TUint aOffset, TUint aSize, TUint32 aMapAttr) |
|
2691 |
{ |
|
2692 |
CHECK_PRECONDITIONS(MASK_THREAD_STANDARD,"Cache::SyncPhysicalMemoryAfterDmaRead"); |
|
2693 |
TheMmu.SyncPhysicalMemoryAfterDmaRead(aPages, aColour, aOffset, aSize, aMapAttr); |
|
2694 |
return KErrNone; |
|
2695 |
} |