// Copyright (c) 1997-2009 Nokia Corporation and/or its subsidiary(-ies).

// All rights reserved.

// This component and the accompanying materials are made available

// under the terms of the License "Eclipse Public License v1.0"

// which accompanies this distribution, and is available

// at the URL "http://www.eclipse.org/legal/epl-v10.html".

//

// Initial Contributors:

// Nokia Corporation - initial contribution.

//

// Contributors:

//

// Description:

// e32\memmodel\epoc\multiple\arm\xmmu.cpp

// 

//

#include "arm_mem.h"

#include <mmubase.inl>

#include <ramcache.h>

#include <demand_paging.h>

#include "execs.h"

#include <defrag.h>

#include "cache_maintenance.inl"

#undef __MMU_MACHINE_CODED__

// SECTION_PDE(perm, attr, domain, execute, global)

// PT_PDE(domain)

// LP_PTE(perm, attr, execute, global)

// SP_PTE(perm, attr, execute, global)

const TInt KPageColourShift=2;

const TInt KPageColourCount=(1<<KPageColourShift);

const TInt KPageColourMask=KPageColourCount-1;

const TPde KPdPdePerm=PT_PDE(0);

const TPde KPtPdePerm=PT_PDE(0);

const TPde KShadowPdePerm=PT_PDE(0);

#if defined(__CPU_MEMORY_TYPE_REMAPPING)

// ARM1176, ARM11MPCore, ARMv7 and later

// __CPU_MEMORY_TYPE_REMAPPING means that only three bits (TEX0:C:B) in page table define

// memory attributes. Kernel runs with a limited set of memory types: stronlgy ordered,

// device, normal un-cached & and normal WBWA. Due to lack of write through mode, page tables are

// write-back which means that cache has to be cleaned on every page/directory table update.

const TPte KPdPtePerm=				SP_PTE(KArmV6PermRWNO, EMemAttNormalCached, 0, 1);

const TPte KPtPtePerm=				SP_PTE(KArmV6PermRWNO, EMemAttNormalCached, 0, 1);

const TPte KPtInfoPtePerm=			SP_PTE(KArmV6PermRWNO, EMemAttNormalCached, 0, 1);

const TPte KRomPtePerm=				SP_PTE(KArmV6PermRORO, EMemAttNormalCached, 1, 1);

const TPte KShadowPtePerm=			SP_PTE(KArmV6PermRORO, EMemAttNormalCached, 1, 1);

const TPde KRomSectionPermissions=	SECTION_PDE(KArmV6PermRORO, EMemAttNormalCached, 0, 1, 1);

const TPte KUserCodeLoadPte=		SP_PTE(KArmV6PermRWNO, EMemAttNormalCached, 1, 0);

const TPte KUserCodeRunPte=			SP_PTE(KArmV6PermRORO, EMemAttNormalCached, 1, 0);

const TPte KGlobalCodeRunPte=		SP_PTE(KArmV6PermRORO, EMemAttNormalCached, 1, 1);

const TPte KKernelCodeRunPte=		SP_PTE(KArmV6PermRONO, EMemAttNormalCached, 1, 1);

const TInt KNormalUncachedAttr = EMemAttNormalUncached;

const TInt KNormalCachedAttr = EMemAttNormalCached;

#else

//ARM1136 

const TPte KPtInfoPtePerm=SP_PTE(KArmV6PermRWNO, KArmV6MemAttWBWAWBWA, 0, 1);

#if defined (__CPU_WriteThroughDisabled)

const TPte KPdPtePerm=SP_PTE(KArmV6PermRWNO, KArmV6MemAttWBWAWBWA, 0, 1);

const TPte KPtPtePerm=SP_PTE(KArmV6PermRWNO, KArmV6MemAttWBWAWBWA, 0, 1);

const TPte KRomPtePerm=SP_PTE(KArmV6PermRORO, KArmV6MemAttWBWAWBWA, 1, 1);

const TPte KShadowPtePerm=SP_PTE(KArmV6PermRWRO, KArmV6MemAttWBWAWBWA, 1, 1);

const TPde KRomSectionPermissions	=	SECTION_PDE(KArmV6PermRORO, KArmV6MemAttWBWAWBWA, 0, 1, 1);

const TPte KUserCodeLoadPte=SP_PTE(KArmV6PermRWNO, KArmV6MemAttWBWAWBWA, 1, 0);

const TPte KUserCodeRunPte=SP_PTE(KArmV6PermRWRO, KArmV6MemAttWBWAWBWA, 1, 0);

const TPte KGlobalCodeRunPte=SP_PTE(KArmV6PermRWRO, KArmV6MemAttWBWAWBWA, 1, 1);

const TInt KKernelCodeRunPteAttr = KArmV6MemAttWBWAWBWA;

#else

const TPte KPdPtePerm=SP_PTE(KArmV6PermRWNO, KArmV6MemAttWBRAWTRA, 0, 1);

const TPte KPtPtePerm=SP_PTE(KArmV6PermRWNO, KArmV6MemAttWBRAWTRA, 0, 1);

const TPte KRomPtePerm=SP_PTE(KArmV6PermRORO, KArmV6MemAttWTRAWTRA, 1, 1);

const TPte KShadowPtePerm=SP_PTE(KArmV6PermRWRO, KArmV6MemAttWTRAWTRA, 1, 1);

const TPde KRomSectionPermissions	=	SECTION_PDE(KArmV6PermRORO, KArmV6MemAttWTRAWTRA, 0, 1, 1);

const TPte KUserCodeLoadPte=SP_PTE(KArmV6PermRWNO, KArmV6MemAttWTRAWTRA, 1, 0);

const TPte KUserCodeRunPte=SP_PTE(KArmV6PermRWRO, KArmV6MemAttWTRAWTRA, 1, 0);

const TPte KGlobalCodeRunPte=SP_PTE(KArmV6PermRWRO, KArmV6MemAttWTRAWTRA, 1, 1);

const TInt KKernelCodeRunPteAttr = KArmV6MemAttWTRAWTRA;

#endif

#if defined(__CPU_ARM1136_ERRATUM_353494_FIXED)

const TInt KKernelCodeRunPtePerm = KArmV6PermRONO;

#else

const TInt KKernelCodeRunPtePerm = KArmV6PermRORO;

#endif

const TPte KKernelCodeRunPte=SP_PTE(KKernelCodeRunPtePerm, KKernelCodeRunPteAttr, 1, 1);

const TInt KNormalUncachedAttr = KArmV6MemAttNCNC;

const TInt KNormalCachedAttr = KArmV6MemAttWBWAWBWA;

#endif

extern void __FlushBtb();

#if defined(__CPU_ARM1136__) && !defined(__CPU_ARM1136_ERRATUM_353494_FIXED)

extern void remove_and_invalidate_page(TPte* aPte, TLinAddr aAddr, TInt aAsid);

extern void remove_and_invalidate_section(TPde* aPde, TLinAddr aAddr, TInt aAsid);

#endif

LOCAL_D const TPte ChunkPtePermissions[ENumChunkTypes] =

	{

#if defined(__CPU_MEMORY_TYPE_REMAPPING)

// ARM1176, ARM11 mcore, ARMv7 and later

	SP_PTE(KArmV6PermRWNO, EMemAttNormalCached, 0, 1),		// EKernelData

	SP_PTE(KArmV6PermRWNO, EMemAttNormalCached, 0, 1),		// EKernelStack

	SP_PTE(KArmV6PermRWNO, EMemAttNormalCached, 1, 1),		// EKernelCode - loading

	SP_PTE(KArmV6PermRWNO, EMemAttNormalCached, 1, 1),		// EDll (used for global code) - loading

	SP_PTE(KArmV6PermRORO, EMemAttNormalCached, 1, 0),		// EUserCode - run

	SP_PTE(KArmV6PermRWRW, EMemAttNormalCached, 0, 1),		// ERamDrive

	SP_PTE(KArmV6PermRWRW, EMemAttNormalCached, 0, 0),		// EUserData

	SP_PTE(KArmV6PermRWRW, EMemAttNormalCached, 0, 0),		// EDllData

	SP_PTE(KArmV6PermRWRW, EMemAttNormalCached, 1, 0),		// EUserSelfModCode

	SP_PTE(KArmV6PermRWRW, EMemAttNormalCached, 0, 0),		// ESharedKernelSingle

	SP_PTE(KArmV6PermRWRW, EMemAttNormalCached, 0, 0),		// ESharedKernelMultiple

	SP_PTE(KArmV6PermRWRW, EMemAttNormalCached, 0, 0),		// ESharedIo

	SP_PTE(KArmV6PermRWNO, EMemAttNormalCached, 0, 1),		// ESharedKernelMirror

	SP_PTE(KArmV6PermRWNO, EMemAttNormalCached, 0, 1),		// EKernelMessage

#else

	SP_PTE(KArmV6PermRWNO, KArmV6MemAttWBWAWBWA, 0, 1),		// EKernelData

	SP_PTE(KArmV6PermRWNO, KArmV6MemAttWBWAWBWA, 0, 1),		// EKernelStack

#if defined (__CPU_WriteThroughDisabled)

	SP_PTE(KArmV6PermRWNO, KArmV6MemAttWBWAWBWA, 1, 1),		// EKernelCode - loading

	SP_PTE(KArmV6PermRWNO, KArmV6MemAttWBWAWBWA, 1, 1),		// EDll (used for global code) - loading

	SP_PTE(KArmV6PermRWRO, KArmV6MemAttWBWAWBWA, 1, 0),		// EUserCode - run

#else

	SP_PTE(KArmV6PermRWNO, KArmV6MemAttWTRAWTRA, 1, 1),		// EKernelCode - loading

	SP_PTE(KArmV6PermRWNO, KArmV6MemAttWTRAWTRA, 1, 1),		// EDll (used for global code) - loading

	SP_PTE(KArmV6PermRWRO, KArmV6MemAttWTRAWTRA, 1, 0),		// EUserCode - run

#endif

	SP_PTE(KArmV6PermRWRW, KArmV6MemAttWBWAWBWA, 0, 1),		// ERamDrive

	SP_PTE(KArmV6PermRWRW, KArmV6MemAttWBWAWBWA, 0, 0),		// EUserData

	SP_PTE(KArmV6PermRWRW, KArmV6MemAttWBWAWBWA, 0, 0),		// EDllData

	SP_PTE(KArmV6PermRWRW, KArmV6MemAttWBWAWBWA, 1, 0),		// EUserSelfModCode

	SP_PTE(KArmV6PermRWRW, KArmV6MemAttWBWAWBWA, 0, 0),		// ESharedKernelSingle

	SP_PTE(KArmV6PermRWRW, KArmV6MemAttWBWAWBWA, 0, 0),		// ESharedKernelMultiple

	SP_PTE(KArmV6PermRWRW, KArmV6MemAttWBWAWBWA, 0, 0),		// ESharedIo

	SP_PTE(KArmV6PermRWNO, KArmV6MemAttWBWAWBWA, 0, 1),		// ESharedKernelMirror

	SP_PTE(KArmV6PermRWNO, KArmV6MemAttWBWAWBWA, 0, 1),		// EKernelMessage

#endif

	};

// The domain for each chunk is selected according to its type.

// The RamDrive lives in a separate domain, to minimise the risk

// of accidental access and corruption. User chunks may also be

// located in a separate domain (15) in DEBUG builds.

LOCAL_D const TPde ChunkPdePermissions[ENumChunkTypes] =

	{

	PT_PDE(0),						// EKernelData

	PT_PDE(0),						// EKernelStack

	PT_PDE(0),						// EKernelCode

	PT_PDE(0),						// EDll

	PT_PDE(USER_MEMORY_DOMAIN),		// EUserCode

	PT_PDE(1),						// ERamDrive

	PT_PDE(USER_MEMORY_DOMAIN),		// EUserData

	PT_PDE(USER_MEMORY_DOMAIN),		// EDllData

	PT_PDE(USER_MEMORY_DOMAIN),		// EUserSelfModCode

	PT_PDE(USER_MEMORY_DOMAIN),		// ESharedKernelSingle

	PT_PDE(USER_MEMORY_DOMAIN),		// ESharedKernelMultiple

	PT_PDE(0),						// ESharedIo

	PT_PDE(0),						// ESharedKernelMirror

	PT_PDE(0),						// EKernelMessage

	};

// Inline functions for simple transformations

inline TLinAddr PageTableLinAddr(TInt aId)

	{

	return (KPageTableBase+(aId<<KPageTableShift));

	}

inline TPte* PageTable(TInt aId)

	{

	return (TPte*)(KPageTableBase+(aId<<KPageTableShift));

	}

inline TPte* PageTableEntry(TInt aId, TLinAddr aAddress)

	{

	return PageTable(aId) + ((aAddress >> KPageShift) & (KChunkMask >> KPageShift));

	}

inline TLinAddr PageDirectoryLinAddr(TInt aOsAsid)

	{

	return (KPageDirectoryBase+(aOsAsid<<KPageDirectoryShift));

	}

inline TPde* PageDirectoryEntry(TInt aOsAsid, TLinAddr aAddress)

	{

	return PageDirectory(aOsAsid) + (aAddress >> KChunkShift);

	}

extern void InvalidateTLBForPage(TLinAddr /*aLinAddr*/, TInt /*aAsid*/);

extern void FlushTLBs();

extern TUint32 TTCR();

TPte* SafePageTableFromPde(TPde aPde)

	{

	if((aPde&KPdeTypeMask)==KArmV6PdePageTable)

		{

		SPageInfo* pi = SPageInfo::SafeFromPhysAddr(aPde);

		if(pi)

			{

			TInt id = (pi->Offset()<<KPtClusterShift) | ((aPde>>KPageTableShift)&KPtClusterMask);

			return PageTable(id);

			}

		}

	return 0;

	}

TPte* SafePtePtrFromLinAddr(TLinAddr aAddress, TInt aOsAsid=0)

	{

	if ((TInt)(aAddress>>KChunkShift)>=(TheMmu.iLocalPdSize>>2))

		aOsAsid = 0;

	TPde pde = PageDirectory(aOsAsid)[aAddress>>KChunkShift];

	TPte* pt = SafePageTableFromPde(pde);

	if(pt)

		pt += (aAddress>>KPageShift)&(KChunkMask>>KPageShift);

	return pt;

	}

#ifndef _DEBUG

// inline in UREL builds...

#ifdef __ARMCC__

	__forceinline /* RVCT ignores normal inline qualifier :-( */

#else

	inline

#endif

#endif

TPte* PtePtrFromLinAddr(TLinAddr aAddress, TInt aOsAsid=0)

	{

	// this function only works for process local memory addresses, or for kernel memory (asid==0).

	__NK_ASSERT_DEBUG(aOsAsid==0 || (TInt)(aAddress>>KChunkShift)<(TheMmu.iLocalPdSize>>2));

	TPde pde = PageDirectory(aOsAsid)[aAddress>>KChunkShift];

	SPageInfo* pi = SPageInfo::FromPhysAddr(pde);

	TInt id = (pi->Offset()<<KPtClusterShift) | ((pde>>KPageTableShift)&KPtClusterMask);

	TPte* pt = PageTable(id);

	pt += (aAddress>>KPageShift)&(KChunkMask>>KPageShift);

	return pt;

	}

TInt ArmMmu::LinearToPhysical(TLinAddr aLinAddr, TInt aSize, TPhysAddr& aPhysicalAddress, TPhysAddr* aPhysicalPageList, TInt aOsAsid)

	{

	__KTRACE_OPT(KMMU,Kern::Printf("ArmMmu::LinearToPhysical %08x+%08x, asid=%d",aLinAddr,aSize,aOsAsid));

	TPhysAddr physStart = ArmMmu::LinearToPhysical(aLinAddr,aOsAsid);

	TPhysAddr nextPhys = physStart&~KPageMask;

	TUint32* pageList = aPhysicalPageList;

	TInt pageIndex = aLinAddr>>KPageShift;

	TInt pagesLeft = ((aLinAddr+aSize-1)>>KPageShift)+1 - pageIndex;

	TInt pdeIndex = aLinAddr>>KChunkShift;

	TPde* pdePtr = (pdeIndex<(iLocalPdSize>>2) || (iAsidInfo[aOsAsid]&1))

					? PageDirectory(aOsAsid)

					: ::InitPageDirectory;

	pdePtr += pdeIndex;

	while(pagesLeft)

		{

		pageIndex &= KChunkMask>>KPageShift;

		TInt pagesLeftInChunk = (1<<(KChunkShift-KPageShift))-pageIndex;

		if(pagesLeftInChunk>pagesLeft)

			pagesLeftInChunk = pagesLeft;

		pagesLeft -= pagesLeftInChunk;

		TPhysAddr phys;

		TPde pde = *pdePtr++;

		TUint pdeType = pde&KPdeTypeMask;

		if(pdeType==KArmV6PdeSection)

			{

			phys = (pde & KPdeSectionAddrMask) + (pageIndex*KPageSize);

			__KTRACE_OPT(KMMU2,Kern::Printf("ArmMmu::LinearToPhysical Section phys=%8x",phys));

			TInt n=pagesLeftInChunk;

			phys==nextPhys ? nextPhys+=n*KPageSize : nextPhys=KPhysAddrInvalid;

			if(pageList)

				{

				TUint32* pageEnd = pageList+n;

				do

					{

					*pageList++ = phys;

					phys+=KPageSize;

					}

				while(pageList<pageEnd);

				}

			}

		else

			{

			TPte* pt = SafePageTableFromPde(pde);

			if(!pt)

				{

				__KTRACE_OPT(KMMU,Kern::Printf("ArmMmu::LinearToPhysical missing page table: PDE=%8x",pde));

				return KErrNotFound;

				}

			pt += pageIndex;

			for(;;)

				{

				TPte pte = *pt++;

				TUint pte_type = pte & KPteTypeMask;

				if (pte_type >= KArmV6PteSmallPage)

					{

					phys = (pte & KPteSmallPageAddrMask);

					__KTRACE_OPT(KMMU2,Kern::Printf("ArmMmu::LinearToPhysical Small Page phys=%8x",phys));

					phys==nextPhys ? nextPhys+=KPageSize : nextPhys=KPhysAddrInvalid;

					if(pageList)

						*pageList++ = phys;

					if(--pagesLeftInChunk)

						continue;

					break;

					}

				if (pte_type == KArmV6PteLargePage)

					{

					--pt; // back up ptr

					TUint pageOffset = ((TUint)pt>>2)&(KLargeSmallPageRatio-1);

					phys = (pte & KPteLargePageAddrMask) + pageOffset*KPageSize;

					__KTRACE_OPT(KMMU2,Kern::Printf("ArmMmu::LinearToPhysical Large Page phys=%8x",phys));

					TInt n=KLargeSmallPageRatio-pageOffset;

					if(n>pagesLeftInChunk)

						n = pagesLeftInChunk;

					phys==nextPhys ? nextPhys+=n*KPageSize : nextPhys=KPhysAddrInvalid;

					if(pageList)

						{

						TUint32* pageEnd = pageList+n;

						do

							{

							*pageList++ = phys;

							phys+=KPageSize;

							}

						while(pageList<pageEnd);

						}

					pt += n;

					if(pagesLeftInChunk-=n)

						continue;

					break;

					}

				__KTRACE_OPT(KMMU,Kern::Printf("ArmMmu::LinearToPhysical bad PTE %8x",pte));

				return KErrNotFound;

				}

			}

		if(!pageList && nextPhys==KPhysAddrInvalid)

			{

			__KTRACE_OPT(KMMU,Kern::Printf("ArmMmu::LinearToPhysical not contiguous"));

			return KErrNotFound;

			}

		pageIndex = 0;

		}

	if(nextPhys==KPhysAddrInvalid)

		{

		// Memory is discontiguous...

		aPhysicalAddress = KPhysAddrInvalid;

		return 1;

		}

	else

		{

		// Memory is contiguous...

		aPhysicalAddress = physStart;

		return KErrNone;

		}

	}

TInt ArmMmu::PreparePagesForDMA(TLinAddr aLinAddr, TInt aSize, TInt aOsAsid, TPhysAddr* aPhysicalPageList)

//Returns the list of physical pages belonging to the specified memory space.

//Checks these pages belong to a chunk marked as being trusted. 

//Locks these pages so they can not be moved by e.g. ram defragmentation.

	{

	SPageInfo* pi = NULL;

	DChunk* chunk = NULL;

	TInt err = KErrNone;

	__NK_ASSERT_DEBUG(MM::MaxPagesInOneGo == 32);	// Needs to be a power of 2.

	TUint flashMask = MM::MaxPagesInOneGo - 1;

	__KTRACE_OPT(KMMU2,Kern::Printf("ArmMmu::PreparePagesForDMA %08x+%08x, asid=%d",aLinAddr,aSize,aOsAsid));

	TUint32* pageList = aPhysicalPageList;

	TInt pagesInList = 0;				//The number of pages we put in the list so far

	TInt pageIndex = (aLinAddr & KChunkMask) >> KPageShift;	// Index of the page within the section

	TInt pagesLeft = ((aLinAddr & KPageMask) + aSize + KPageMask) >> KPageShift;

	TInt pdeIndex = aLinAddr>>KChunkShift;

	MmuBase::Wait(); 	// RamAlloc Mutex for accessing page/directory tables.

	NKern::LockSystem();// SystemlLock for accessing SPageInfo objects.

	// Get the page directory entry that maps aLinAddr.

	// If the address is in the global region check whether this asid maps

	// global pdes (i.e. the LSB of iAsidInfo is set), if not find the pde from 

	// the kernel's initial page directory.

	TPde* pdePtr = (pdeIndex<(iLocalPdSize>>2) || (iAsidInfo[aOsAsid]&1)) ? PageDirectory(aOsAsid) : ::InitPageDirectory;

	pdePtr += pdeIndex;//This points to the first pde 

	while(pagesLeft)

		{

		TInt pagesLeftInChunk = (1<<(KChunkShift-KPageShift))-pageIndex;

		if(pagesLeftInChunk>pagesLeft)

			pagesLeftInChunk = pagesLeft;

		pagesLeft -= pagesLeftInChunk;

		TPte* pPte = SafePageTableFromPde(*pdePtr++);

		if(!pPte) 

			{// Cannot get page table. 

			err = KErrNotFound; 

			goto fail; 

			}

		pPte += pageIndex;

		for(;pagesLeftInChunk--;)

			{// This pte must be of type ArmV6 small page, the pde type will 

			// have already been checked by SafePageTableFromPde().

			__NK_ASSERT_DEBUG((*pPte & KArmV6PteTypeMask) >= KArmV6PteSmallPage);

			TPhysAddr phys = (*pPte++ & KPteSmallPageAddrMask);

			pi =  SPageInfo::SafeFromPhysAddr(phys);

			if(!pi)	

				{// Invalid address

				err = KErrNotFound; 

				goto fail; 

				}

			__KTRACE_OPT(KMMU2,Kern::Printf("PageInfo: PA:%x T:%x S:%x O:%x C:%x",phys, pi->Type(), pi->State(), pi->Owner(), pi->LockCount()));

			if (chunk == NULL)

				{//This is the first page. Check 'trusted' bit.

				if (pi->Type()!= SPageInfo::EChunk)

					{// The first page does not belong to a chunk.

					err = KErrAccessDenied;

					goto fail;

					}

				chunk = (DChunk*)pi->Owner();

				if ((chunk == NULL) || ((chunk->iAttributes & DChunk::ETrustedChunk) == 0))

					{// Not a trusted chunk

					err = KErrAccessDenied;

					goto fail;

					}

				}

			pi->Lock();

			*pageList++ = phys;

			if(!(++pagesInList & flashMask))

				{

				NKern::FlashSystem();

				}

			}

		pageIndex = 0;

		}

	if (pi->Type() != SPageInfo::EChunk)

		{// The last page does not belong to a chunk.

		err = KErrAccessDenied;

		goto fail;

		}

	if (chunk && (chunk != (DChunk*)pi->Owner()))

		{//The first & the last page do not belong to the same chunk.

		err = KErrArgument;

		goto fail;

		}

	NKern::UnlockSystem();

	MmuBase::Signal();

	return KErrNone;

fail:

	__KTRACE_OPT(KMMU2,Kern::Printf("ArmMmu::PreparePagesForDMA failed"));

	NKern::UnlockSystem();

	MmuBase::Signal();

	ReleasePagesFromDMA(aPhysicalPageList, pagesInList);

	return err;

	}

TInt ArmMmu::ReleasePagesFromDMA(TPhysAddr* aPhysicalPageList, TInt aPageCount)

// Unlocks physical pages.

// @param aPhysicalPageList - points to the list of physical pages that should be released.

// @param aPageCount		- the number of physical pages in the list.

	{

	NKern::LockSystem();

	__KTRACE_OPT(KMMU2,Kern::Printf("ArmMmu::ReleasePagesFromDMA count:%d",aPageCount));

	TUint flashMask = MM::MaxPagesInOneGo - 1;

	while (aPageCount--)

		{

		SPageInfo* pi =  SPageInfo::SafeFromPhysAddr(*aPhysicalPageList++);

		if(!pi)

			{

			NKern::UnlockSystem();

			return KErrArgument;

			}

		__KTRACE_OPT(KMMU2,Kern::Printf("PageInfo: T:%x S:%x O:%x C:%x",pi->Type(), pi->State(), pi->Owner(), pi->LockCount()));

		pi->Unlock();

		if(!(aPageCount & flashMask))

			{

			NKern::FlashSystem();

			}

		}

	NKern::UnlockSystem();

	return KErrNone;

	}

TPhysAddr ArmMmu::LinearToPhysical(TLinAddr aLinAddr, TInt aOsAsid)

//

// Find the physical address corresponding to a given linear address in a specified OS

// address space. Call with system locked.

//

	{

	__KTRACE_OPT(KMMU,Kern::Printf("ArmMmu::LinearToPhysical(%08x,%d)",aLinAddr,aOsAsid));