1 // Copyright (c) 2010 Nokia Corporation and/or its subsidiary(-ies). |
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2 // All rights reserved. |
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3 // This component and the accompanying materials are made available |
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4 // under the terms of the License "Eclipse Public License v1.0" |
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5 // which accompanies this distribution, and is available |
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6 // at the URL " http://www.eclipse.org/legal/epl-v10.html ". |
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7 // |
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8 // Initial Contributors: |
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9 // Nokia Corporation - initial contribution. |
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10 // |
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11 // Contributors: |
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12 // |
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13 // Description: |
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14 // os\kernelhwsrv\kernel\eka\drivers\power\smppower\idlehelper.cpp |
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15 // Impelentation of helper classes required to implement CPU idle |
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16 // functionality in a SMP BSP. |
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17 |
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18 /** |
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19 @file |
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20 @prototype |
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21 */ |
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22 |
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23 #include <kernel/arm/arm.h> |
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24 #include <smppower/idlehelper.h> |
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25 |
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26 #ifdef __SMP__ |
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27 //-/-/-/-/-/-/-/-/-/ class TIdleSupport/-/-/-/-/-/-/-/-/-/ |
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28 |
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29 TUint TIdleSupport::iGlobalIntDistAddress=0; |
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30 TUint TIdleSupport::iBaseIntIfAddress=0; |
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31 volatile TUint32* TIdleSupport::iTimerCount=0; |
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32 volatile TUint32 TIdleSupport::iIdlingCpus=0; |
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33 volatile TUint32 TIdleSupport::iAllEngagedCpusMask=0; |
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34 volatile TUint32 TIdleSupport::iRousingCpus=0; |
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35 volatile TUint32 TIdleSupport::iExitRequired=EFalse; |
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36 |
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37 /** |
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38 Setup interrupt access for static library by setting up |
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39 interrupt distributor and CPU interrupt interface addresses |
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40 aGlobalIntDistAddress = interrupt distributor base address |
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41 aBaseIntIfAddress = CPU interrupt base address |
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42 aTimerCount = optional pointer to hw timer counter reg from bsp (only used for btrace) |
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43 @pre |
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44 */ |
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45 |
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46 void TIdleSupport::SetupIdleSupport(TUint32 aGlobalIntDistAddress, TUint32 aBaseIntIfAddress, TUint32* aTimerCount) |
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47 { |
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48 iGlobalIntDistAddress=aGlobalIntDistAddress; |
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49 iBaseIntIfAddress=aBaseIntIfAddress; |
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50 iTimerCount=aTimerCount; /*NULL by default*/ |
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51 iAllEngagedCpusMask=AllCpusMask(); |
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52 } |
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53 /** |
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54 Returns the current HW timer count reg value by default |
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55 Only used for btrace. If this is not set NKern::FastCounter is |
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56 returned. |
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57 */ |
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58 |
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59 TUint32 TIdleSupport::GetTimerCount() |
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60 { |
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61 if(iTimerCount) |
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62 return *iTimerCount; |
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63 else |
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64 return NKern::FastCounter(); |
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65 } |
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66 |
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67 /** |
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68 Returns TRUE if any interrupt is pending,FALSE otherwise |
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69 */ |
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70 |
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71 TBool TIdleSupport::IsIntPending() |
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72 { |
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73 return ((TUint32)IntPending()!=KNoInterruptsPending); |
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74 } |
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75 |
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76 /** |
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77 Set the piroity of the Idle IPI to be the highest |
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78 @pre |
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79 */ |
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80 |
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81 void TIdleSupport::SetIdleIPIToHighestPriority() |
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82 { |
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83 // Set Idle IPI to highest priority |
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84 NKern::ThreadEnterCS(); |
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85 TInt frz = NKern::FreezeCpu(); |
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86 __PM_IDLE_ASSERT_ALWAYS(!frz); |
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87 TInt orig_cpu = NKern::CurrentCpu(); |
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88 TInt ncpu = NKern::NumberOfCpus(); |
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89 TInt cpu = orig_cpu; |
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90 TUint32 orig_affinity = 0; |
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91 do |
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92 { |
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93 TUint32 affinity = NKern::ThreadSetCpuAffinity(NKern::CurrentThread(), (TUint32)cpu); |
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94 if (cpu == orig_cpu) |
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95 { |
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96 orig_affinity = affinity; |
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97 NKern::EndFreezeCpu(frz); |
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98 } |
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99 TInt cpu_now = NKern::CurrentCpu(); |
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100 __PM_IDLE_ASSERT_ALWAYS(cpu_now == cpu); |
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101 |
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102 // here we can set the priority of the IPI vector for each CPU in turn |
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103 GicDistributor* theGIC = (GicDistributor*) TIdleSupport::iGlobalIntDistAddress; |
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104 TUint8* priorities = (TUint8*) &(theGIC->iPriority); |
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105 priorities[IDLE_WAKEUP_IPI_VECTOR]=0x0; |
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106 __e32_io_completion_barrier(); |
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107 if (++cpu == ncpu) |
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108 cpu = 0; |
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109 } while (cpu != orig_cpu); |
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110 NKern::ThreadSetCpuAffinity(NKern::CurrentThread(), orig_affinity); |
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111 NKern::ThreadLeaveCS(); |
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112 } |
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113 |
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114 |
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115 /** |
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116 Atomically clears the current cpu idle mask bit to indicate current core has woken |
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117 up from an interrupt or IPI. |
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118 return TRUE only if all other cores are in idle and we were woken from an IPI from the last |
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119 core going idle (otherwisw FALSE). |
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120 aCpuMask- Bit mask with only current CPU bit set |
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121 Normal usage:use in idle handler after waking from all cores down IPI |
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122 |
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123 @pre |
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124 */ |
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125 TBool TIdleSupport::ClearLocalAndCheckGlobalIdle(TUint32 aCpuMask) |
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126 { |
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127 return (__e32_atomic_and_ord32(&iIdlingCpus,~aCpuMask) & KGlobalIdleFlag); |
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128 } |
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129 |
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130 |
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131 /** |
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132 Atomically sets the cpu bit rousing mask only to indicate current CPU has woken. |
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133 return TRUE only if this is first CPU awake.(otherwise FALSE). |
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134 aCMask- Bit mask with only current CPU bit set |
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135 Normal usage: use in idle handler just after core is woken |
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136 |
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137 @pre */ |
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138 |
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139 |
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140 TBool TIdleSupport::FirstCoreAwake(TUint32 aCMask) |
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141 { |
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142 //TInt c = NKern::CurrentCpu(); |
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143 //TUint32 cMask = (1<<c);//only current cpu mask is set |
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144 return (!__e32_atomic_ior_acq32(&iRousingCpus,aCMask)); |
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145 } |
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146 |
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147 /** |
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148 Sets the exit required flag in TIdleSupport. Exit required is |
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149 normaly required be set if an interrupt is pending on a Core |
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150 aBreakSyncPoint- TBreakableSyncPoint* that all cores were waiting on |
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151 before interrupt occured. Normal usage: after interrupt pending check |
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152 |
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153 @pre */ |
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154 |
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155 void TIdleSupport::SetExitRequired(TBreakableSyncPoint* aBreakSyncPoint) |
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156 { |
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157 iExitRequired=ETrue; |
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158 if(aBreakSyncPoint) |
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159 aBreakSyncPoint->Break(); |
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160 } |
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161 |
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162 /** |
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163 Sets the exit required flag in TIdleSupport. Exit required is |
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164 normaly required be set if an interrupt is pending on a Core |
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165 aBreakSyncPoint- TBreakableSyncPoint that all cores were waiting on |
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166 before interrupt occured. |
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167 |
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168 @pre */ |
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169 |
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170 TBool TIdleSupport::GetExitRequired() |
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171 { |
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172 return iExitRequired; |
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173 } |
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174 |
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175 /** |
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176 Resets all the control flags/syncpoints. This is normally done by the |
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177 last core when all cores are confirmed to be idle. |
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178 |
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179 |
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180 @pre */ |
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181 |
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182 void TIdleSupport::ResetLogic() |
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183 { |
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184 iIdlingCpus = 0; // clear idle CPUs |
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185 iRousingCpus = 0; // clear rousing CPUs |
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186 iExitRequired = EFalse; |
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187 } |
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188 |
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189 |
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190 /** |
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191 mark a core as retired |
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192 |
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193 @pre called by idle handler as part of idle entry before |
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194 any syncpoint or calls to SetLocalAndCheckSetGlobalIdle |
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195 */ |
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196 void TIdleSupport::MarkCoreRetired(TUint32 aCpuMask) |
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197 { |
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198 __e32_atomic_and_rlx32(&iAllEngagedCpusMask,~aCpuMask); |
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199 PMBTRACE4(KRetireCore,KRetireMarkCoreRetired,aCpuMask); |
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200 } |
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201 |
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202 /** |
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203 mark a core as enaged |
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204 @pre called outside idle handler ( can be called in idle entry before |
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205 any syncpoint or calls to SetLocalAndCheckSetGlobalIdle |
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206 */ |
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207 void TIdleSupport::MarkCoreEngaged(TUint32 aCpuMask) |
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208 { |
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209 __e32_atomic_ior_rlx32(&iAllEngagedCpusMask,aCpuMask); |
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210 PMBTRACE4(KEngageCore,KEngageMarkCoreEngaged,aCpuMask); |
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211 } |
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212 |
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213 /** |
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214 Returns the current cpu idling bit mask |
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215 @pre */ |
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216 |
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217 TUint32 TIdleSupport::GetCpusIdleMask() |
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218 { |
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219 return iIdlingCpus; |
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220 } |
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221 |
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222 /** |
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223 Returns address of enaged cpus mask, needed for synch point construction |
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224 |
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225 */ |
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226 |
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227 volatile TUint32* TIdleSupport::EngagedCpusMaskAddr() |
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228 { |
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229 return &iAllEngagedCpusMask; |
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230 } |
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231 |
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232 /** |
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233 Returns address of enaged cpus mask, needed for synch point construction |
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234 |
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235 */ |
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236 |
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237 TUint32 TIdleSupport::AllCpusMask() |
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238 { |
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239 return ((0x1<<NKern::NumberOfCpus())-1); |
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240 } |
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241 |
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242 /** |
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243 clears IPI and asserts so in |
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244 @pre */ |
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245 #ifdef _DEBUG |
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246 void TIdleSupport::ClearIdleIPI() |
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247 { |
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248 __PM_IDLE_ASSERT_ALWAYS((DoClearIdleIPI()&0x1ff)==IDLE_WAKEUP_IPI_VECTOR); |
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249 } |
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250 #endif |
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251 |
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252 |
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253 //-/-/-/-/-/-/-/-/-/ class TSyncPointBase /-/-/-/-/-/-/-/-/-/ |
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254 TSyncPointBase::TSyncPointBase() |
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255 :iStageAndCPUWaitingMask(0), |
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256 iAllEnagedCpusMask(TIdleSupport::EngagedCpusMaskAddr()) |
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257 { |
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258 } |
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259 |
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260 |
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261 #ifdef _DEBUG |
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262 void TSyncPointBase::SignalAndWait(TUint32 aStage) |
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263 { |
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264 PMBTRACE8(KSyncPoint,KSignalAndWaitEntry,aStage,*iAllEnagedCpusMask); |
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265 #else |
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266 void TSyncPointBase::SignalAndWait() |
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267 { |
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268 #endif |
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269 TInt c = NKern::CurrentCpu(); |
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270 DoSW(1<<c); |
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271 #ifdef _DEBUG |
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272 PMBTRACE0(KSyncPoint,KSignalAndWaiteXit); |
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273 #endif |
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274 } |
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275 |
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276 |
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277 /** |
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278 Resets a syncpoint. |
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279 No barriers are used in function so add them if required. For breakable synchpoints this must be called before sync point can be used, |
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280 for normal syncpoints this must be called whenever a CPU gets enaged |
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281 @pre Should be called from one CPU. |
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282 */ |
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283 void TSyncPointBase::Reset() |
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284 { |
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285 // Could assert it is already broken // not using atomics because this must be called from only one cpu before |
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286 // and be synchronised |
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287 iStageAndCPUWaitingMask = 0; |
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288 } |
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289 |
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290 |
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291 //-/-/-/-/-/-/-/-/-/ class TBreakableSyncPoint /-/-/-/-/-/-/-/-/-/ |
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292 |
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293 /** |
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294 Breaks the sync point until it is reset again. Any attempt to wait on the point will return inmediatelly until the point is reset |
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295 */ |
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296 void TBreakableSyncPoint::Break() |
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297 { |
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298 __e32_atomic_ior_ord32(&iStageAndCPUWaitingMask,0x80000000); |
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299 } |
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300 |
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301 |
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302 #endif //__SMP__ |
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