1273 { |
1273 { |
1274 return ChunkPtePermissions[aChunkType]; |
1274 return ChunkPtePermissions[aChunkType]; |
1275 } |
1275 } |
1276 |
1276 |
1277 const TUint FBLK=(EMapAttrFullyBlocking>>12); |
1277 const TUint FBLK=(EMapAttrFullyBlocking>>12); |
|
1278 const TUint BFNC=(EMapAttrBufferedNC>>12); |
1278 const TUint BUFC=(EMapAttrBufferedC>>12); |
1279 const TUint BUFC=(EMapAttrBufferedC>>12); |
|
1280 const TUint L1UN=(EMapAttrL1Uncached>>12); |
1279 const TUint WTRA=(EMapAttrCachedWTRA>>12); |
1281 const TUint WTRA=(EMapAttrCachedWTRA>>12); |
|
1282 const TUint WTWA=(EMapAttrCachedWTWA>>12); |
1280 const TUint WBRA=(EMapAttrCachedWBRA>>12); |
1283 const TUint WBRA=(EMapAttrCachedWBRA>>12); |
1281 |
1284 const TUint WBWA=(EMapAttrCachedWBWA>>12); |
1282 #if defined(__CPU_XSCALE__) || defined(__CPU_SA1__) |
1285 const TUint AWTR=(EMapAttrAltCacheWTRA>>12); |
|
1286 const TUint AWTW=(EMapAttrAltCacheWTWA>>12); |
1283 const TUint AWBR=(EMapAttrAltCacheWBRA>>12); |
1287 const TUint AWBR=(EMapAttrAltCacheWBRA>>12); |
1284 #endif |
1288 const TUint AWBW=(EMapAttrAltCacheWBWA>>12); |
|
1289 const TUint MAXC=(EMapAttrL1CachedMax>>12); |
|
1290 |
|
1291 const TUint L2UN=(EMapAttrL2Uncached>>12); |
1285 |
1292 |
1286 const TUint16 UNS=0xffffu; // Unsupported attribute |
1293 const TUint16 UNS=0xffffu; // Unsupported attribute |
1287 |
1294 const TUint16 SPE=0xfffeu; // Special processing required |
1288 |
1295 |
1289 #if defined(__CPU_ARM710T__) || defined(__CPU_ARM720T__) |
1296 #if defined(__CPU_ARM710T__) || defined(__CPU_ARM720T__) |
1290 // Original definition of C B |
1297 // Original definition of C B |
1291 static const TUint16 CacheBuffAttributes[16]= |
1298 static const TUint16 CacheBuffAttributes[16]= |
1292 {0x00,0x00,0x04,0x04,0x0C,0x0C,0x0C,0x0C, UNS, UNS, UNS, UNS, UNS, UNS, UNS,0x0C}; |
1299 {0x00,0x00,0x04,0x04,0x0C,0x0C,0x0C,0x0C, UNS, UNS, UNS, UNS, UNS, UNS, UNS,0x0C}; |
1306 {0x00,0x00,0x04,0x04,0x04,0x04,0x0C,0x0C,0x04,0x04,0x08,0x08, UNS, UNS, UNS,0x0C}; |
1313 {0x00,0x00,0x04,0x04,0x04,0x04,0x0C,0x0C,0x04,0x04,0x08,0x08, UNS, UNS, UNS,0x0C}; |
1307 static const TUint8 CacheBuffActual[16]= |
1314 static const TUint8 CacheBuffActual[16]= |
1308 {FBLK,FBLK,BUFC,BUFC,BUFC,BUFC,WBRA,WBRA,FBLK,FBLK,AWBR,AWBR,FBLK,FBLK,FBLK,WBRA}; |
1315 {FBLK,FBLK,BUFC,BUFC,BUFC,BUFC,WBRA,WBRA,FBLK,FBLK,AWBR,AWBR,FBLK,FBLK,FBLK,WBRA}; |
1309 |
1316 |
1310 #elif defined(__CPU_XSCALE__) |
1317 #elif defined(__CPU_XSCALE__) |
1311 const TUint WBWA=(EMapAttrCachedWBWA>>12); |
|
1312 const TUint16 SPE=0xfffeu; // Special processing required |
|
1313 |
|
1314 #ifdef __CPU_XSCALE_MANZANO__ |
1318 #ifdef __CPU_XSCALE_MANZANO__ |
1315 const TUint L1UN=(EMapAttrL1Uncached>>12); |
|
1316 const TUint BFNC=(EMapAttrBufferedNC>>12); |
|
1317 |
|
1318 #ifdef __HAS_EXTERNAL_CACHE__ |
1319 #ifdef __HAS_EXTERNAL_CACHE__ |
1319 // ***MANZANO with L2 cache****** // |
1320 // ***MANZANO with L2 cache****** // |
1320 const TUint L2UN=(EMapAttrL2Uncached>>12); |
|
1321 const TUint MAXC=(EMapAttrL1CachedMax>>12); |
|
1322 |
1321 |
1323 //Specifies TEX::CB bits for different L1/L2 cache attributes |
1322 //Specifies TEX::CB bits for different L1/L2 cache attributes |
1324 // ...876543201 |
1323 // ...876543201 |
1325 // ...TEX..CB.. |
1324 // ...TEX..CB.. |
1326 static const TUint16 CacheBuffAttributes[80]= |
1325 static const TUint16 CacheBuffAttributes[80]= |