equal
deleted
inserted
replaced
84 */ |
84 */ |
85 EXPORT_C TLinAddr X86::IrqStackTop(TInt aCpu) |
85 EXPORT_C TLinAddr X86::IrqStackTop(TInt aCpu) |
86 { |
86 { |
87 TLinAddr a = 0; |
87 TLinAddr a = 0; |
88 if (aCpu>=0 && aCpu<KMaxCpus) |
88 if (aCpu>=0 && aCpu<KMaxCpus) |
89 a = TLinAddr(TheSubSchedulers[aCpu].iSSX.iIrqStackTop); |
89 a = TLinAddr(TheSubSchedulers[aCpu].i_IrqStackTop); |
90 else |
90 else |
91 { |
91 { |
92 TInt irq = NKern::DisableAllInterrupts(); |
92 TInt irq = NKern::DisableAllInterrupts(); |
93 a = TLinAddr(SubScheduler().iSSX.iIrqStackTop); |
93 a = TLinAddr(SubScheduler().i_IrqStackTop); |
94 NKern::RestoreInterrupts(irq); |
94 NKern::RestoreInterrupts(irq); |
95 } |
95 } |
96 return a; |
96 return a; |
97 } |
97 } |
98 |
98 |
148 cd.iTss.iSs0 = KRing0DS; |
148 cd.iTss.iSs0 = KRing0DS; |
149 cd.iTss.iEsp0 = esp; |
149 cd.iTss.iEsp0 = esp; |
150 SetTssDescriptor(&cp.iGdt[5+i], &cd.iTss); |
150 SetTssDescriptor(&cp.iGdt[5+i], &cd.iTss); |
151 |
151 |
152 TSubScheduler& ss = TheSubSchedulers[i]; |
152 TSubScheduler& ss = TheSubSchedulers[i]; |
153 ss.iSSX.iIrqNestCount = (TLinAddr)(-1); |
153 ss.i_IrqNestCount = (TAny*)(-1); |
154 ss.iSSX.iIrqStackTop = (TLinAddr)esp; |
154 ss.i_IrqStackTop = (TAny*)esp; |
155 ss.iSSX.iTss = &cd.iTss; |
155 ss.i_Tss = &cd.iTss; |
156 } |
156 } |
157 |
157 |
158 X86::DefaultCR0 = get_cr0(); |
158 X86::DefaultCR0 = get_cr0(); |
159 NIrq::HwInit1(); |
159 NIrq::HwInit1(); |
160 |
160 |