equal
deleted
inserted
replaced
87 // is fixed on this hardware, or |
87 // is fixed on this hardware, or |
88 // 2) using the ARM1176 processor and ARM1176 Erratum 415047 "Cancelled write to CONTEXTID register might update ASID" |
88 // 2) using the ARM1176 processor and ARM1176 Erratum 415047 "Cancelled write to CONTEXTID register might update ASID" |
89 // is fixed on this hardware. |
89 // is fixed on this hardware. |
90 // |
90 // |
91 // macro __CPU_ARM1136_ERRATUM_408022_FIXED |
91 // macro __CPU_ARM1136_ERRATUM_408022_FIXED |
92 |
92 |
93 // Uncomment if: |
93 // Uncomment if: |
94 // 1) using ARM1136 processor and ARM1136 Erratum 411920: "Invalidate Entire Instruction Cache |
94 // 1) using ARM1136 processor and ARM1136 Erratum 411920: "Invalidate Entire Instruction Cache |
95 // operation might fail to invalidate some lines if coincident with linefill" |
95 // operation might fail to invalidate some lines if coincident with linefill" |
96 // is fixed on this hardware, or |
96 // is fixed on this hardware, or |
97 // 2) using ARM1176 processor and ARM1176 Erratum 415045: "Invalidate Entire Instruction Cache |
97 // 2) using ARM1176 processor and ARM1176 Erratum 415045: "Invalidate Entire Instruction Cache |
102 // 2) Replaces Invalidate ICache operation with the sequence defined in the errata document. |
102 // 2) Replaces Invalidate ICache operation with the sequence defined in the errata document. |
103 // If this macro is enabled, it should be accompanied by: |
103 // If this macro is enabled, it should be accompanied by: |
104 // "GBLL CFG_CPU_ARM1136_ERRATUM_411920_FIXED" in variant.mmh |
104 // "GBLL CFG_CPU_ARM1136_ERRATUM_411920_FIXED" in variant.mmh |
105 // |
105 // |
106 // macro __CPU_ARM1136_ERRATUM_411920_FIXED |
106 // macro __CPU_ARM1136_ERRATUM_411920_FIXED |
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107 |
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108 // Uncomment next line if using the ARM1176 processor and ARM1176 Erratum 720013 "Invalidate Instruction |
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109 // Cache operations can fail" is fixed on this hardware. |
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110 // |
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111 // macro __CPU_ARM1176_ERRATUM_720013_FIXED |
107 |
112 |
108 // TO DO: |
113 // TO DO: |
109 // |
114 // |
110 // Uncomment the next line if using the ARM1136 processor with L210/L220 cache and ARM1136 |
115 // Uncomment the next line if using the ARM1136 processor with L210/L220 cache and ARM1136 |
111 // Erratum 317041:"TTBR0/TTBR1 bits[4:3] do not read back correctly" |
116 // Erratum 317041:"TTBR0/TTBR1 bits[4:3] do not read back correctly" |