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1 // Copyright (c) 2002-2009 Nokia Corporation and/or its subsidiary(-ies). |
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2 // All rights reserved. |
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3 // This component and the accompanying materials are made available |
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4 // under the terms of "Eclipse Public License v1.0" |
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5 // which accompanies this distribution, and is available |
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6 // at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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7 // |
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8 // Initial Contributors: |
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9 // Nokia Corporation - initial contribution. |
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10 // |
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11 // Contributors: |
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12 // |
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13 // Description: |
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14 // include/drivers/dmadefs.h |
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15 // DMA Framework - General class, enum, constant and type definitions. |
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16 // |
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17 // |
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18 |
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19 #ifndef __DMADEFS_H__ |
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20 #define __DMADEFS_H__ |
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21 |
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22 |
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23 #include <e32def.h> |
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24 |
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25 |
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26 /** The client request callback type */ |
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27 enum TDmaCallbackType |
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28 { |
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29 /** Transfer request completion callback */ |
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30 EDmaCallbackRequestCompletion = 0x01, |
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31 /** Transfer request completion callback - source side */ |
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32 EDmaCallbackRequestCompletion_Src = 0x02, |
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33 /** Transfer request completion callback - destination side */ |
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34 EDmaCallbackRequestCompletion_Dst = 0x04, |
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35 |
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36 /** Descriptor completion callback */ |
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37 EDmaCallbackDescriptorCompletion = 0x08, |
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38 /** Descriptor completion callback - source side */ |
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39 EDmaCallbackDescriptorCompletion_Src = 0x10, |
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40 /** Descriptor completion callback - destination side */ |
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41 EDmaCallbackDescriptorCompletion_Dst = 0x20, |
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42 |
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43 /** Frame completion callback */ |
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44 EDmaCallbackFrameCompletion = 0x40, |
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45 /** Frame completion callback - source side */ |
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46 EDmaCallbackFrameCompletion_Src = 0x80, |
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47 /** Frame completion callback - destination side */ |
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48 EDmaCallbackFrameCompletion_Dst = 0x100, |
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49 |
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50 /** H/W descriptor pause event callback */ |
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51 EDmaCallbackLinkedListPaused = 0x200, |
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52 /** H/W descriptor pause event callback - source side */ |
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53 EDmaCallbackLinkedListPaused_Src = 0x400, |
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54 /** H/W descriptor pause event callback - destination side */ |
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55 EDmaCallbackLinkedListPaused_Dst = 0x800 |
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56 }; |
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57 |
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58 |
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59 /** The outcome of the transfer request */ |
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60 enum TDmaResult |
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61 { |
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62 /** Completed without error */ |
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63 EDmaResultOK = 0, |
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64 /** There was an error */ |
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65 EDmaResultError |
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66 }; |
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67 |
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68 |
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69 |
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70 /** To be used with address mode field of the DMA transfer config struct. |
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71 |
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72 @see TDmaTransferConfig::iAddrMode |
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73 */ |
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74 enum TDmaAddrMode |
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75 { |
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76 /** Constant addressing. The address remains the same for consecutive |
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77 accesses. |
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78 */ |
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79 KDmaAddrModeConstant, |
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80 /** Post-increment addressing. The address increases by the element size |
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81 after each access. |
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82 */ |
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83 KDmaAddrModePostIncrement, |
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84 /** Post-decrement addressing. The address decreases by the element size |
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85 after each access. |
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86 */ |
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87 KDmaAddrModePostDecrement, |
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88 /** 1D-index addressing. The address always increases by the element size |
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89 plus the element skip value after each access. |
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90 */ |
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91 KDmaAddrMode1DIndex, |
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92 /** 2D-index addressing. The address increases by the element size plus the |
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93 element skip value - but only within a frame. Once a full frame has been |
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94 transferred, the address increases by the element size plus the element |
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95 skip value plus the frame skip value. |
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96 */ |
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97 KDmaAddrMode2DIndex |
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98 }; |
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99 |
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100 |
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101 /** To be used with the burst size field of the DMA transfer config struct. |
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102 |
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103 @see SDmacCaps::iBurstTransactions |
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104 @see TDmaTransferConfig::iBurstSize |
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105 */ |
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106 enum TDmaBurstSize |
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107 { |
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108 /** Don't use burst transactions */ |
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109 KDmaNoBursts = -1, |
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110 /** Don't care (the default) */ |
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111 KDmaBurstSizeAny = 0x00, |
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112 /** 4 bytes */ |
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113 KDmaBurstSize4 = 0x04, |
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114 /** 8 bytes */ |
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115 KDmaBurstSize8 = 0x08, |
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116 /** 16 bytes */ |
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117 KDmaBurstSize16 = 0x10, |
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118 /** 32 bytes */ |
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119 KDmaBurstSize32 = 0x20, |
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120 /** 64 bytes */ |
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121 KDmaBurstSize64 = 0x40, |
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122 /** 128 bytes */ |
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123 KDmaBurstSize128 = 0x80 |
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124 }; |
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125 |
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126 |
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127 /** To be used with the flags field of the DMA transfer config struct. |
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128 |
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129 @see TDmaTransferConfig::iFlags |
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130 */ |
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131 enum TDmaTransferFlags |
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132 { |
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133 /** Location is address of a memory buffer (as opposed to a peripheral or a |
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134 register). |
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135 */ |
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136 KDmaMemAddr = 0x01, |
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137 /** Address is a physical address (as opposed to a linear one). |
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138 If it is a memory address then KDmaMemIsContiguous will need to be set |
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139 as well. |
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140 */ |
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141 KDmaPhysAddr = 0x02, |
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142 /** Target memory is known to be physically contiguous, hence there is |
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143 no need for the framework to check for memory fragmentation. |
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144 */ |
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145 KDmaMemIsContiguous = 0x04, |
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146 /** Don't use packed access (if possible) */ |
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147 KDmaDontUsePacked = 0x08, |
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148 /** Location is big endian (little endian if not set). |
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149 |
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150 To have any effect, this flag requires the DMAC to support endianness |
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151 conversion. |
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152 |
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153 @see SDmacCaps::iEndiannessConversion |
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154 */ |
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155 KDmaBigEndian = 0x10, |
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156 /** Don't do endianness conversion even if applicable. |
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157 |
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158 To have any effect, this flag requires the DMAC to support endianness |
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159 conversion. |
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160 |
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161 @see SDmacCaps::iEndiannessConversion |
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162 */ |
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163 KDmaLockEndian = 0x20, |
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164 /** Execute client request callback after each subtransfer (streaming / |
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165 loop case). |
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166 |
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167 This option is only taken into account if the respective |
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168 TDmaTransferConfig::iRepeatCount is non-zero. |
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169 |
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170 The callback will complete with a TDmaCallbackType of |
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171 EDmaCallbackRequestCompletion (even if the repeat counts for source and |
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172 destination are different), unless the flag |
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173 TDmaPILFlags::KDmaAsymCompletionCallback is set too, in which case what |
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174 is described there applies. |
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175 */ |
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176 KDmaCallbackAfterEveryTransfer = 0x40, |
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177 /** Execute client request callback after each completed hardware |
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178 descriptor. |
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179 |
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180 Requires the DMAC to support this feature. Unless the DMAC supports |
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181 asymmetric descriptor interrupts as well, this flag should not be set |
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182 on only one (source or destination) side. |
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183 |
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184 @see SDmacCaps::iDescriptorInterrupt |
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185 @see SDmacCaps::iAsymDescriptorInterrupt |
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186 */ |
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187 KDmaCallbackAfterEveryDescriptor = 0x80, |
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188 /** Execute client request callback after each completed frame. |
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189 |
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190 Requires the DMAC to support this feature. Unless the DMAC supports |
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191 asymmetric frame interrupts as well, this flag should not be set on |
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192 only one (source or destination) side. |
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193 |
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194 @see SDmacCaps::iFrameInterrupt |
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195 @see SDmacCaps::iAsymFrameInterrupt |
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196 */ |
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197 KDmaCallbackAfterEveryFrame = 0x100 |
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198 }; |
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199 |
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200 |
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201 /** To be used with the synchronization flags field of a DMA transfer |
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202 config struct. |
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203 |
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204 @see SDmacCaps::iSynchronizationTypes |
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205 @see TDmaTransferConfig::iSyncFlags |
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206 */ |
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207 enum TDmaTransferSyncFlags |
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208 { |
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209 /** Leave the decision on whether the transfer is hardware synchronized at |
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210 this end (either source or destination) to the Framework. This is the |
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211 default. |
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212 */ |
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213 KDmaSyncAuto = 0x00, |
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214 /** Transfer is not hardware synchronized at this end (either source or |
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215 destination). |
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216 */ |
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217 KDmaSyncNone = 0x01, |
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218 /** Transfer is hardware synchronized at this end (either source or |
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219 destination). This option can also be used on its own, without any |
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220 of the following sync sizes. |
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221 */ |
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222 KDmaSyncHere = 0x02, |
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223 /** H/W synchronized at this end: transfer one ELEMENT (a number of |
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224 bytes, depending on the configured element size) per sync event. |
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225 */ |
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226 KDmaSyncSizeElement = 0x04, |
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227 /** H/W synchronized at this end: transfer one FRAME (a number of |
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228 elements, depending on the configured frame size) per sync event. |
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229 */ |
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230 KDmaSyncSizeFrame = 0x08, |
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231 /** H/W synchronized at this end: transfer one BLOCK (a number of |
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232 frames, depending on the configured transfer size) per sync |
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233 event. This is the most common use case. |
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234 */ |
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235 KDmaSyncSizeBlock = 0x10, |
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236 /** H/W synchronized at this end: transfer one PACKET (a number of |
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237 elements, depending on the configured packet size) per sync event. |
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238 In cases where the transfer block size is not a multiple of the |
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239 packet size the last packet will consist of the remaining elements. |
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240 */ |
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241 KDmaSyncSizePacket = 0x20 |
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242 }; |
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243 |
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244 |
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245 /** To be used with the Graphics operation field of a DMA transfer request. |
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246 |
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247 @see TDmaTransferArgs::iGraphicsOps |
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248 */ |
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249 enum TDmaGraphicsOps |
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250 { |
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251 /** Don't use any graphics acceleration feature (the default) */ |
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252 KDmaGraphicsOpNone = 0x00, |
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253 /** Enable graphics acceleration feature 'Constant Fill' */ |
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254 KDmaGraphicsOpConstantFill = 0x01, |
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255 /** Enable graphics acceleration feature 'TransparentCopy' */ |
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256 KDmaGraphicsOpTransparentCopy = 0x02 |
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257 }; |
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258 |
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259 |
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260 /** To be used with the PIL flags field of a DMA transfer request. |
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261 |
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262 @see TDmaTransferArgs::iFlags |
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263 */ |
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264 enum TDmaPILFlags |
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265 { |
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266 /** Request a different max transfer size (for instance for test |
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267 purposes). |
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268 */ |
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269 KDmaAltTransferLength = 0x01, |
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270 /** Execute client request callback in ISR context instead of from a |
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271 DFC. |
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272 */ |
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273 KDmaRequestCallbackFromIsr = 0x02, |
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274 /** Execute descriptor completion callback in ISR context instead of |
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275 from a DFC. This option is to be used in conjunction with the |
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276 TDmaTransferFlags::KDmaCallbackAfterEveryDescriptor flag. |
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277 */ |
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278 KDmaDescriptorCallbackFromIsr = 0x04, |
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279 /** Execute frame completion callback in ISR context instead of |
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280 from a DFC. This option is to be used in conjunction with the |
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281 TDmaTransferFlags::KDmaCallbackAfterEveryFrame flag. |
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282 */ |
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283 KDmaFrameCallbackFromIsr = 0x08, |
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284 /** Execute the client request callback separately for source and |
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285 destination subtransfers. |
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286 |
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287 This flag also determines the TDmaCallbackType value returned. If set, |
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288 the callback will complete with EDmaCallbackRequestCompletion_Src or |
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289 EDmaCallbackRequestCompletion_Dst, respectively, instead of with |
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290 EDmaCallbackRequestCompletion. |
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291 |
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292 Requires the DMAC to support this feature. |
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293 |
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294 @see SDmacCaps::iAsymCompletionInterrupt |
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295 */ |
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296 KDmaAsymCompletionCallback = 0x10, |
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297 /** Execute the descriptor completion callback separately for source |
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298 and destination subtransfers. |
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299 |
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300 This flag modifies the behaviour of the |
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301 TDmaTransferFlags::KDmaCallbackAfterEveryDescriptor flag and also |
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302 determines the TDmaCallbackType value returned. If set, the callback |
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303 will complete with EDmaCallbackDescriptorCompletion_Src or |
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304 EDmaCallbackDescriptorCompletion_Dst, respectively, instead of with |
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305 EDmaCallbackDescriptorCompletion. |
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306 |
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307 Requires the DMAC to support this feature. |
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308 |
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309 @see SDmacCaps::iAsymDescriptorInterrupt |
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310 */ |
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311 KDmaAsymDescriptorCallback = 0x20, |
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312 /** Execute the frame completion callback separately for source and |
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313 destination subtransfers. |
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314 |
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315 This flag modifies the behaviour of the |
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316 TDmaTransferFlags::KDmaCallbackAfterEveryFrame flag. If set, the |
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317 callback will complete with EDmaCallbackFrameCompletion_Src or |
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318 EDmaCallbackFrameCompletion_Dst, respectively, instead of with |
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319 EDmaCallbackFrameCompletion. |
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320 |
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321 Requires the DMAC to support this feature. |
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322 |
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323 @see SDmacCaps::iAsymFrameInterrupt |
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324 */ |
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325 KDmaAsymFrameCallback = 0x40, |
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326 /** This transfer (only) should use the channel priority indicated by |
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327 TDmaTransferArgs::iChannelPriority. |
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328 */ |
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329 KDmaRequestChannelPriority = 0x80 |
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330 }; |
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331 |
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332 |
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333 /** Values which can be used with the priority field when opening a channel |
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334 and/or when fragmenting a transfer request. |
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335 |
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336 @see TDmaChannel::SCreateInfo::iPriority |
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337 @see TDmaTransferArgs::iChannelPriority |
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338 */ |
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339 enum TDmaPriority |
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340 { |
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341 /** No transfer priority preference (don't care value) */ |
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342 KDmaPriorityNone = 0x0, |
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343 /** Platform-independent transfer priority 1 (lowest) */ |
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344 KDmaPriority1 = 0x80000001, |
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345 /** Platform-independent transfer priority 2 */ |
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346 KDmaPriority2 = 0x80000002, |
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347 /** Platform-independent transfer priority 3 */ |
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348 KDmaPriority3 = 0x80000003, |
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349 /** Platform-independent transfer priority 4 */ |
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350 KDmaPriority4 = 0x80000004, |
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351 /** Platform-independent transfer priority 5 */ |
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352 KDmaPriority5 = 0x80000005, |
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353 /** Platform-independent transfer priority 6 */ |
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354 KDmaPriority6 = 0x80000006, |
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355 /** Platform-independent transfer priority 7 */ |
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356 KDmaPriority7 = 0x80000007, |
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357 /** Platform-independent transfer priority 8 (highest) */ |
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358 KDmaPriority8 = 0x80000008 |
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359 }; |
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360 |
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361 |
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362 /** Contains the configuration values for either the source or the |
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363 destination side of a DMA transfer. |
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364 |
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365 Note that some fields (notably iElementSize, iElementsPerFrame and |
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366 iFramesPerTransfer) may only differ between source and destination if |
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367 the underlying DMAC supports this. |
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368 |
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369 @see SDmacCaps::iSrcDstAsymmetry |
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370 @see TDmaTransferArgs::iSrcConfig |
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371 @see TDmaTransferArgs::iDstConfig |
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372 */ |
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373 struct TDmaTransferConfig |
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374 { |
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375 friend struct TDmaTransferArgs; |
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376 |
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377 /** Default constructor. Initializes all fields with meaningful default |
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378 values. |
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379 */ |
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380 #ifdef DMA_APIV2 |
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381 KIMPORT_C |
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382 #endif |
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383 TDmaTransferConfig(); |
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384 |
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385 /** Intended for general use ie. not 2D or 1D transfers |
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386 */ |
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387 #ifdef DMA_APIV2 |
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388 KIMPORT_C |
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389 #endif |
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390 TDmaTransferConfig ( |
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391 TUint32 aAddr, |
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392 TUint aTransferFlags, |
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393 TDmaAddrMode aAddrMode = KDmaAddrModePostIncrement, |
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394 TUint aSyncFlags = KDmaSyncAuto, |
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395 TDmaBurstSize aBurstSize = KDmaBurstSizeAny, |
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396 TUint aElementSize = 0, |
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397 TUint aElementsPerPacket = 0, |
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398 TUint aPslTargetInfo = 0, |
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399 TInt aRepeatCount = 0 |
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400 ); |
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401 |
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402 /** Intended for 1D and 2D transfers |
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403 */ |
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404 #ifdef DMA_APIV2 |
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405 KIMPORT_C |
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406 #endif |
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407 TDmaTransferConfig ( |
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408 TUint32 aAddr, |
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409 TUint aElementSize, |
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410 TUint aElementsPerFrame, |
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411 TUint aFramesPerTransfer, |
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412 TInt aElementSkip, |
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413 TInt aFrameSkip, |
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414 TUint aTransferFlags, |
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415 TUint aSyncFlags = KDmaSyncAuto, |
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416 TDmaBurstSize aBurstSize = KDmaBurstSizeAny, |
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417 TUint aElementsPerPacket = 0, |
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418 TUint aPslTargetInfo = 0, |
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419 TInt aRepeatCount = 0 |
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420 ); |
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421 |
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422 /** Transfer start address */ |
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423 TUint32 iAddr; |
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424 /** Address mode */ |
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425 TDmaAddrMode iAddrMode; |
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426 /** Element size in bytes (1/2/4/8) */ |
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427 TUint iElementSize; |
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428 /** Number of elements per frame */ |
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429 TUint iElementsPerFrame; |
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430 /** Number of elements per packet */ |
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431 TUint iElementsPerPacket; |
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432 /** Number of frames to transfer (result is the transfer block) */ |
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433 TUint iFramesPerTransfer; |
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434 /** Element skip in bytes (for addr modes E1DIndex or E2DIndex) */ |
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435 TInt iElementSkip; |
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436 /** Frame skip in bytes (for addr mode E2DIndex) */ |
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437 TInt iFrameSkip; |
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438 /** Use burst transactions of the specified size (in bytes) |
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439 @see TDmaBurstSize |
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440 */ |
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441 TInt iBurstSize; |
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442 /** PIL src/dst config flags. |
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443 @see TDmaTransferFlags |
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444 */ |
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445 TUint32 iFlags; |
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446 /** Transfer synchronization flags. |
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447 @see TDmaTransferSyncFlags |
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448 */ |
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449 TUint32 iSyncFlags; |
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450 /** Information passed to the PSL */ |
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451 TUint iPslTargetInfo; |
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452 /** How often to repeat this (sub-)transfer: |
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453 0 no repeat (the default) |
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454 1..n once / n times |
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455 -1 endlessly. |
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456 */ |
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457 TInt iRepeatCount; |
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458 /** Structure contents delta vector (usage tbd) */ |
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459 TUint32 iDelta; |
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460 /** Reserved for future use */ |
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461 TUint32 iReserved; |
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462 |
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463 private: |
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464 /** Private constructor. Initializes fields with the values passed in by |
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465 the legacy version of the DDmaRequest::Fragment() call. |
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466 */ |
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467 TDmaTransferConfig(TUint32 aAddr, TUint aFlags, TBool aAddrInc); |
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468 }; |
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469 |
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470 |
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471 /** To be used by the client to pass DMA transfer request details to the |
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472 framework. |
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473 |
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474 Also used internally by the framework as a pseudo descriptor if the |
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475 controller doesn't support hardware descriptors (scatter/gather LLI). |
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476 |
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477 @see DDmaRequest::Fragment |
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478 */ |
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479 struct TDmaTransferArgs |
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480 { |
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481 friend class DDmaRequest; |
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482 friend class TDmaChannel; |
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483 friend class TDmac; |
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484 friend class DmaChannelMgr; |
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485 |
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486 /** Default constructor. Initializes all fields with meaningful default |
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487 values. |
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488 */ |
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489 #ifdef DMA_APIV2 |
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490 KIMPORT_C |
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491 #endif |
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492 TDmaTransferArgs(); |
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493 |
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494 /** For transfers where src and dst TDmaTransferConfig structs share some |
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495 of the same options ie. iDmaTransferFlags, iAddrMode, iSyncFlags, |
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496 iBurstSize, and iElementSize. |
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497 |
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498 @param aSrcAddr |
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499 @param aDstAddr |
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500 @param aCount Number of bytes to transfer |
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501 @param aDmaTransferFlags Bitmask of TDmaTransferFlags for src and dst |
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502 @param aDmaSyncFlags Bitmask of TDmaTransferSyncFlags for src and dst |
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503 @param aMode Address mode for src and dst |
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504 @param aDmaPILFlags Bitmask of TDmaPILFlags |
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505 @param aElementSize In bytes (1/2/4/8) for src and dst |
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506 @param aChannelPriority |
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507 @param aBurstSize for src and dst |
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508 @param aPslRequestInfo Info word passed to the PSL |
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509 @param aGraphicOp Graphics operation to be executed |
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510 @param aColour Colour value for graphics operation |
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511 */ |
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512 #ifdef DMA_APIV2 |
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513 KIMPORT_C |
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514 #endif |
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515 TDmaTransferArgs ( |
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516 TUint aSrcAddr, TUint aDstAddr, TUint aCount, |
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517 TUint aDmaTransferFlags, TUint aDmaSyncFlags = KDmaSyncAuto, |
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518 TUint aDmaPILFlags = 0, |
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519 TDmaAddrMode aMode = KDmaAddrModePostIncrement, TUint aElementSize = 0, |
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520 TUint aChannelPriority = KDmaPriorityNone, |
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521 TDmaBurstSize aBurstSize = KDmaBurstSizeAny, TUint aPslRequestInfo = 0, |
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522 TDmaGraphicsOps aGraphicOp = KDmaGraphicsOpNone, TUint32 aColour = 0 |
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523 ); |
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524 |
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525 /** For transfers needing specific options for source and destination |
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526 TDmaTransferConfig structs. |
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527 |
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528 @param aSrc Configuration values for the source |
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529 @param aDst Configuration values for the destination |
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530 @param aFlags @see TDmaPILFlags |
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531 @param aChannelPriority Use for this request (only) the indicated |
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532 channel priority. Requires KDmaRequestChannelPriority to be set in |
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533 iFlags as well. @see TDmaPriority |
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534 |
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535 @param aPslRequestInfo Info word passed to the PSL |
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536 @param aGraphicOp Graphics operation to be executed |
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537 @param aColour Colour value for graphics operation |
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538 */ |
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539 #ifdef DMA_APIV2 |
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540 KIMPORT_C |
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541 #endif |
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542 TDmaTransferArgs ( |
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543 const TDmaTransferConfig& aSrc, |
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544 const TDmaTransferConfig& aDst, |
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545 TUint32 aFlags = 0, |
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546 TUint aChannelPriority = KDmaPriorityNone, |
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547 TUint aPslRequestInfo = 0, |
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548 TDmaGraphicsOps aGraphicOp = KDmaGraphicsOpNone, TUint32 aColour = 0 |
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549 ); |
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550 |
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551 /** Configuration values for the source */ |
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552 TDmaTransferConfig iSrcConfig; |
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553 /** Configuration values for the destination */ |
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554 TDmaTransferConfig iDstConfig; |
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555 |
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556 /** Number of bytes to transfer (optional). |
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557 |
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558 A non-zero value here must be consistent with iElementSize, |
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559 iElementsPerFrame and iFramesPerTransfer in iSrcConfig and iDstConfig |
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560 if the latter are specified as well (or instead, they may be left at |
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561 their default values of zero). |
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562 |
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563 If zero, the PIL will fill in a value calculated from multiplying |
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564 iElementSize, iElementsPerFrame and iFramesPerTransfer in iSrcConfig, |
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565 so that the PSL can rely on it being always non-zero and valid. |
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566 */ |
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567 TUint iTransferCount; |
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568 /** Graphics operation to be executed */ |
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569 TDmaGraphicsOps iGraphicsOps; |
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570 /** Colour value for graphics operations */ |
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571 TUint32 iColour; |
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572 /** PIL common flags |
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573 @see TDmaPILFlags |
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574 */ |
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575 TUint32 iFlags; |
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576 /** Use for this request (only) the indicated channel priority. |
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577 Requires KDmaRequestChannelPriority to be set in iFlags as well. |
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578 @see TDmaPriority |
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579 */ |
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580 TUint iChannelPriority; |
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581 /** Info word passed to the PSL */ |
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582 TUint iPslRequestInfo; |
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583 |
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584 /** Structure contents delta vector (usage tbd) */ |
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585 TUint32 iDelta; |
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586 /** Reserved for future use */ |
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587 TUint32 iReserved1; |
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588 |
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589 private: |
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590 /** Private constructor. Initializes fields with the values passed in by |
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591 the legacy version of the DDmaRequest::Fragment() call. |
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592 */ |
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593 TDmaTransferArgs(TUint32 aSrcAddr, TUint32 aDstAddr, TInt aCount, |
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594 TUint aFlags, TUint32 aPslInfo); |
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595 /** Stores the PSL cookie returned by TDmaChannel::PslId() at request |
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596 fragmentation time. |
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597 The value PslId() is often (but not necessarily) identical with the |
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598 client's TDmaChannel::SCreateInfo::iCookie, which gets passed by the |
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599 PIL into DmaChannelMgr::Open() as 'aOpenId'. |
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600 */ |
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601 TUint32 iChannelCookie; |
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602 /** Reserved for future use */ |
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603 TUint32 iReserved2; |
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604 }; |
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605 |
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606 |
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607 /** DMAC capabilities info structure. |
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608 |
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609 Instances are to be filled in by the PSL and then linked to via TDmaChannel |
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610 objects after they have been opened. |
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611 |
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612 The contents may vary even between channels on the same DMAC (but will |
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613 remain constant for a given channel for the duration that it is open), |
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614 depending on static or dynamic factors which only the PSL knows about. |
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615 |
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616 @see TDmaChannel::Open |
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617 @see TDmaChannel::DmacCaps |
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618 */ |
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619 struct SDmacCaps |
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620 { |
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621 /** DMAC supports n + 1 different channel priorities. */ |
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622 TUint iChannelPriorities; |
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623 /** DMAC supports the pausing and resuming of channels. */ |
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624 TBool iChannelPauseAndResume; |
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625 /** DMA addresses must be aligned on an element size boundary. */ |
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626 TBool iAddrAlignedToElementSize; |
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627 /** DMAC supports 1D (element) index addressing in hardware. */ |
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628 TBool i1DIndexAddressing; |
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629 /** DMAC supports 2D (frame) index addressing in hardware. */ |
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630 TBool i2DIndexAddressing; |
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631 /** DMAC supports these transfer synchronization types (bitmap of values). |
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632 |
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633 @see TDmaTransferSyncFlags |
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634 */ |
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635 TUint iSynchronizationTypes; |
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636 /** DMAC supports burst transactions with these sizes (bitmap of values). |
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637 |
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638 @see TDmaBurstSize |
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639 */ |
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640 TUint iBurstTransactions; |
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641 /** DMAC supports a 'h/w descriptor complete' interrupt. */ |
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642 TBool iDescriptorInterrupt; |
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643 /** DMAC supports a 'frame transfer complete' interrupt. */ |
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644 TBool iFrameInterrupt; |
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645 /** DMAC supports a 'linked-list pause event' interrupt. */ |
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646 TBool iLinkedListPausedInterrupt; |
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647 /** DMAC supports endianness conversion. */ |
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648 TBool iEndiannessConversion; |
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649 /** DMAC supports these graphics operations (bitmap of values). |
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650 |
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651 @see TDmaGraphicsOps |
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652 */ |
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653 TUint iGraphicsOps; |
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654 /** DMAC supports repeated transfers (loops). */ |
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655 TBool iRepeatingTransfers; |
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656 /** DMAC supports logical channel linking (chaining). */ |
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657 TBool iChannelLinking; |
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658 /** DMAC supports scatter/gather mode (linked list items). */ |
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659 TBool iHwDescriptors; |
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660 /** DMAC supports asymmetric source and destination transfer |
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661 parameters (such as element size). |
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662 */ |
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663 TBool iSrcDstAsymmetry; |
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664 /** DMAC supports asymmetric h/w descriptor lists. |
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665 |
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666 ETrue here requires ETrue for iHwDescriptors and iSrcDstAsymmetry as |
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667 well. |
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668 */ |
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669 TBool iAsymHwDescriptors; |
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670 /** DMAC with asymmetric descriptor support has the limitation that the |
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671 number of bytes transferred in source and destination must be equal in |
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672 every link segment (i.e. in each src/dst descriptor pair). |
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673 |
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674 ETrue here requires ETrue for iAsymHwDescriptors as well. |
|
675 */ |
|
676 TBool iBalancedAsymSegments; |
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677 /** DMAC supports separate transfer completion notifications for source and |
|
678 destination side subtransfers. |
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679 |
|
680 This capability is required for the asymmetric transfer completion |
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681 callback API feature. |
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682 |
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683 @see TDmaPILFlags::KDmaAsymCompletionCallback |
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684 */ |
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685 TBool iAsymCompletionInterrupt; |
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686 /** DMAC supports separate descriptor completion notifications for source and |
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687 destination side. |
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688 |
|
689 This capability is required for the asymmetric descriptor completion |
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690 callback API feature. |
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691 |
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692 ETrue here requires ETrue for both iDescriptorInterrupt and |
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693 iAsymHwDescriptors as well. |
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694 |
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695 @see TDmaPILFlags::KDmaAsymDescriptorCallback |
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696 */ |
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697 TBool iAsymDescriptorInterrupt; |
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698 /** DMAC supports separate frame completion notifications for source and |
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699 destination side. |
|
700 |
|
701 This capability is required for the asymmetric frame completion |
|
702 callback API feature. |
|
703 |
|
704 ETrue here requires ETrue for iFrameInterrupt as well. |
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705 |
|
706 @see TDmaPILFlags::KDmaAsymFrameCallback |
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707 */ |
|
708 TBool iAsymFrameInterrupt; |
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709 |
|
710 /** Reserved for future use */ |
|
711 TUint32 iReserved[5]; |
|
712 }; |
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713 |
|
714 |
|
715 struct TDmaV2TestInfo |
|
716 { |
|
717 enum {KMaxChannels=32}; |
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718 /** Maximum transfer size in bytes for all channels (ie. the minimum of all channels' maximum size)*/ |
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719 TUint iMaxTransferSize; |
|
720 /** 3->Memory buffers must be 4-byte aligned, 7->8-byte aligned, ... */ |
|
721 TUint iMemAlignMask; |
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722 /** Cookie to pass to DDmaRequest::Fragment for memory-memory transfer */ |
|
723 TUint32 iMemMemPslInfo; |
|
724 /** Number of test single-buffer channels */ |
|
725 TInt iMaxSbChannels; |
|
726 /** Pointer to array containing single-buffer test channel ids */ |
|
727 TUint32 iSbChannels[KMaxChannels]; |
|
728 /** Number of test double-buffer channels */ |
|
729 TInt iMaxDbChannels; |
|
730 /** Pointer to array containing double-buffer test channel ids */ |
|
731 TUint32 iDbChannels[KMaxChannels]; |
|
732 /** Number of test scatter-gather channels */ |
|
733 TInt iMaxSgChannels; |
|
734 /** Pointer to array containing scatter-gather test channel ids */ |
|
735 TUint32 iSgChannels[KMaxChannels]; |
|
736 }; |
|
737 |
|
738 |
|
739 #endif // #ifndef __DMADEFS_H__ |