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299 * On SMP, only the running core is maintained. |
299 * On SMP, only the running core is maintained. |
300 */ |
300 */ |
301 static void CleanAndInvalidate_DCache_All(); |
301 static void CleanAndInvalidate_DCache_All(); |
302 |
302 |
303 /* |
303 /* |
304 * Synchronises a single line of cache(s) for instruction execution. |
304 * Synchronises the ICache and DCache for instruction execution. |
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305 * Also invalidates the branch predictor array, this is architecture dependant: |
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306 * ARM7: Invalidates aAddr and aAddr+2 (covering possible THUMB instructions) |
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307 * ARM6: Invalidates the whole Branch Predictor Array |
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308 * |
305 * On SMP, only the running core is maintained. |
309 * On SMP, only the running core is maintained. |
306 * |
310 * |
307 * @arg aAddr Virtual address that belongs to the cache line. |
311 * @arg aAddr 32bit aligned virtual address that belongs to the cache line. |
308 * |
312 * |
309 * NOTE: On SMP this is guaranted NOT to broadcast to other cores. |
313 * NOTE: On SMP this is guaranteed NOT to broadcast to other cores. |
310 * NOTE: It assumes the same line size for ICache and DCache |
314 * NOTE: It assumes the same line size for ICache and DCache |
311 */ |
315 */ |
312 static void IMB_CacheLine(TLinAddr aAddr); |
316 static void IMB_CacheLine(TLinAddr aAddr); |
313 |
317 |
314 private: |
318 private: |