220 r=(*f)(a2); |
220 r=(*f)(a2); |
221 break; |
221 break; |
222 } |
222 } |
223 case RShadow::EControlAllocPhys: |
223 case RShadow::EControlAllocPhys: |
224 { |
224 { |
|
225 |
225 TInt size=(TInt)a1; |
226 TInt size=(TInt)a1; |
226 TInt align=(TInt)a2; |
227 TInt align=(TInt)a2; |
227 TPhysAddr pa; |
228 TPhysAddr pa; |
|
229 |
|
230 NKern::ThreadEnterCS(); |
228 r=Epoc::AllocPhysicalRam(size,pa,align); |
231 r=Epoc::AllocPhysicalRam(size,pa,align); |
|
232 NKern::ThreadLeaveCS(); |
|
233 |
229 if (r==KErrNone) |
234 if (r==KErrNone) |
230 { |
235 { |
231 if (pa&0x0f) |
236 if (pa&0x0f) |
232 r=KErrCorrupt; |
237 r=KErrCorrupt; |
233 else |
238 else |
234 r=pa>>4; |
239 r=pa>>4; |
235 } |
240 } |
|
241 |
236 break; |
242 break; |
237 } |
243 } |
238 case RShadow::EControlFreePhys: |
244 case RShadow::EControlFreePhys: |
239 { |
245 { |
|
246 |
240 TPhysAddr pa=(TPhysAddr)a1; |
247 TPhysAddr pa=(TPhysAddr)a1; |
241 TInt size=(TInt)a2; |
248 TInt size=(TInt)a2; |
|
249 NKern::ThreadEnterCS(); |
242 r=Epoc::FreePhysicalRam(pa,size); |
250 r=Epoc::FreePhysicalRam(pa,size); |
|
251 NKern::ThreadLeaveCS(); |
243 break; |
252 break; |
244 } |
253 } |
245 case RShadow::EControlClaimPhys: |
254 case RShadow::EControlClaimPhys: |
246 { |
255 { |
|
256 |
247 TPhysAddr pa=(TPhysAddr)a1; |
257 TPhysAddr pa=(TPhysAddr)a1; |
248 TInt size=(TInt)a2; |
258 TInt size=(TInt)a2; |
|
259 NKern::ThreadEnterCS(); |
249 r=Epoc::ClaimPhysicalRam(pa,size); |
260 r=Epoc::ClaimPhysicalRam(pa,size); |
|
261 NKern::ThreadLeaveCS(); |
250 break; |
262 break; |
251 } |
263 } |
252 |
264 |
253 // GetMemoryArchitecture |
265 // GetMemoryArchitecture |
254 case RShadow::EControlGetMemoryArchitecture: |
266 case RShadow::EControlGetMemoryArchitecture: |