1 // Copyright (c) 2009 Nokia Corporation and/or its subsidiary(-ies). |
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2 // All rights reserved. |
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3 // This component and the accompanying materials are made available |
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4 // under the terms of the License "Eclipse Public License v1.0" |
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5 // which accompanies this distribution, and is available |
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6 // at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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7 // |
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8 // Initial Contributors: |
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9 // Nokia Corporation - initial contribution. |
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10 // |
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11 // Contributors: |
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12 // |
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13 // Description: |
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14 // This is a test for the PCI driver, so far implemented only on the |
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15 // Naviengine platform. It aims to test: |
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16 // -That known values of data in config and memory space, on a given |
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17 // device can be read as expected. |
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18 // -That data can be written and modified in config and memory space |
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19 // -PCI memory buffers mapped or allocated by the PCI driver work as |
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20 // expected. These are |
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21 // -DChunk created by PCI driver and accessible from PCI |
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22 // -DPlatHwChunk created by PCI driver and accessible from PCI |
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23 // -DChunk created externally, then mapped in to PCI memory space |
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24 // There are tests to: |
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25 // - Create and close each buffer. Heap checking ensures proper |
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26 // cleanup |
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27 // - Create and close multiple buffers from multiple threads. |
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28 // This is an SMP focused test to check that the implementation |
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29 // of the chunk manager and allocator in the driver are thread |
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30 // safe. The tests should pass without triggering any assertions in |
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31 // the driver's invariance checks. |
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32 // - Write to buffers from software, and read back via the |
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33 // system to PCI window, and vice-versa -- a loop-back test. |
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34 // This checks that PCI buffers are indeed accessible to PCI devices. |
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35 // |
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36 // The tests require several pieces of PSL specific information: |
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37 // - A TPciDevice containing the vendor and device IDs of a PCI device |
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38 // to use for testing. |
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39 // - TAddrSpaceTests which identify regions of a device's config and |
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40 // memory space with known values, or which are known to be writable. |
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41 // |
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42 // The test driver grants access to the PCI API with the following |
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43 // constructs: |
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44 // - TUserConfigSpace and TUserMemorySpace, derived from TUserPciSpace, |
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45 // which are user side equivalents of kernel-side objects allowing |
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46 // accesses of different sizes to a PCI device's config space or |
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47 // memory space. |
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48 // - RPciChunk which is derived from and RChunk and corresponds to |
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49 // a kernel-side DChunk, which in turn corresponds to a PCI chunk or |
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50 // buffer. The test driver uses these for all PCI chunk types (a |
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51 // "wrapper" DChunk is used to map the memory of a PCI DPlatHwChunk |
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52 // to user side). |
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53 // |
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54 // Known Issues: |
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55 // The test driver d_pci is intended to be platform independent but |
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56 // for now still contains some PSL specific information .eg the test |
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57 // info structure (which should really be passed up from the PSL) and |
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58 // the address and size of the system to pci window. For now the |
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59 // test driver code will remain in the Naviengine baseport directory. |
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60 // If the PCI driver is ever ported to a new platform this can be |
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61 // rectified. |
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62 // |
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63 // |
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64 // |
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65 #include "../misc/test_thread.h" |
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66 #include <e32std.h> |
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67 #define __E32TEST_EXTENSION__ |
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68 #include <e32test.h> |
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69 #include "t_pci.h" |
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70 #include <assp/naviengine/pci.h> |
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71 |
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72 class RPci; |
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73 /** |
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74 Extends RChunk to hold the PCI address |
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75 associated with a chunk. |
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76 */ |
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77 class RPciChunk: public RChunk |
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78 { |
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79 public: |
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80 TUint PciBase() |
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81 { |
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82 return iPciBaseAddr; |
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83 } |
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84 |
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85 /** |
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86 Return the PCI accessible size |
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87 */ |
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88 TInt Size() const |
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89 { |
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90 return iPciSize; |
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91 } |
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92 |
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93 private: |
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94 friend class RPci; |
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95 TUint iPciBaseAddr; |
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96 TInt iPciSize; //size of the region mapped into PCI |
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97 }; |
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98 |
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99 typedef TInt (RPci::*ChunkOpenFn)(RPciChunk&, TInt, TRequestStatus*); |
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100 |
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101 class RPci : public RBusLogicalChannel |
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102 { |
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103 public: |
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104 TInt Open(); |
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105 TInt GetTestInfo(TPciTestInfo& aTestInfo); |
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106 |
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107 TInt Open(const TPciDevice&); |
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108 |
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109 TUint AccessConfigSpace(const TUserConfigSpace& aCs); |
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110 TUint AccessMemorySpace(const TUserMemorySpace& aMs); |
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111 TInt OpenPciDChunk(RPciChunk& aPciChunk,TInt aPciChunkSize, TRequestStatus* aStatus=0); |
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112 TInt OpenPciPlatHwChunk(RPciChunk& aPciHwChunk,TInt aPciChunkSize, TRequestStatus* aStatus=0); |
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113 TInt OpenPciMappedChunk(RPciChunk& aPciMappedChunk,TInt aPciChunkSize, TRequestStatus* aStatus=0); |
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114 TInt OpenPciWindowChunk(RChunk& aPciWindowChunk); |
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115 TInt RunUnitTests(); |
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116 private: |
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117 TInt DoOpenPciChunk(RPciChunk& aPciChunk, TInt aPciChunkSize, TPciTestCmd aCmd, TRequestStatus* aStatus); |
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118 }; |
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119 |
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120 inline TInt RPci::Open() |
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121 { |
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122 return DoCreate(KPciLddFactory, TVersion(), KNullUnit, NULL, NULL); |
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123 } |
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124 |
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125 inline TInt RPci::Open(const TPciDevice& aDevice) |
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126 { |
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127 TPckgC<TPciDevice> devicePkg(aDevice); |
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128 return DoCreate(KPciLddFactory, TVersion(), KNullUnit, NULL, &devicePkg); |
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129 } |
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130 |
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131 inline TInt RPci::GetTestInfo(TPciTestInfo& aTestInfo) |
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132 { |
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133 TPckg<TPciTestInfo> info(aTestInfo); |
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134 return DoControl(EGetTestInfo, &info); |
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135 } |
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136 |
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137 inline TInt RPci::RunUnitTests() |
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138 { |
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139 return DoControl(ERunUnitTests); |
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140 } |
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141 |
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142 TUint RPci::AccessConfigSpace(const TUserConfigSpace& aCs) |
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143 { |
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144 TPckgC<TUserConfigSpace> pkg(aCs); |
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145 return DoControl(EAccessConfigSpace, &pkg); |
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146 } |
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147 |
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148 TUint RPci::AccessMemorySpace(const TUserMemorySpace& aMs) |
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149 { |
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150 TPckgC<TUserMemorySpace> pkg(aMs); |
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151 return DoControl(EAccessMemorySpace, &pkg); |
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152 } |
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153 |
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154 TInt RPci::OpenPciDChunk(RPciChunk& aPciChunk,TInt aPciChunkSize, TRequestStatus* aStatus) |
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155 { |
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156 return DoOpenPciChunk(aPciChunk, aPciChunkSize, EOpenPciDChunk, aStatus); |
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157 } |
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158 |
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159 TInt RPci::OpenPciPlatHwChunk(RPciChunk& aPciHwChunk,TInt aPciChunkSize, TRequestStatus* aStatus) |
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160 { |
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161 return DoOpenPciChunk(aPciHwChunk, aPciChunkSize, EOpenPciPlatHwChunk, aStatus); |
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162 } |
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163 |
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164 TInt RPci::OpenPciMappedChunk(RPciChunk& aPciMappedChunk,TInt aPciChunkSize, TRequestStatus* aStatus) |
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165 { |
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166 return DoOpenPciChunk(aPciMappedChunk, aPciChunkSize, EOpenPciMappedChunk, aStatus); |
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167 } |
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168 |
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169 TInt RPci::OpenPciWindowChunk(RChunk& aPciWindowChunk) |
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170 { |
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171 TUint chunkHandle = DoControl(EOpenPciWindowChunk); |
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172 return aPciWindowChunk.SetReturnedHandle(chunkHandle); |
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173 } |
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174 |
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175 TInt RPci::DoOpenPciChunk(RPciChunk& aPciChunk, TInt aPciChunkSize, TPciTestCmd aCmd, TRequestStatus* aStatus) |
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176 { |
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177 const TInt constPciChunkSize = aPciChunkSize; |
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178 TPciChunkCreateInfo info(constPciChunkSize, aPciChunk.iPciBaseAddr, aStatus); |
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179 TPckgC<TPciChunkCreateInfo> pkg(info); |
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180 |
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181 TUint chunkHandle = DoControl(aCmd, &pkg); |
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182 |
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183 const TInt r = aPciChunk.SetReturnedHandle(chunkHandle); |
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184 if(r == KErrNone) |
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185 { |
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186 aPciChunk.iPciSize = constPciChunkSize; |
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187 } |
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188 return r; |
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189 } |
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190 |
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191 TUserPciSpace::TUserPciSpace(RPci& aPci) |
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192 :iPci(&aPci) |
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193 {} |
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194 |
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195 TUserConfigSpace::TUserConfigSpace(RPci& aPci) |
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196 :TUserPciSpace(aPci) |
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197 {} |
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198 |
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199 TUint TUserConfigSpace::Call() |
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200 { |
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201 return iPci->AccessConfigSpace(*this); |
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202 } |
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203 |
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204 TUserPciSpace* TUserConfigSpace::Clone() const |
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205 { |
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206 return new TUserConfigSpace(*this); |
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207 } |
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208 |
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209 TUserMemorySpace::TUserMemorySpace(RPci& aPci, TInt aBarIndex) |
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210 :TUserPciSpace(aPci), iBarIndex(aBarIndex) |
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211 {} |
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212 |
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213 TUint TUserMemorySpace::Call() |
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214 { |
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215 return iPci->AccessMemorySpace(*this); |
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216 } |
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217 |
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218 TUserPciSpace* TUserMemorySpace::Clone() const |
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219 { |
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220 return new TUserMemorySpace(*this); |
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221 } |
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222 |
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223 /** |
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224 Test address allocator |
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225 */ |
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226 TInt TestRunPciUnitTest(RPci& pci) |
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227 { |
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228 return pci.RunUnitTests(); |
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229 } |
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230 |
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231 |
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232 /** |
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233 Read from a defined address in memory or config space, compare against expected values. |
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234 8,16, and 32 bit accesses performed. |
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235 |
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236 @param aSpace Object gving access to either the config or memory space of a PCI device |
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237 @param aInfo Contains the address and expected value of a dword |
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238 */ |
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239 void TestReadAddressSpace(TUserPciSpace& aSpace, const TPciTestInfo::TAddrSpaceTest& aInfo, RTest& test, TBool aVerbose=EFalse) |
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240 { |
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241 const TUint os = aInfo.iOffset; |
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242 //Iterate over different widths, and possible |
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243 //subfields of 32 bit word |
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244 for(TInt bitWidth=32; bitWidth>=8; bitWidth>>=1) |
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245 { |
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246 const TInt numberOfFields = (32/bitWidth); |
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247 for(TInt i=0; i< numberOfFields; i++) |
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248 { |
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249 const TInt extraByteOffset = i * (bitWidth >> 3); |
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250 const TInt byteOffset = os + extraByteOffset; |
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251 if(aVerbose) |
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252 test.Printf(_L("Access bitWidth=%d byte offset=%d\n"), bitWidth, byteOffset); |
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253 |
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254 const TUint expected = aInfo.Expected(bitWidth, byteOffset); |
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255 const TUint read = aSpace.Read(bitWidth, byteOffset); |
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256 if(aVerbose) |
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257 test.Printf(_L("expect 0x%08x, read 0x%08x\n"), expected, read); |
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258 test_Equal(expected, read); |
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259 } |
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260 } |
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261 } |
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262 |
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263 /** |
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264 Verify writes and modifications to a defined address in memory or config space. 8,16, and 32 bit |
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265 accesses performed. |
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266 |
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267 @param aSpace Object gving access to either the config or memory space of a PCI device |
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268 @param aInfo Contains the address of a (at least partially) writable dword |
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269 */ |
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270 void TestWriteAddressSpace(TUserPciSpace& aSpace, TPciTestInfo::TAddrSpaceTest& aInfo, RTest& test, TBool aVerbose=EFalse) |
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271 { |
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272 const TUint original = aSpace.Read(32, aInfo.iOffset); |
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273 const TUint os = aInfo.iOffset; |
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274 TUint mask = ~aInfo.iReadOnlyMask; |
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275 |
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276 //The pattern will be truncated when used with bit widths |
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277 //less than 32. |
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278 const TUint initPattern = 0xFFFFFFFF; |
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279 |
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280 for(TInt bitWidth=32; bitWidth>=8; bitWidth>>=1) |
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281 { |
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282 const TUint pattern = initPattern >> (32-bitWidth); |
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283 const TInt numberOfFields = (32/bitWidth); |
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284 for(TInt i=0; i< numberOfFields; i++) |
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285 { |
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286 const TInt extraByteOffset = i * (bitWidth >> 3); |
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287 const TInt byteOffset = os + extraByteOffset; |
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288 if(aVerbose) |
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289 test.Printf(_L("Access bitWidth=%d byte offset=%d\n"), bitWidth, byteOffset); |
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290 //the full dword we expect |
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291 //currently assume that the unwritable bits will be 0 |
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292 const TUint writeExpect = (pattern << (bitWidth * i) ) & mask; |
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293 const TUint clearExpect = 0; |
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294 |
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295 //do write followed by clear |
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296 const TUint expect[] = {writeExpect, clearExpect}; |
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297 const TUint write[] = {pattern, 0}; |
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298 for(TInt n = 0; n < 2; n++) |
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299 { |
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300 aSpace.Write(bitWidth, byteOffset, write[n]); |
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301 TUint result = aSpace.Read(32, os); |
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302 |
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303 if(aVerbose) |
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304 test.Printf(_L("wrote 0x%08x, expect 0x%08x, read 0x%08x\n"), |
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305 write[n], expect[n], result); |
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306 test_Equal(expect[n], result); |
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307 } |
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308 |
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309 //test Modify calls. Set then clear pattern |
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310 TUint set[] = {pattern, 0}; |
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311 TUint clear[] = {0, pattern}; |
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312 |
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313 for(TInt m = 0; m < 2; m++) |
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314 { |
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315 aSpace.Modify(bitWidth, byteOffset, clear[m], set[m]); |
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316 TUint result = aSpace.Read(32, os); |
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317 |
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318 if(aVerbose) |
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319 test.Printf(_L("clear 0x%08x, set 0x%08x, expect 0x%08x, read 0x%08x\n"), clear[m], set[m], expect[m], result); |
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320 test_Equal(expect[m], result); |
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321 } |
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322 } |
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323 } |
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324 |
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325 //restore orginal value or we will not be able to access device |
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326 aSpace.Write(32, os, original); |
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327 } |
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328 |
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329 |
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330 /** |
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331 Verify that a PCI DChunk can be opened and closed from user side |
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332 |
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333 @param pci The RPci object to use |
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334 @param test The RTest object to use |
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335 @param aPciChunkSize The size of the DChunk which would be created |
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336 */ |
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337 void TestOpenAndCloseDChunk(RPci& pci,RTest& test,TInt aPciChunkSize) |
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338 { |
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339 RPciChunk testPciDChunk; |
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340 |
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341 // Create and open Chunk |
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342 TRequestStatus status; |
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343 TInt r = pci.OpenPciDChunk(testPciDChunk,aPciChunkSize, &status); |
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344 test_KErrNone(r); |
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345 |
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346 test(testPciDChunk.IsWritable()); |
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347 test(testPciDChunk.IsReadable()); |
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348 |
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349 test.Printf(_L("PCI Chunk base = 0x%08x\n"), testPciDChunk.Base()); |
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350 test.Printf(_L("PCI Chunk size = %d\n"), testPciDChunk.Size()); |
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351 test.Printf(_L("PCI Address = 0x%08x\n"), testPciDChunk.PciBase()); |
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352 |
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353 //Close Chunk |
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354 test.Next(_L("Close PCI Chunk handle")); |
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355 |
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356 RTest::CloseHandleAndWaitForDestruction(testPciDChunk); |
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357 User::WaitForRequest(status); |
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358 } |
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359 |
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360 /** |
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361 Verify that a PCI PlatHwChunk can be opened and closed from user side |
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362 |
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363 |
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364 @param pci The RPci object to use |
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365 @param test The RTest object to use |
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366 @param aPciChunkSize The size of the PlatHwChunk which would be created |
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367 */ |
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368 void TestOpenAndClosePciPlatHwChunk(RPci& pci,RTest& test,TInt aPciChunkSize) |
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369 { |
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370 RPciChunk testPciPlatHwChunk; |
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371 |
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372 // Create and open Chunk |
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373 TRequestStatus status; |
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374 TInt r = pci.OpenPciPlatHwChunk(testPciPlatHwChunk,aPciChunkSize, &status); |
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375 test_KErrNone(r); |
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376 |
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377 test(testPciPlatHwChunk.IsWritable()); |
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378 test(testPciPlatHwChunk.IsReadable()); |
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379 |
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380 test.Printf(_L("PCI Chunk base = 0x%08x\n"), testPciPlatHwChunk.Base()); |
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381 test.Printf(_L("PCI Chunk size = %d\n"), testPciPlatHwChunk.Size()); |
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382 test.Printf(_L("PCI Address = 0x%08x\n"), testPciPlatHwChunk.PciBase()); |
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383 |
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384 //Close Chunk |
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385 testPciPlatHwChunk.Close(); |
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386 User::WaitForRequest(status); |
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387 test.Next(_L("Closed PCI PlatHwChunk handle")); |
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388 } |
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389 |
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390 /** |
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391 Verify that pci-mapped DChunk can be opended and closed form user side |
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392 |
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393 @param pci The RPci object to use |
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394 @param test The RTest object to use |
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395 @param aPciChunkSize The size of the pci-mapped DChunk which would be created |
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396 */ |
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397 void TestPciMapppedChunk(RPci& pci,RTest& test,TInt aPciChunkSize) |
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398 { |
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399 RPciChunk testPciMappedChunk; |
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400 |
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401 // Create and open Chunk |
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402 TRequestStatus status; |
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403 TInt r = pci.OpenPciMappedChunk(testPciMappedChunk,aPciChunkSize, &status); |
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404 test_KErrNone(r); |
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405 |
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406 test(testPciMappedChunk.IsWritable()); |
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407 test(testPciMappedChunk.IsReadable()); |
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408 |
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409 test.Printf(_L("PCI Chunk base = 0x%08x\n"), testPciMappedChunk.Base()); |
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410 test.Printf(_L("PCI Chunk size = %d\n"), testPciMappedChunk.Size()); |
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411 test.Printf(_L("PCI Address = 0x%08x\n"), testPciMappedChunk.PciBase()); |
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412 |
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413 //Close Chunk |
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414 testPciMappedChunk.Close(); |
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415 User::WaitForRequest(status); |
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416 test.Next(_L("Closed PCI Mapped Chunk handle")); |
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417 } |
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418 |
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419 /** |
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420 Verify that an RChunk can be open to grant access to the internal PCI window from the user side |
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421 |
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422 @param pci The RPci object to use |
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423 @param test The RTest object to use |
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424 */ |
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425 void TestPciWindowChunk(RPci& pci,RTest& test) |
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426 { |
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427 RChunk testPciWindowChunk; |
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428 |
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429 // Create and open DChunk |
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430 TInt r = pci.OpenPciWindowChunk(testPciWindowChunk); |
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431 test_KErrNone(r); |
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432 |
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433 test(testPciWindowChunk.IsWritable()); |
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434 test(testPciWindowChunk.IsReadable()); |
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435 |
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436 test.Printf(_L("PCI Window Chunk base = 0x%08x\n"), testPciWindowChunk.Base()); |
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437 test.Printf(_L("PCI Window Chunk size = %d\n"), testPciWindowChunk.Size()); |
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438 |
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439 //Close Chunk |
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440 testPciWindowChunk.Close(); |
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441 test.Next(_L("Closed PCI Window Chunk handle")); |
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442 } |
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443 |
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444 |
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445 class CPciTest : public CTest |
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446 { |
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447 protected: |
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448 CPciTest(const TDesC& aName, TInt aIterations, RPci& aDevice) |
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449 : CTest(aName, aIterations), iDevice(aDevice) |
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450 {} |
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451 |
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452 RPci iDevice; |
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453 }; |
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454 |
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455 /** |
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456 Each instance of test will open a chunk, using the function specified in |
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457 the template argument, FUNC. |
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458 |
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459 The total number of chunks that can be opened by all instances is limited |
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460 by iMaxCount. |
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461 |
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462 All intances of the test will hold their chunk open until iMaxCount has |
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463 been reached. |
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464 */ |
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465 template<ChunkOpenFn FUNC> |
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466 class CPciOpenChunkTest : public CPciTest |
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467 { |
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468 public: |
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469 CPciOpenChunkTest(const TDesC& aName, TInt aIterations, RPci& aDevice, |
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470 RSemaphore aSemOpen, RSemaphore aSemClose, RFastLock aLock, TInt aMaxCount) |
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471 :CPciTest(aName, aIterations, aDevice), |
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472 iSemOpen(aSemOpen), iSemClose(aSemClose), iLock(aLock), iMaxCount(aMaxCount) |
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473 { |
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474 } |
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475 |
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476 virtual void RunTest() |
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477 { |
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478 RTest test(iName); |
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479 RPciChunk chunk; |
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480 |
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481 iSemOpen.Wait(); |
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482 TRequestStatus status; |
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483 const TInt chunkSize = 0x400; |
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484 //open chunk by calling FUNC |
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485 TInt r = ((iDevice).*(FUNC))(chunk, chunkSize, &status); |
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486 test_KErrNone(r); |
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487 |
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488 iLock.Wait(); |
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489 iOpenCount++; |
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490 test.Printf(_L("Opened chunk %d\n"), iOpenCount); |
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491 if(iOpenCount == iMaxCount) |
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492 { |
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493 test.Printf(_L("Opened=%d, max=%d: Allow chunks to close\n"), iOpenCount, iMaxCount); |
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494 //release all waiting threads |
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495 //plus 1 preincrement so this |
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496 //thread also passes |
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497 iSemClose.Signal(iOpenCount); |
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498 iOpenCount = 0; |
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499 } |
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500 iLock.Signal(); |
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501 |
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502 |
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503 iSemClose.Wait(); |
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504 chunk.Close(); |
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505 User::WaitForRequest(status); |
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506 |
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507 // permit another chunk to be opened |
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508 iSemOpen.Signal(); |
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509 test.Close(); |
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510 } |
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511 |
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512 virtual CTest* Clone() const |
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513 { |
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514 //make shallow copy |
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515 return new CPciOpenChunkTest(*this); |
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516 } |
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517 |
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518 |
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519 private: |
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520 RSemaphore& iSemOpen; ///!< Represents the number of available PCI mappings |
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521 RSemaphore& iSemClose; ///!< Represents the number of threads waiting to close their chunk |
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522 RFastLock& iLock; |
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523 static TInt iOpenCount; |
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524 const TInt iMaxCount; |
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525 }; |
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526 |
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527 template<ChunkOpenFn FUNC> |
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528 TInt CPciOpenChunkTest<FUNC>::iOpenCount = 0; |
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529 |
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530 |
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531 /** |
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532 Test which will perform various reads from a PCI address |
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533 space (config or memory) and confirm that values are read |
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534 as expected |
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535 */ |
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536 class CPciAddressSpaceRead : public CPciTest |
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537 { |
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538 public: |
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539 CPciAddressSpaceRead(const TDesC& aName, TInt aIterations, RPci& aDevice, |
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540 const TUserPciSpace& aSpace, const TPciTestInfo::TAddrSpaceTest& aInfo) |
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541 :CPciTest(aName, aIterations, aDevice), |
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542 iAddressSpace(aSpace.Clone()), iSpaceTestInfo(aInfo) |
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543 { |
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544 } |
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545 |
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546 CPciAddressSpaceRead(const CPciAddressSpaceRead& aOther) |
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547 :CPciTest(aOther)/* TODO-REVIEW have object-sliced aOther - is this ok?*/, |
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548 iAddressSpace(aOther.iAddressSpace->Clone()), iSpaceTestInfo(aOther.iSpaceTestInfo) |
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549 { |
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550 } |
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551 |
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552 virtual ~CPciAddressSpaceRead() |
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553 { |
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554 delete iAddressSpace; |
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555 } |
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556 |
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557 virtual void RunTest() |
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558 { |
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559 __UHEAP_MARK; |
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560 RTest test(iName); |
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561 TestReadAddressSpace(*iAddressSpace, iSpaceTestInfo, test); |
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562 test.Close(); |
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563 __UHEAP_MARKEND; |
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564 } |
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565 |
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566 virtual CTest* Clone() const |
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567 { |
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568 //make shallow copy |
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569 return new CPciAddressSpaceRead(*this); |
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570 } |
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571 |
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572 private: |
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573 TUserPciSpace* iAddressSpace; |
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574 const TPciTestInfo::TAddrSpaceTest& iSpaceTestInfo; |
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575 }; |
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576 |
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577 /** |
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578 For aBuffer, test writing to it then reading back from aWindow |
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579 then write via window and read back from chunk |
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580 |
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581 @param test The RTest object to use |
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582 @param aBuffer RChunk corresponding to a PCI accessible buffer |
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583 @param aWindow RChunk coressponding an appropriate System-to-PCI memory window |
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584 It is presumed to start at PCI address 0 |
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585 */ |
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586 void DoLoopBackTest(RTest& test, RPciChunk aBuffer, RChunk aWindow) |
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587 { |
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588 test.Start(_L("Test accessing memory via PCI")); |
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589 |
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590 TUint8* const bufferBase = aBuffer.Base(); |
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591 const TUint bufferSize = aBuffer.Size(); |
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592 const TUint bufferPciBase = aBuffer.PciBase(); |
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593 |
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594 TUint8* const windowBase = aWindow.Base(); |
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595 const TUint windowSize = aWindow.Size(); |
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596 |
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597 #define PRINT(N) RDebug::Printf("%s = 0x%08x (%d)", #N, (N), (N)) |
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598 PRINT(bufferBase); |
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599 PRINT(bufferSize); |
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600 PRINT(bufferPciBase); |
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601 |
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602 PRINT(windowBase); |
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603 PRINT(windowSize); |
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604 |
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605 #undef PRINT |
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606 |
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607 //need to check that the end of the buffer |
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608 //is within the windowed region |
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609 test(bufferPciBase + bufferSize <= windowSize); |
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610 TUint8* const bufferBaseWithinWindow = windowBase + bufferPciBase; |
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611 |
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612 test.Next(_L("write chunk")); |
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613 for(TUint i = 0; i < bufferSize; ++i) |
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614 { |
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615 //each byte will hold its own offset modulo 256 |
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616 bufferBase[i] = (TUint8)i; |
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617 } |
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618 |
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619 test.Next(_L("read back via window")); |
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620 for(TUint j=0; j < bufferSize; ++j) |
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621 { |
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622 const TUint8 result = bufferBaseWithinWindow[j]; |
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623 test_Equal(j%256, result); |
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624 } |
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625 |
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626 //clear chunk |
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627 memclr(bufferBase, bufferSize); |
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628 test.Next(_L("write via window")); |
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629 for(TUint k=0; k < bufferSize; ++k) |
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630 { |
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631 //each byte will hold its own offset modulo 256 |
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632 bufferBaseWithinWindow[k] = (TUint8)k; |
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633 } |
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634 |
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635 test.Next(_L("read back from chunk")); |
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636 for(TUint l=0; l < bufferSize; ++l) |
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637 { |
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638 const TUint8 result = bufferBase[l]; |
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639 test_Equal(l%256, result); |
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640 } |
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641 |
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642 test.End(); |
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643 } |
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644 |
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645 /** |
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646 Take care of opening a chunk, running the test and closing |
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647 */ |
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648 template<ChunkOpenFn OPEN_FUNC> |
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649 inline void LoopBackTest(RPci& aPci, RTest& test, RChunk& aWindow) |
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650 { |
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651 RPciChunk pciChunk; |
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652 const TInt chunkSize = 0x400; //1k |
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653 |
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654 //call the specified chunk opening function |
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655 TRequestStatus status; |
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656 TInt r = ((aPci).*(OPEN_FUNC))(pciChunk, chunkSize, &status); |
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657 test_KErrNone(r); |
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658 DoLoopBackTest(test, pciChunk, aWindow); |
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659 pciChunk.Close(); |
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660 User::WaitForRequest(status); |
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661 } |
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662 |
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663 /** |
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664 Run the loopback test for the 3 types of buffer supported by the PCI driver. |
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665 DChunk |
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666 DPlatChunk |
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667 Mapped In external memory |
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668 */ |
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669 void TestLoopBack(RPci& aPci, RTest& test) |
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670 { |
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671 test.Next(_L("Open PCI window")); |
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672 RChunk window; |
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673 |
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674 TInt r = aPci.OpenPciWindowChunk(window); |
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675 test_KErrNone(r); |
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676 |
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677 test.Next(_L("DChunk")); |
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678 LoopBackTest<&RPci::OpenPciDChunk>(aPci, test, window); |
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679 |
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680 test.Next(_L("DPlatHwChunk")); |
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681 LoopBackTest<&RPci::OpenPciPlatHwChunk>(aPci, test, window); |
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682 |
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683 test.Next(_L("DChunk (mapped in)")); |
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684 LoopBackTest<&RPci::OpenPciMappedChunk>(aPci, test, window); |
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685 |
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686 window.Close(); |
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687 } |
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688 #ifndef __VC32__ //visual studio 6 doesn't approve of pointer to member function template parameters |
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689 /** |
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690 Run the CPciOpenChunkTest for each type of chunk. This function also creates (and destroys) the |
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691 necessary semaphores and locks. |
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692 CPciOpenChunkTest objects are run in multiple threads using MultipleTestRun(). |
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693 |
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694 @param aDevice Handle to the test driver |
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695 @param test RTest to use. |
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696 @param aBufferLimit The maximum number of buffers which can be opened simultaneously |
|
697 */ |
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698 void TestBufferOpenConcurrency(RPci& aDevice, RTest& test, TInt aBufferLimit) |
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699 { |
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700 RSemaphore semaphoreOpen; |
|
701 RSemaphore semaphoreClose; |
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702 RFastLock lock; |
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703 |
|
704 TInt r = semaphoreOpen.CreateLocal(aBufferLimit); |
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705 test_KErrNone(r); |
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706 |
|
707 r = semaphoreClose.CreateLocal(0); |
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708 test_KErrNone(r); |
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709 |
|
710 r = lock.CreateLocal(); |
|
711 test_KErrNone(r); |
|
712 |
|
713 const TInt iterations = 3; |
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714 { |
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715 test.Printf(_L("Opening %d PCI DChunks in %d threads\n"), aBufferLimit, aBufferLimit); |
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716 CPciOpenChunkTest<&RPci::OpenPciDChunk> |
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717 dChunkTest(_L("Concurrent-DChunk"), iterations, aDevice, semaphoreOpen, semaphoreClose, lock, aBufferLimit); |
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718 |
|
719 MultipleTestRun(test, dChunkTest, aBufferLimit); |
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720 } |
|
721 |
|
722 { |
|
723 test.Printf(_L("Opening %d PCI DPlatHwChunks in %d threads\n"), aBufferLimit, aBufferLimit); |
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724 CPciOpenChunkTest<&RPci::OpenPciPlatHwChunk> |
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725 platChunkTest(_L("Concurrent-DPlatHwChunk"), iterations, aDevice, semaphoreOpen, semaphoreClose, lock, aBufferLimit); |
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726 |
|
727 MultipleTestRun(test, platChunkTest, aBufferLimit); |
|
728 } |
|
729 |
|
730 { |
|
731 test.Printf(_L("Opening %d PCI Mapped chunks in %d threads\n"), aBufferLimit, aBufferLimit); |
|
732 CPciOpenChunkTest<&RPci::OpenPciMappedChunk> |
|
733 mappedChunkTest(_L("Concurrent-DChunk(mapped)"), iterations, aDevice, semaphoreOpen, semaphoreClose, lock, aBufferLimit); |
|
734 |
|
735 MultipleTestRun(test, mappedChunkTest, aBufferLimit); |
|
736 } |
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737 |
|
738 semaphoreOpen.Close(); |
|
739 semaphoreClose.Close(); |
|
740 lock.Close(); |
|
741 } |
|
742 #endif |
|
743 |
|
744 TInt E32Main() |
|
745 { |
|
746 __UHEAP_MARK; |
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747 |
|
748 _LIT(KPci, "PCI"); |
|
749 RTest test(KPci); |
|
750 test.Start(_L("Running PCI tests\n")); |
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751 |
|
752 TInt r = User::LoadLogicalDevice(KPciLdd); |
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753 |
|
754 __KHEAP_MARK; |
|
755 |
|
756 if(r==KErrNotFound) |
|
757 { |
|
758 test.Printf(_L("No PCI system present - skipping test\n")); |
|
759 return KErrNone; |
|
760 } |
|
761 if(r!=KErrNone && r!=KErrAlreadyExists) |
|
762 { |
|
763 test_KErrNone(r); |
|
764 } |
|
765 |
|
766 test.Next(_L("Open non-existant device\n")); |
|
767 RPci device; |
|
768 TPciDevice unavailable; |
|
769 r = device.Open(unavailable); |
|
770 test_Equal(KErrNotFound, r); |
|
771 |
|
772 RPci pciInfo; |
|
773 r = pciInfo.Open(); |
|
774 test_KErrNone(r); |
|
775 |
|
776 test.Next(_L("Get test info from driver\n")); |
|
777 TPciTestInfo info; |
|
778 r = pciInfo.GetTestInfo(info); |
|
779 test_KErrNone(r); |
|
780 pciInfo.Close(); |
|
781 |
|
782 test.Next(_L("Open test device\n")); |
|
783 r = device.Open(info.iDevice); |
|
784 test_KErrNone(r); |
|
785 |
|
786 test.Next(_L("Run Device Unit Test\n")); |
|
787 r=TestRunPciUnitTest(device); |
|
788 test_KErrNone(r); |
|
789 |
|
790 test.Next(_L("Read config space\n")); |
|
791 TUserConfigSpace cs(device); |
|
792 TestReadAddressSpace(cs, info.iCfgSpaceRead, test); |
|
793 |
|
794 test.Next(_L("Write config space\n")); |
|
795 TestWriteAddressSpace(cs, info.iCfgSpaceWrite, test); |
|
796 |
|
797 test.Next(_L("Read memory space\n")); |
|
798 TUserMemorySpace ms(device, info.iMemSpaceIndex); |
|
799 TestReadAddressSpace(ms, info.iMemSpaceRead, test); |
|
800 |
|
801 test.Next(_L("Modify memory space\n")); |
|
802 TestWriteAddressSpace(ms, info.iMemSpaceWrite, test); |
|
803 |
|
804 { |
|
805 const TInt addrSpaceThreadCount = 4; |
|
806 const TInt iterations = 100; |
|
807 test.Next(_L("Concurrent config space reads")); |
|
808 CPciAddressSpaceRead cfgSpaceRead(_L("Cfg Space Read"), iterations, device, cs, info.iCfgSpaceRead); |
|
809 MultipleTestRun(test, cfgSpaceRead, addrSpaceThreadCount); |
|
810 |
|
811 test.Next(_L("Concurrent memory space reads")); |
|
812 CPciAddressSpaceRead memSpaceRead(_L("Memory Space Read"), iterations, device, ms, info.iMemSpaceRead); |
|
813 MultipleTestRun(test, memSpaceRead, addrSpaceThreadCount); |
|
814 } |
|
815 |
|
816 TInt testDChunkSize = 0x4000; |
|
817 test.Next(_L("Open and Close DChunks\n")); |
|
818 TestOpenAndCloseDChunk(device,test,testDChunkSize); |
|
819 |
|
820 TInt testDPlatChunkSize = 0x2000; |
|
821 test.Next(_L("Open and Close PlatHwChunks\n")); |
|
822 TestOpenAndClosePciPlatHwChunk(device,test,testDPlatChunkSize); |
|
823 |
|
824 //TestPciMapppedChunk() fails for sizes greater than 4K. |
|
825 //The issue is that a block of externally mapped memory must be |
|
826 //naturally alligned in order to be accessible to the PCI bus (ie |
|
827 //an 8k buffer would have to start at an address which is a |
|
828 //multiple of 8k. |
|
829 // |
|
830 //Now we could fix this for sure on the kernel side, by making |
|
831 //sure we only commit correctly aligned memory into the chunk (as |
|
832 //the pci driver itself does), |
|
833 //However, by using a 4k chunk, we know this will be on a page |
|
834 //boundary so the alignment is correct (assuming the page size |
|
835 //isn't changed). |
|
836 TInt testMapppedChunkSize = 0x1000; |
|
837 test.Next(_L("Open and Close Pci Mappped Chunk\n")); |
|
838 TestPciMapppedChunk(device,test,testMapppedChunkSize); |
|
839 |
|
840 test.Next(_L("Open and Close Pci Window Chunk\n")); |
|
841 TestPciWindowChunk(device,test); |
|
842 |
|
843 const TInt numberOfThreads = info.iNumberOfBars; |
|
844 test.Printf(_L("Open buffers concurrently, max supported = %d\n"), numberOfThreads); |
|
845 #ifndef __VC32__ |
|
846 TestBufferOpenConcurrency(device, test, numberOfThreads); |
|
847 #else |
|
848 test.Printf(_L("TestBufferOpenConcurrency not implemented for WINS"), numberOfThreads); |
|
849 #endif |
|
850 |
|
851 test.Next(_L("Test loop back")); |
|
852 TestLoopBack(device, test); |
|
853 |
|
854 device.Close(); |
|
855 __KHEAP_MARKEND; |
|
856 |
|
857 r = User::FreeLogicalDevice(KPciLdd); |
|
858 test_KErrNone(r); |
|
859 |
|
860 test.End(); |
|
861 test.Close(); |
|
862 |
|
863 __UHEAP_MARKEND; |
|
864 return KErrNone; |
|
865 } |
|