35 #define __PRI_LIST_MACHINE_CODED__ |
35 #define __PRI_LIST_MACHINE_CODED__ |
36 #define __FAST_SEM_MACHINE_CODED__ |
36 #define __FAST_SEM_MACHINE_CODED__ |
37 #define __FAST_MUTEX_MACHINE_CODED__ |
37 #define __FAST_MUTEX_MACHINE_CODED__ |
38 #define __NTHREAD_WAITSTATE_MACHINE_CODED__ |
38 #define __NTHREAD_WAITSTATE_MACHINE_CODED__ |
39 |
39 |
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40 class TSubScheduler; |
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41 class TScheduler; |
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42 struct SFullArmRegSet; |
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43 struct ArmScu; |
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44 struct GicDistributor; |
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45 struct GicCpuIfc; |
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46 struct ArmLocalTimer; |
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47 struct ArmGlobalTimer; |
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48 |
40 // TSubScheduler member data |
49 // TSubScheduler member data |
41 #define i_ScuAddr iExtras[4] // Address of SCU (also in TScheduler) |
50 struct TSubSchedulerX |
42 #define i_GicDistAddr iExtras[5] // Address of GIC Distributor (also in TScheduler) |
51 { |
43 #define i_GicCpuIfcAddr iExtras[6] // Address of GIC CPU Interface (also in TScheduler) |
52 TUint32 iSSXP[3]; |
44 #define i_LocalTimerAddr iExtras[7] // Address of local timer registers (also in TScheduler) |
53 ArmGlobalTimer* iGlobalTimerAddr; // Address of global timer registers (also in TScheduler) |
45 #define i_IrqCount iExtras[8] // count of interrupts handled |
54 ArmScu* iScuAddr; // Address of SCU (also in TScheduler) |
46 #define i_IrqNestCount iExtras[9] // IRQ nest count for this CPU (starts at -1) |
55 GicDistributor* iGicDistAddr; // Address of GIC Distributor (also in TScheduler) |
47 #define i_ExcInfo iExtras[10] // pointer to exception info for crash debugger |
56 GicCpuIfc* iGicCpuIfcAddr; // Address of GIC CPU Interface (also in TScheduler) |
48 #define i_CrashState iExtras[11] // 0=normal, 1=this CPU faulted, 2=this CPU has received an NMI and halted |
57 ArmLocalTimer* iLocalTimerAddr; // Address of local timer registers (also in TScheduler) |
49 #define i_AbtStackTop iExtras[12] // Top of ABT stack for this CPU, also used to point to SFullArmRegSet |
58 volatile TUint32 iIrqCount; // count of interrupts handled |
50 #define i_UndStackTop iExtras[13] // Top of UND stack for this CPU |
59 volatile TInt iIrqNestCount; // IRQ nest count for this CPU (starts at -1) |
51 #define i_FiqStackTop iExtras[14] // Top of FIQ stack for this CPU |
60 TAny* iExcInfo; // pointer to exception info for crash debugger |
52 #define i_IrqStackTop iExtras[15] // Top of IRQ stack for this CPU |
61 volatile TInt iCrashState; // 0=normal, 1=this CPU faulted, 2=this CPU has received an NMI and halted |
53 #define i_TimerMultF iExtras[16] // Timer frequency / Max Timer frequency * 2^32 |
62 union { |
54 #define i_TimerMultI iExtras[17] // Max Timer frequency / Timer frequency * 2^24 |
63 TLinAddr iAbtStackTop; // Top of ABT stack for this CPU, also used to point to SFullArmRegSet |
55 #define i_CpuMult iExtras[18] // CPU frequency / Max CPU frequency * 2^32 |
64 SFullArmRegSet* iRegs; |
56 #define i_LastTimerSet iExtras[20] // Value last written to local timer counter |
65 }; |
57 #define i_TimestampError iExtras[21] // Current error in the timestamp |
66 TLinAddr iUndStackTop; // Top of UND stack for this CPU |
58 #define i_MaxCorrection iExtras[22] // Maximum correction to timestamp in one go |
67 TLinAddr iFiqStackTop; // Top of FIQ stack for this CPU |
59 #define i_TimerGap iExtras[23] // Timestamp ticks taken to read and write local timer counter |
68 TLinAddr iIrqStackTop; // Top of IRQ stack for this CPU |
60 |
69 volatile TUint32 iCpuFreqM; // CPU frequency / Max CPU frequency (mantissa, bit 31=1) f/fmax=mantissa/2^shift |
61 #define i_Regs iExtras[12] // Alias for i_AbtStackTop |
70 volatile TInt iCpuFreqS; // CPU frequency / Max CPU frequency (shift) |
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71 volatile TUint32 iCpuPeriodM; // Max CPU frequency / CPU frequency (mantissa, bit 31=1) fmax/f=mantissa/2^shift |
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72 volatile TInt iCpuPeriodS; // Max CPU frequency / CPU frequency (shift) |
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73 volatile TUint32 iNTimerFreqM; // Nominal Timer frequency / Max Timer frequency (mantissa, bit 31=1) f/fmax=mantissa/2^shift |
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74 volatile TInt iNTimerFreqS; // Nominal Timer frequency / Max Timer frequency (shift) |
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75 volatile TUint32 iNTimerPeriodM; // Nominal Max Timer frequency / Timer frequency (mantissa, bit 31=1) fmax/f=mantissa/2^shift |
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76 volatile TInt iNTimerPeriodS; // Nominal Max Timer frequency / Timer frequency (shift) |
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77 volatile TUint32 iTimerFreqM; // Timer frequency / Max Timer frequency (mantissa, bit 31=1) f/fmax=mantissa/2^shift |
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78 volatile TInt iTimerFreqS; // Timer frequency / Max Timer frequency (shift) |
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79 volatile TUint32 iTimerPeriodM; // Max Timer frequency / Timer frequency (mantissa, bit 31=1) fmax/f=mantissa/2^shift |
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80 volatile TInt iTimerPeriodS; // Max Timer frequency / Timer frequency (shift) |
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81 volatile TUint64 iLastSyncTime; // Timestamp at which last reference check occurred |
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82 volatile TUint32 iTicksSinceLastSync; // Local timer ticks between last ref. check and next zero crossing |
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83 volatile TUint32 iLastTimerSet; // Value last written to local timer counter |
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84 volatile TUint32 iGapEstimate; // 2^16 * estimated gap in ticks whenever local timer counter is read then written |
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85 volatile TUint32 iGapCount; // count of local timer counter RMW ops |
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86 volatile TUint32 iTotalTicks; // programmed ticks since last sync |
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87 volatile TUint32 iDitherer; // PRNG state for dither generation |
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88 volatile TInt iFreqErrorEstimate; // Current frequency offset between local timer and reference |
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89 volatile TInt iFreqErrorLimit; // Saturation level for frequency offset |
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90 volatile TInt64 iErrorIntegrator; // Accumulator to integrate time error measurements |
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91 volatile TUint64 iRefAtLastCorrection; // Value of reference timer at last correction |
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92 volatile TUint8 iM; // Value controlling loop bandwidth (larger->lower loop bandwidth) |
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93 volatile TUint8 iN; // Number of timer ticks between corrections = 2^iN |
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94 volatile TUint8 iD; // Value controlling loop damping |
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95 volatile TUint8 iSSXP1; |
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96 |
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97 TUint32 iSSXP2[19]; |
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98 TUint64 iSSXP3; // one 64 bit value to guarantee alignment |
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99 }; |
62 |
100 |
63 // TScheduler member data |
101 // TScheduler member data |
64 #define i_TimerMax iExtras[16] // Maximum per-CPU timer frequency (after prescaling) |
102 struct TSchedulerX |
65 |
103 { |
66 |
104 TUint64 iTimerMax; // Maximum per-CPU timer frequency (after prescaling) |
67 #define RESCHED_IPI_VECTOR 0x00 |
105 TUint32 iSXP[1]; |
68 #define GENERIC_IPI_VECTOR 0x01 |
106 ArmGlobalTimer* iGlobalTimerAddr; // Address of global timer registers (also in TSubScheduler) |
69 #define TRANSFERRED_IRQ_VECTOR 0x02 |
107 ArmScu* iScuAddr; // Address of SCU (also in TSubScheduler) |
70 #define CRASH_IPI_VECTOR 0x03 // would really like this to be a FIQ |
108 GicDistributor* iGicDistAddr; // Address of GIC Distributor (also in TSubScheduler) |
71 #define BOOT_IPI_VECTOR 0x04 // used during boot to handshake with APs |
109 GicCpuIfc* iGicCpuIfcAddr; // Address of GIC CPU Interface (also in TSubScheduler) |
72 #define RESERVED_IPI_VECTOR_1 0x05 // reserved for future kernel functionality |
110 ArmLocalTimer* iLocalTimerAddr; // Address of local timer registers (also in TSubScheduler) |
73 #define RESERVED_IPI_VECTOR_2 0x06 // reserved for future kernel functionality |
111 TUint32 iSXP2[8]; |
74 #define RESERVED_IPI_VECTOR_3 0x07 // reserved for future kernel functionality |
112 }; |
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113 |
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114 |
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115 #define RESCHED_IPI_VECTOR 0x00 |
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116 #define GENERIC_IPI_VECTOR 0x01 |
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117 #define TRANSFERRED_IRQ_VECTOR 0x02 |
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118 #define CRASH_IPI_VECTOR 0x03 // would really like this to be a FIQ |
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119 #define BOOT_IPI_VECTOR 0x04 // used during boot to handshake with APs |
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120 #define INDIRECT_POWERDOWN_IPI_VECTOR 0x04 // used to trigger core power down |
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121 #define RESERVED_IPI_VECTOR_1 0x05 // reserved for future kernel functionality |
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122 #define RESERVED_IPI_VECTOR_2 0x06 // reserved for future kernel functionality |
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123 #define IDLE_WAKEUP_IPI_VECTOR 0x07 // for use of Idle handler/Wakeup handler |
75 |
124 |
76 #if defined(__CPU_ARM11MP__) |
125 #if defined(__CPU_ARM11MP__) |
77 #define TIMESLICE_VECTOR 0x1D // vector 29 is per-CPU timer interrupt |
126 #define TIMESLICE_VECTOR 0x1D // vector 29 is per-CPU timer interrupt |
78 // vector 30 is per-CPU Watchdog timer when not in watchdog mode |
127 // vector 30 is per-CPU Watchdog timer when not in watchdog mode |
79 // vector 31 is external nIRQ local interrupt pin |
128 // vector 31 is external nIRQ local interrupt pin |