equal
deleted
inserted
replaced
70 |
70 |
71 |
71 |
72 __NAKED__ TInt ThreadContextHwExc(TAny*) |
72 __NAKED__ TInt ThreadContextHwExc(TAny*) |
73 { |
73 { |
74 asm("stmdb sp!, {r4-r11,lr} "); |
74 asm("stmdb sp!, {r4-r11,lr} "); |
75 asm("mov r1, #0x80000000"); |
75 asm("mov r1, #0x00000000"); |
76 asm("bl SetRegs"); |
76 asm("bl SetRegs"); |
77 asm("ldr r0,[r13, #1]"); // Cause alignment fault |
77 asm("ldr r0,[r0]"); // Cause data abort with null access, SetRegs will have set r0=0 |
78 asm("ThreadContextHwExc_pc:"); |
78 asm("ThreadContextHwExc_pc:"); |
79 asm("mov r0, #0 "); |
79 asm("mov r0, #0 "); |
80 asm("ldmia sp!, {r4-r11,pc} "); |
80 asm("ldmia sp!, {r4-r11,pc} "); |
81 } |
81 } |
82 |
82 |