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1 // Copyright (c) 1998-2009 Nokia Corporation and/or its subsidiary(-ies). |
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2 // All rights reserved. |
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3 // This component and the accompanying materials are made available |
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4 // under the terms of the License "Eclipse Public License v1.0" |
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5 // which accompanies this distribution, and is available |
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6 // at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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7 // |
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8 // Initial Contributors: |
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9 // Nokia Corporation - initial contribution. |
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10 // |
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11 // Contributors: |
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12 // |
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13 // Description: |
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14 // template/template_variant/variant.mmh |
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15 // TO DO: (mandatory) |
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16 // Add here a definition for your CPU (list in CONFIG.INC) |
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17 // |
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18 // |
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19 |
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20 macro __CPU_ARM1176__ |
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21 |
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22 // TO DO: (mandatory) |
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23 // |
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24 // Add here a definition for your Memory Model |
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25 // |
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26 #define MM_MULTIPLE |
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27 |
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28 // TO DO: (mandatory) |
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29 // |
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30 // Macro which generates the names for the binaries for this platform |
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31 // |
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32 #define VariantTarget(name,ext) _template_##name##.##ext |
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33 #define VariantMediaDefIncludePath SYMBIAN_OS_LAYER_PLATFORM_EXPORT_PATH(template) |
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34 |
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35 //Include debug support. Some e32 tests require debug support |
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36 macro __DEBUGGER_SUPPORT__ |
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37 |
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38 // |
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39 // TO DO: |
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40 // |
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41 // If euser is built from the variant, uncomment the following line to build it |
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42 // as ARM rather than Thumb |
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43 // |
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44 // #define __BUILD_VARIANT_EUSER_AS_ARM__ |
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45 |
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46 // TO DO: (optional) |
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47 // |
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48 // To replace some of the generic utility functions with variant specific |
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49 // versions (eg to replace memcpy with a version optimised for the hardware), |
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50 // uncomment the two lines below and edit the files in the replacementUtils |
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51 // directory. |
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52 // |
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53 // #define REPLACE_GENERIC_UTILS |
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54 // #define VariantReplacementUtilsPath template/template_variant/replacement_utils |
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55 |
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56 // TO DO: (optional) |
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57 // |
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58 // Enable BTrace support in release versions of the kernel by adding |
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59 // the following BTRACE macro declarations |
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60 // |
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61 // macro BTRACE_KERNEL_ALL |
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62 |
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63 // TO DO: |
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64 // |
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65 // Uncomment the following line if using the r1p0 release or later of the ARM1136 processor. |
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66 // |
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67 // macro __CPU_ARM1136_IS_R1__ |
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68 |
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69 // TO DO: |
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70 // |
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71 // Include the following line if default memory mapping should use shared memory. |
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72 // Should be on for multicore (SMP) devices. |
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73 // |
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74 // macro __CPU_USE_SHARED_MEMORY |
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75 // |
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76 |
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77 // TO DO: |
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78 // |
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79 // Uncomment the next line if using the ARM1136 processor and ARM1136 Erratum 406973 |
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80 // "CLREX instruction might be ignored during data cache line fill" |
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81 // is fixed on this hardware. |
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82 // |
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83 // macro __CPU_ARM1136_ERRATUM_406973_FIXED |
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84 |
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85 // Uncomment next line if: |
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86 // 1) using the ARM1136 processor and ARM1136 Erratum 408022 "Cancelled write to CONTEXTID register might update ASID" |
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87 // is fixed on this hardware, or |
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88 // 2) using the ARM1176 processor and ARM1176 Erratum 415047 "Cancelled write to CONTEXTID register might update ASID" |
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89 // is fixed on this hardware. |
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90 // |
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91 // macro __CPU_ARM1136_ERRATUM_408022_FIXED |
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92 |
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93 // Uncomment if: |
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94 // 1) using ARM1136 processor and ARM1136 Erratum 411920: "Invalidate Entire Instruction Cache |
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95 // operation might fail to invalidate some lines if coincident with linefill" |
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96 // is fixed on this hardware, or |
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97 // 2) using ARM1176 processor and ARM1176 Erratum 415045: "Invalidate Entire Instruction Cache |
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98 // operation might fail to invalidate some lines if coincident with linefill |
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99 // is fixed on this hardware. |
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100 // Workaround: |
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101 // 1) Disables the use of of prefetch range cache operations by setting RV bit in Auxiliary Ctrl Reg. |
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102 // 2) Replaces Invalidate ICache operation with the sequence defined in the errata document. |
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103 // If this macro is enabled, it should be accompanied by: |
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104 // "GBLL CFG_CPU_ARM1136_ERRATUM_411920_FIXED" in variant.mmh |
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105 // |
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106 // macro __CPU_ARM1136_ERRATUM_411920_FIXED |
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107 |
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108 // Uncomment next line if using the ARM1176 processor and ARM1176 Erratum 720013 "Invalidate Instruction |
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109 // Cache operations can fail" is fixed on this hardware. |
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110 // |
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111 // macro __CPU_ARM1176_ERRATUM_720013_FIXED |
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112 |
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113 // TO DO: |
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114 // |
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115 // Uncomment the next line if using the ARM1136 processor with L210/L220 cache and ARM1136 |
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116 // Erratum 317041:"TTBR0/TTBR1 bits[4:3] do not read back correctly" |
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117 // is fixed on this hardware. |
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118 // |
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119 // macro __CPU_ARM1136_ERRATUM_317041_FIXED |
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120 |
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121 // Uncomment the following line if Page Tables/Dirs have to be updated in main memory. |
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122 // Standard platforms shouldn't have this feature switched on. |
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123 // This must be accompanied by __ARM_L210_CACHE__ or __ARM_L220_CACHE__ macro. |
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124 // Omission:: The solution doesn't update temporary mappings |
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125 // of inter-process communication (IPC) - aka aliasing. |
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126 // |
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127 // macro __FLUSH_PT_INTO_RAM__ |
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128 |
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129 // Uncomment the following line if Symbian OS is running in TrustZone non-secure state and the |
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130 // secure state has prevented code executing in non-secure state from being able to mask FIQs by |
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131 // setting the SCR.FW bit in the secure configuration register. |
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132 // |
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133 // macro __FIQ_RESERVED_FOR_SECURE_STATE__ |
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134 |
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135 // Various PlatSec configuration options cannot be disabled even by clearing the appropriate |
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136 // bits in the kernel configuration flags - they are enforced at compile time. Uncomment the |
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137 // following to allow the clearing of bits in the kernel config flags to disable the relevant |
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138 // options at run time. |
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139 // |
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140 //macro __PLATSEC_UNLOCKED__ |
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141 |
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142 // If this macro is enabled then EMapAttrBufferedNC memory will be remapped as EMapAttrFullyBlocking |
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143 //macro FAULTY_NONSHARED_DEVICE_MEMORY |
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144 |
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145 // Uncomment the following line if L210/20 cache is running in forced-WT mode. |
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146 // (Forced_WT bit set in Debug Control Register of L210/20 cache controller.) |
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147 // macro __ARM_L2_CACHE_WT_MODE |
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148 |
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149 // For the status of errata of L210 & L220 cache, see the header of source file: |
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150 // e32\kernel\arm\cachel2.cpp |
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151 |
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152 #if defined(__USING_USING_ASSP_REGISTER_API__) || defined(__USING_INTERRUPT_API__) || defined(__USING_ASSP_REGISTER_API__) |
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153 library VariantTarget(katemplate,lib) |
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154 #endif |
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155 |
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156 // Uncomment the following if IIC Controller is required |
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157 library iic.lib |
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158 |