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1 // Copyright (c) 1998-2009 Nokia Corporation and/or its subsidiary(-ies). |
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2 // All rights reserved. |
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3 // This component and the accompanying materials are made available |
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4 // under the terms of the License "Eclipse Public License v1.0" |
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5 // which accompanies this distribution, and is available |
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6 // at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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7 // |
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8 // Initial Contributors: |
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9 // Nokia Corporation - initial contribution. |
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10 // |
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11 // Contributors: |
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12 // |
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13 // Description: |
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14 // e32\include\memmodel\epoc\plat_priv.h |
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15 // |
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16 // WARNING: This file contains some APIs which are internal and are subject |
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17 // to change without notice. Such APIs should therefore not be used |
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18 // outside the Kernel and Hardware Services package. |
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19 // |
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20 |
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21 #ifndef __M32KERN_H__ |
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22 #define __M32KERN_H__ |
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23 #include <kernel/kern_priv.h> |
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24 #include <platform.h> |
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25 #include <e32def_private.h> |
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26 |
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27 /** Hardware Variant Discriminator |
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28 |
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29 @internalTechnology |
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30 */ |
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31 class THardwareVariant |
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32 { |
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33 public: |
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34 inline THardwareVariant(); |
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35 inline THardwareVariant(TUint aVariant); |
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36 inline operator TUint(); |
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37 inline TBool IsIndependent(); |
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38 inline TBool IsCpu(); |
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39 inline TBool IsCompatibleWith(TUint aCpu, TUint aAsic, TUint aVMask); |
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40 private: |
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41 inline TUint Layer(); |
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42 inline TUint Parent(); |
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43 inline TUint VMask(); |
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44 private: |
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45 TUint iVariant; |
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46 }; |
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47 |
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48 /** |
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49 @internalTechnology |
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50 */ |
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51 inline THardwareVariant::THardwareVariant() |
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52 {iVariant=0x01000000;} |
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53 |
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54 /** |
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55 @internalTechnology |
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56 */ |
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57 inline THardwareVariant::THardwareVariant(TUint aVariant) |
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58 {iVariant=aVariant;} |
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59 |
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60 /** |
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61 @internalTechnology |
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62 */ |
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63 inline THardwareVariant::operator TUint() |
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64 {return iVariant;} |
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65 |
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66 /** |
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67 @internalTechnology |
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68 */ |
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69 inline TUint THardwareVariant::Layer() |
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70 {return iVariant>>24;} |
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71 |
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72 /** |
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73 @internalTechnology |
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74 */ |
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75 inline TUint THardwareVariant::Parent() |
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76 {return (iVariant>>16)&0xff;} |
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77 |
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78 /** |
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79 @internalTechnology |
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80 */ |
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81 inline TUint THardwareVariant::VMask() |
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82 {return iVariant&0xffff;} |
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83 |
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84 /** |
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85 @internalTechnology |
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86 */ |
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87 inline TBool THardwareVariant::IsIndependent() |
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88 {return (Layer()<=3);} |
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89 |
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90 /** |
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91 @internalTechnology |
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92 */ |
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93 inline TBool THardwareVariant::IsCpu() |
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94 {return (Parent()==3);} |
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95 |
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96 /** |
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97 @internalTechnology |
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98 */ |
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99 inline TBool THardwareVariant::IsCompatibleWith(TUint aCpu, TUint aAsic, TUint aVMask) |
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100 { return(Layer()<=3 || (Parent()==3 && Layer()==aCpu) || |
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101 (Layer()==aAsic && (VMask() & aVMask)!=0) );} |
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102 |
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103 |
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104 /** Functions/Data defined in layer 2 or below of the kernel and not available to layer 1. |
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105 |
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106 @internalComponent |
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107 */ |
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108 class PP |
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109 { |
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110 public: |
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111 enum TPlatPanic |
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112 { |
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113 EInitialSystemTimeInvalid=0, |
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114 EInvalidStartupReason=1, |
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115 EIncorrectDllDataAddress=2, |
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116 ENoDllDataChunk=3, |
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117 EUnsupportedOldBinary=4, |
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118 }; |
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119 |
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120 static void Panic(TPlatPanic aPanic); |
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121 static void InitSuperPageFromRom(TLinAddr aRomHeader, TLinAddr aSuperPage); |
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122 public: |
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123 static TInt RamDriveMaxSize; |
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124 static TInt RamDriveRange; |
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125 static TUint32 NanoWaitCal; |
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126 static DChunk* TheRamDriveChunk; |
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127 static TLinAddr RamDriveStartAddress; |
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128 static TInt MaxUserThreadStack; |
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129 static TInt UserThreadStackGuard; |
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130 static TInt MaxStackSpacePerProcess; |
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131 static TInt SupervisorThreadStackGuard; |
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132 static TUint32 MonitorEntryPoint[3]; |
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133 static TLinAddr RomRootDirAddress; |
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134 public: |
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135 }; |
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136 |
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137 extern "C" { |
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138 extern TLinAddr RomHeaderAddress; |
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139 } |
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140 |
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141 /******************************************** |
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142 * Code segment |
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143 ********************************************/ |
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144 |
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145 /** |
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146 @internalComponent |
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147 */ |
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148 struct SRamCodeInfo |
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149 { |
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150 TInt iCodeSize; |
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151 TInt iTextSize; |
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152 TLinAddr iCodeRunAddr; |
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153 TLinAddr iCodeLoadAddr; |
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154 TInt iDataSize; |
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155 TInt iBssSize; |
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156 TLinAddr iDataRunAddr; |
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157 TLinAddr iDataLoadAddr; |
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158 TInt iConstOffset; // not used |
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159 TLinAddr iExportDir; |
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160 TInt iExportDirCount; |
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161 TLinAddr iExceptionDescriptor; |
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162 }; |
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163 |
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164 |
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165 class DEpocCodeSeg; |
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166 |
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167 /** |
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168 @internalComponent |
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169 */ |
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170 class DEpocCodeSegMemory : public DBase |
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171 { |
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172 public: |
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173 static DEpocCodeSegMemory* New(DEpocCodeSeg* aCodeSeg); |
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174 TInt Open(); |
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175 TInt Close(); |
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176 protected: |
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177 DEpocCodeSegMemory(DEpocCodeSeg* aCodeSeg); |
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178 public: |
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179 TInt iAccessCount; |
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180 SRamCodeInfo iRamInfo; |
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181 DEpocCodeSeg* iCodeSeg; |
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182 }; |
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183 |
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184 |
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185 /** |
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186 @internalComponent |
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187 */ |
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188 class DEpocCodeSeg : public DCodeSeg |
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189 { |
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190 public: |
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191 virtual ~DEpocCodeSeg(); |
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192 void Destruct(); |
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193 public: |
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194 virtual void Info(TCodeSegCreateInfo& aInfo); |
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195 virtual TLibraryFunction Lookup(TInt aOrdinal); |
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196 virtual TInt GetMemoryInfo(TModuleMemoryInfo& aInfo, DProcess* aProcess); |
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197 virtual TInt DoCreate(TCodeSegCreateInfo& aInfo, DProcess* aProcess); |
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198 virtual void InitData(); |
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199 virtual TInt Loaded(TCodeSegCreateInfo& aInfo); |
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200 virtual TInt DoCreateRam(TCodeSegCreateInfo& aInfo, DProcess* aProcess)=0; |
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201 virtual TInt DoCreateXIP(DProcess* aProcess)=0; |
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202 public: |
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203 inline SRamCodeInfo& RamInfo() |
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204 {return *(SRamCodeInfo*)iInfo;} |
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205 inline const TRomImageHeader& RomInfo() |
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206 {return *(const TRomImageHeader*)iInfo;} |
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207 void GetDataSizeAndBase(TInt& aTotalDataSizeOut, TLinAddr& aDataBaseOut); |
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208 public: |
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209 TUint8 iXIP; // TRUE for XIP ROM code |
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210 const TAny* iInfo; // pointer to TRomImageHeader or SRamCodeInfo |
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211 DEpocCodeSegMemory* iMemory; |
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212 TCodeSegLoaderCookieList* iLoaderCookie; |
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213 }; |
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214 |
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215 /******************************************** |
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216 * Process control block |
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217 ********************************************/ |
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218 |
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219 /** |
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220 @internalComponent |
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221 */ |
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222 class DEpocProcess : public DProcess |
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223 { |
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224 public: |
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225 virtual TInt AttachExistingCodeSeg(TProcessCreateInfo& aInfo); |
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226 }; |
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227 |
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228 /** |
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229 @internalComponent |
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230 */ |
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231 inline const TRomHeader& TheRomHeader() |
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232 {return *((const TRomHeader *)RomHeaderAddress);} |
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233 |
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234 #endif |