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1 // Copyright (c) 1998-2009 Nokia Corporation and/or its subsidiary(-ies). |
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2 // All rights reserved. |
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3 // This component and the accompanying materials are made available |
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4 // under the terms of the License "Eclipse Public License v1.0" |
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5 // which accompanies this distribution, and is available |
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6 // at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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7 // |
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8 // Initial Contributors: |
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9 // Nokia Corporation - initial contribution. |
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10 // |
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11 // Contributors: |
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12 // |
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13 // Description: |
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14 // e32\include\nkern\nk_cpu.h |
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15 // |
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16 // WARNING: This file contains some APIs which are internal and are subject |
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17 // to change without notice. Such APIs should therefore not be used |
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18 // outside the Kernel and Hardware Services package. |
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19 // |
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20 |
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21 /** |
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22 @file |
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23 @publishedPartner |
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24 @released |
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25 */ |
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26 |
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27 #ifndef __NK_CPU_H__ |
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28 #define __NK_CPU_H__ |
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29 |
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30 #include <cpudefs.h> |
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31 |
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32 #ifdef __CPU_ARM |
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33 #if defined(__CPU_GENERIC_ARM4__) |
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34 // no cache no MMU |
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35 #define __CPU_ARM_ABORT_MODEL_RESTORED |
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36 #endif |
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37 |
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38 #if defined(__CPU_ARM710T__) || defined(__CPU_ARM720T__) |
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39 #define __CPU_HAS_MMU |
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40 #define __CPU_HAS_CACHE |
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41 #define __CPU_ARM_ABORT_MODEL_UPDATED |
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42 #define __CPU_WRITE_BUFFER |
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43 #endif |
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44 |
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45 #ifdef __CPU_SA1__ |
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46 #define __CPU_HAS_MMU |
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47 #define __CPU_HAS_CACHE |
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48 #define __CPU_ARM_ABORT_MODEL_RESTORED |
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49 #define __CPU_SPLIT_CACHE |
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50 #define __CPU_SPLIT_TLB |
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51 #define __CPU_WRITE_BUFFER |
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52 #define __CPU_HAS_ALT_D_CACHE |
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53 #define __CPU_WRITE_BACK_CACHE |
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54 #define __CPU_CACHE_FLUSH_BY_DATA_READ |
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55 #define __CPU_HAS_SINGLE_ENTRY_DCACHE_FLUSH |
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56 #endif |
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57 |
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58 #if defined(__CPU_ARM920T__) || defined(__CPU_ARM925T__) || defined(__CPU_ARM926J__) |
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59 #define __CPU_HAS_MMU |
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60 #define __CPU_HAS_CACHE |
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61 #define __CPU_ARM_ABORT_MODEL_RESTORED |
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62 #define __CPU_SPLIT_CACHE |
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63 #define __CPU_SPLIT_TLB |
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64 #define __CPU_WRITE_BUFFER |
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65 #define __CPU_WRITE_BACK_CACHE |
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66 #define __CPU_CACHE_FLUSH_BY_WAY_SET_INDEX |
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67 #define __CPU_CACHE_POLICY_IN_PTE |
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68 #define __CPU_HAS_CACHE_TYPE_REGISTER |
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69 #define __CPU_HAS_SINGLE_ENTRY_ITLB_FLUSH |
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70 #define __CPU_HAS_SINGLE_ENTRY_ICACHE_FLUSH |
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71 #define __CPU_HAS_SINGLE_ENTRY_DCACHE_FLUSH |
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72 #endif |
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73 |
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74 #ifdef __CPU_XSCALE__ |
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75 #define __CPU_HAS_MMU |
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76 #define __CPU_HAS_CACHE |
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77 #define __CPU_ARM_ABORT_MODEL_RESTORED |
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78 #define __CPU_SPLIT_CACHE |
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79 #define __CPU_SPLIT_TLB |
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80 #define __CPU_WRITE_BUFFER |
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81 #ifndef __CPU_XSCALE_MANZANO__ |
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82 #define __CPU_HAS_ALT_D_CACHE |
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83 #endif |
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84 #define __CPU_WRITE_BACK_CACHE |
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85 #define __CPU_CACHE_WRITE_ALLOCATE |
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86 #ifdef __CPU_XSCALE_MANZANO__ |
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87 #define __CPU_CACHE_FLUSH_BY_WAY_SET_INDEX |
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88 #else |
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89 #define __CPU_CACHE_FLUSH_BY_LINE_ALLOC |
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90 #endif |
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91 #define __CPU_CACHE_POLICY_IN_PTE |
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92 #define __CPU_HAS_CACHE_TYPE_REGISTER |
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93 #define __CPU_HAS_SINGLE_ENTRY_ITLB_FLUSH |
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94 #define __CPU_HAS_SINGLE_ENTRY_ICACHE_FLUSH |
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95 #define __CPU_HAS_SINGLE_ENTRY_DCACHE_FLUSH |
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96 #define __CPU_HAS_BTB |
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97 #define __CPU_USE_MMU_TEX_FIELD |
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98 #define __CPU_HAS_COPROCESSOR_ACCESS_REG |
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99 #define __CPU_HAS_ACTLR |
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100 #endif |
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101 |
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102 #if defined(__CPU_ARM1136__) || defined(__CPU_ARM11MP__) || defined(__CPU_ARM1176__) || defined(__CPU_CORTEX_A8__) || defined(__CPU_CORTEX_A9__) |
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103 #define __CPU_HAS_MMU |
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104 #define __CPU_HAS_CACHE |
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105 #define __CPU_CACHE_PHYSICAL_TAG |
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106 #define __CPU_SUPPORTS_FAST_PROCESS_SWITCH |
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107 #define __CPU_ARM_ABORT_MODEL_RESTORED |
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108 #define __CPU_SPLIT_CACHE |
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109 |
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110 #if defined(__CPU_CORTEX_A9__) || defined(__CPU_CORTEX_A8__) || defined(__CPU_ARM1136__) |
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111 #define __CPU_SPLIT_TLB |
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112 #endif |
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113 |
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114 #if defined(__CPU_CORTEX_A8__) |
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115 /* Internal cache controller maintains both inner & outer caches. |
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116 * @internalComponent |
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117 */ |
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118 #define __CPU_OUTER_CACHE_IS_INTERNAL_CACHE |
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119 #endif |
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120 |
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121 |
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122 |
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123 #if defined(__CPU_CORTEX_A9__) || defined(__CPU_ARM11MP__) |
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124 #define __CPU_SUPPORTS_TLBIMVAA |
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125 #endif |
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126 |
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127 #if defined(__CPU_CORTEX_A9__) |
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128 #ifdef __SMP__ |
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129 // #define __CPU_SUPPORTS_PAGE_TABLE_WALK_TO_L1_CACHE |
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130 #endif |
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131 #endif |
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132 |
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133 #if (defined(__CPU_ARM1136__) && defined(__CPU_ARM1136_ERRATUM_399234_FIXED)) || (defined(__CPU_ARM11MP__) && defined (__SMP__) ) |
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134 // Page tables on these platforms are either uncached or write through cached. |
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135 #else |
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136 // Page/directory tables are fully cached (write-back) on these platforms. |
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137 #define __CPU_PAGE_TABLES_FULLY_CACHED |
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138 #endif |
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139 |
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140 #define __CPU_WRITE_BUFFER |
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141 #define __CPU_WRITE_BACK_CACHE |
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142 #define __CPU_CACHE_WRITE_ALLOCATE |
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143 #define __CPU_CACHE_FLUSH_BY_WAY_SET_INDEX |
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144 #define __CPU_CACHE_POLICY_IN_PTE |
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145 #define __CPU_HAS_CACHE_TYPE_REGISTER |
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146 #define __CPU_HAS_SINGLE_ENTRY_ITLB_FLUSH |
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147 #define __CPU_HAS_SINGLE_ENTRY_ICACHE_FLUSH |
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148 #define __CPU_HAS_SINGLE_ENTRY_DCACHE_FLUSH |
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149 #define __CPU_HAS_BTB |
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150 #define __CPU_HAS_COPROCESSOR_ACCESS_REG |
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151 #define __CPU_HAS_PREFETCH_BUFFER |
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152 #define __CPU_HAS_ACTLR |
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153 #define __CPU_HAS_TTBR1 |
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154 |
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155 #if !defined(__CPU_ARM1136__) |
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156 #define __CPU_MEMORY_TYPE_REMAPPING |
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157 #endif |
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158 |
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159 #if defined(__CPU_ARM11MP__) && defined(__SMP__) |
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160 #define __BROADCAST_CACHE_MAINTENANCE__ |
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161 #endif |
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162 |
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163 #if defined(__CPU_ARM11MP__) || defined(__CPU_ARM1176__) |
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164 #define __CPU_NEEDS_BTAC_FLUSH_AFTER_ASID_CHANGE |
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165 #endif |
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166 |
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167 #define __CPU_CACHE_HAS_COLOUR |
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168 #define __CPU_I_CACHE_HAS_COLOUR |
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169 |
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170 #if defined(__CPU_ARM1136__) || defined(__CPU_ARM1176__) |
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171 #define __CPU_D_CACHE_HAS_COLOUR |
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172 #elif defined(__CPU_ARM11MP__) |
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173 // MPCore has physically indexed D cache, so no colour problems |
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174 #else |
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175 // Assume other ARM cores have virtually indexed D cache with broken alias avoidence hardware... |
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176 #define __CPU_D_CACHE_HAS_COLOUR |
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177 #endif |
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178 |
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179 |
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180 #endif |
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181 |
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182 |
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183 #ifdef __FIQ_RESERVED_FOR_SECURE_STATE__ |
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184 #define __FIQ_IS_UNCONTROLLED__ |
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185 #endif |
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186 |
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187 #if defined(__CPU_MEMORY_TYPE_REMAPPING) || defined(__MEMMODEL_FLEXIBLE__) |
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188 #define __MMU_USE_SYMMETRIC_ACCESS_PERMISSIONS |
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189 #endif |
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190 |
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191 |
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192 #if defined(__CPU_ARM1136__) && !defined(__CPU_ARM1136_ERRATUM_353494_FIXED) && defined(__MMU_USE_SYMMETRIC_ACCESS_PERMISSIONS) |
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193 #define ERRATUM_353494_MODE_CHANGE(cc,r) FLUSH_BTB(cc,r) |
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194 #else |
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195 #define ERRATUM_353494_MODE_CHANGE(cc,r) |
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196 #endif |
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197 |
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198 #ifdef __CPU_HAS_MMU |
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199 #define __CPU_ARM_USE_DOMAINS |
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200 #endif |
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201 |
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202 #if defined(__ARM_L210_CACHE__) || defined(__ARM_L220_CACHE__)|| defined(__ARM_PL310_CACHE__) |
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203 /** |
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204 Indicates the presense of external cache controller. |
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205 @internalTechnology |
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206 */ |
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207 #define __HAS_EXTERNAL_CACHE__ |
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208 #endif |
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209 |
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210 #ifndef __CPU_HAS_MMU |
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211 #define CPWAIT(cc,r) /**< @internalTechnology */ |
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212 #endif |
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213 |
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214 #include <arm_vfp.h> |
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215 |
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216 // CP15 definitions |
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217 #if defined(__CPU_ARM710T__) || defined(__CPU_ARM720T__) |
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218 #define FLUSH_DCACHE(cc,r) asm("mcr"#cc" p15, 0, "#r", c7, c7, 0 "); /**< @internalTechnology */ |
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219 #define FLUSH_ICACHE(cc,r) asm("mcr"#cc" p15, 0, "#r", c7, c7, 0 "); /**< @internalTechnology */ |
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220 #define FLUSH_IDCACHE(cc,r) asm("mcr"#cc" p15, 0, "#r", c7, c7, 0 "); /**< @internalTechnology */ |
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221 #define FLUSH_DTLB(cc,r) asm("mcr"#cc" p15, 0, "#r", c8, c7, 0 "); /**< @internalTechnology */ |
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222 #define FLUSH_ITLB(cc,r) asm("mcr"#cc" p15, 0, "#r", c8, c7, 0 "); /**< @internalTechnology */ |
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223 #define FLUSH_IDTLB(cc,r) asm("mcr"#cc" p15, 0, "#r", c8, c7, 0 "); /**< @internalTechnology */ |
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224 #define FLUSH_DTLB_ENTRY(cc,addr) asm("mcr"#cc" p15, 0, "#addr", c8, c7, 1 "); /**< @internalTechnology */ |
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225 #define FLUSH_ITLB_ENTRY(cc,addr) asm("mcr"#cc" p15, 0, "#addr", c8, c7, 1 "); /**< @internalTechnology */ |
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226 #define FLUSH_IDTLB_ENTRY(cc,addr) asm("mcr"#cc" p15, 0, "#addr", c8, c7, 1 "); /**< @internalTechnology */ |
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227 #define DRAIN_WRITE_BUFFER(cc,r,rd) // this seems dodgy on Windermere and it works without it |
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228 #define CPWAIT(cc,r) /**< @internalTechnology */ |
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229 |
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230 #elif defined(__CPU_SA1__) |
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231 #define FLUSH_ICACHE(cc,r) asm("mcr"#cc" p15, 0, "#r", c7, c5, 0 "); /**< @internalTechnology */ |
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232 #define PURGE_DCACHE_LINE(cc,r) asm("mcr"#cc" p15, 0, "#r", c7, c6, 1 "); /**< @internalTechnology */ |
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233 #define CLEAN_DCACHE_LINE(cc,r) asm("mcr"#cc" p15, 0, "#r", c7, c10, 1 "); /**< @internalTechnology */ |
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234 #define FLUSH_DCACHE_LINE(cc,r) asm("mcr"#cc" p15, 0, "#r", c7, c10, 1 "); asm("mcr"#cc" p15, 0, "#r", c7, c6, 1 ");/**< @internalTechnology */ |
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235 #define FLUSH_DTLB(cc,r) asm("mcr"#cc" p15, 0, "#r", c8, c6, 0 "); /**< @internalTechnology */ |
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236 #define FLUSH_ITLB(cc,r) asm("mcr"#cc" p15, 0, "#r", c8, c5, 0 "); /**< @internalTechnology */ |
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237 #define FLUSH_IDTLB(cc,r) asm("mcr"#cc" p15, 0, "#r", c8, c7, 0 "); /**< @internalTechnology */ |
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238 #define FLUSH_DTLB_ENTRY(cc,addr) asm("mcr"#cc" p15, 0, "#addr", c8, c6, 1 ");/**< @internalTechnology */ |
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239 #define DRAIN_WRITE_BUFFER(cc,r,rd) asm("mcr"#cc" p15, 0, "#r", c7, c10, 4 "); |
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240 #define CPWAIT(cc,r) /**< @internalTechnology */ |
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241 |
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242 #elif defined(__CPU_ARM920T__) || defined(__CPU_ARM925T__) || defined(__CPU_ARM926J__) |
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243 #define FLUSH_ICACHE(cc,r) asm("mcr"#cc" p15, 0, "#r", c7, c5, 0 "); /**< @internalTechnology */ |
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244 #define FLUSH_ICACHE_LINE(cc,r,tmp) asm("mcr"#cc" p15, 0, "#r", c7, c5, 1 "); /**< @internalTechnology */ |
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245 #define PURGE_DCACHE_LINE(cc,r) asm("mcr"#cc" p15, 0, "#r", c7, c6, 1 "); /**< @internalTechnology */ |
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246 #define CLEAN_DCACHE_LINE(cc,r) asm("mcr"#cc" p15, 0, "#r", c7, c10, 1 "); /**< @internalTechnology */ |
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247 #define CLEAN_DCACHE_INDEX(cc,r) asm("mcr"#cc" p15, 0, "#r", c7, c10, 2 "); /**< @internalTechnology */ |
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248 #define FLUSH_DCACHE_LINE(cc,r) asm("mcr"#cc" p15, 0, "#r", c7, c14, 1 "); /**< @internalTechnology */ |
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249 #define FLUSH_DCACHE_INDEX(cc,r) asm("mcr"#cc" p15, 0, "#r", c7, c14, 2 "); /**< @internalTechnology */ |
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250 #define FLUSH_DTLB(cc,r) asm("mcr"#cc" p15, 0, "#r", c8, c6, 0 "); /**< @internalTechnology */ |
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251 #define FLUSH_ITLB(cc,r) asm("mcr"#cc" p15, 0, "#r", c8, c5, 0 "); /**< @internalTechnology */ |
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252 #define FLUSH_IDTLB(cc,r) asm("mcr"#cc" p15, 0, "#r", c8, c7, 0 "); /**< @internalTechnology */ |
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253 #define FLUSH_DTLB_ENTRY(cc,addr) asm("mcr"#cc" p15, 0, "#addr", c8, c6, 1 ");/**< @internalTechnology */ |
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254 #define FLUSH_ITLB_ENTRY(cc,addr) asm("mcr"#cc" p15, 0, "#addr", c8, c5, 1 ");/**< @internalTechnology */ |
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255 #define DRAIN_WRITE_BUFFER(cc,r,rd) asm("mcr"#cc" p15, 0, "#r", c7, c10, 4 "); |
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256 #define CPWAIT(cc,r) /**< @internalTechnology */ |
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257 #define CACHE_MAINTENANCE_PDE_PTE_UPDATED(r) DRAIN_WRITE_BUFFER(,r,r); |
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258 |
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259 #elif defined(__CPU_XSCALE__) |
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260 //#define FLUSH_ICACHE(cc,r) asm("mcr"#cc" p15, 0, "#r", c7, c5, 0 "); |
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261 #define FLUSH_ICACHE(cc,r) asm("mcr"#cc" p15, 0, "#r", c7, c5, 0; sub"#cc" pc, pc, #4 ");/**< @internalTechnology */ // A step hack |
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262 #define FLUSH_ICACHE_LINE(cc,r,tmp) asm("mcr"#cc" p15, 0, "#r", c7, c5, 1 "); /**< @internalTechnology */ |
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263 #ifdef __CPU_XSCALE_MANZANO__ |
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264 #define PURGE_DCACHE_LINE(cc,r) asm("mcr"#cc" p15, 0, "#r", c7, c6, 1 "); /**< @internalTechnology */ |
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265 #define CLEAN_DCACHE_LINE(cc,r) asm("mcr"#cc" p15, 0, "#r", c7, c10, 1 "); /**< @internalTechnology */ |
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266 #define CLEAN_DCACHE_INDEX(cc,r) asm("mcr"#cc" p15, 0, "#r", c7, c10, 2 "); /**< @internalTechnology */ |
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267 #define FLUSH_DCACHE_LINE(cc,r) asm("mcr"#cc" p15, 0, "#r", c7, c14, 1 "); /**< @internalTechnology */ |
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268 #define FLUSH_DCACHE_INDEX(cc,r) asm("mcr"#cc" p15, 0, "#r", c7, c14, 2 "); /**< @internalTechnology */ |
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269 #else |
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270 #define PURGE_DCACHE_LINE(cc,r) asm("mcr"#cc" p15, 0, "#r", c7, c6, 1 "); asm("nop "); /**< @internalTechnology */ // PXA250 ERRATUM 96 |
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271 #define CLEAN_DCACHE_LINE(cc,r) asm("mcr"#cc" p15, 0, "#r", c7, c10, 1 "); asm("nop ");/**< @internalTechnology */ // PXA250 ERRATUM 96 |
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272 #define FLUSH_DCACHE_LINE(cc,r) asm("mcr"#cc" p15, 0, "#r", c7, c10, 1 "); asm("mcr"#cc" p15, 0, "#r", c7, c6, 1 "); asm("nop "); /**< @internalTechnology */ // PXA250 ERRATUM 96 |
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273 #define ALLOC_DCACHE_LINE(cc,r) asm("mcr"#cc" p15, 0, "#r", c7, c2, 5 "); /**< @internalTechnology */ |
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274 #endif |
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275 #define FLUSH_DTLB(cc,r) asm("mcr"#cc" p15, 0, "#r", c8, c6, 0 "); /**< @internalTechnology */ |
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276 #define FLUSH_ITLB(cc,r) asm("mcr"#cc" p15, 0, "#r", c8, c5, 0 "); /**< @internalTechnology */ |
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277 #define FLUSH_IDTLB(cc,r) asm("mcr"#cc" p15, 0, "#r", c8, c7, 0 "); /**< @internalTechnology */ |
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278 #define FLUSH_DTLB_ENTRY(cc,addr) asm("mcr"#cc" p15, 0, "#addr", c8, c6, 1 "); asm("nop "); asm ("nop "); /**< @internalTechnology */ // PXA250 ERRATUM 21 |
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279 #define FLUSH_ITLB_ENTRY(cc,addr) asm("mcr"#cc" p15, 0, "#addr", c8, c5, 1 "); /**< @internalTechnology */ |
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280 |
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281 #ifdef __CPU_XSCALE_MANZANO__ |
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282 #define DRAIN_WRITE_BUFFER(cc,r,rd) asm("mcr"#cc" p15, 0, "#r", c7, c10, 4 "); |
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283 #else //__CPU_XSCALE_MANZANO__ |
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284 // PXA250 ERRATUM 14 |
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285 #define DRAIN_WRITE_BUFFER(cc,r,rd) asm("mcr"#cc" p15, 0, "#r", c7, c10, 4 "); \ |
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286 asm("ldr"#cc" "#rd", [pc] "); \ |
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287 asm("add pc, pc, #0 "); \ |
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288 asm(".word %a0" : : "i" ((TInt)&SuperPageAddress)); \ |
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289 asm("ldr"#cc" "#rd", ["#rd"] "); \ |
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290 asm("ldr"#cc" "#rd", ["#rd", #%a0]" : : "i" _FOFF(TSuperPage,iUncachedAddress)); \ |
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291 asm("ldr"#cc" "#rd", ["#rd"] "); |
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292 #endif //else __CPU_XSCALE_MANZANO__ |
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293 //#define FLUSH_BTB(cc,r) asm("mcr"#cc" p15, 0, "#r", c7, c5, 6 "); |
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294 #define FLUSH_BTB(cc,r) asm("mcr"#cc" p15, 0, "#r", c7, c5, 6; sub"#cc" pc, pc, #4 "); /**< @internalTechnology */ // A step hack |
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295 #define CPWAIT(cc,r) asm("mrc"#cc" p15, 0, "#r", c2, c0, 0; mov"#cc" "#r","#r"; sub"#cc" pc, pc, #4 "); /**< @internalTechnology */ |
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296 #define GET_CAR(cc,r) asm("mrc"#cc" p15, 0, "#r", c15, c1, 0 "); /**< @internalTechnology */ |
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297 #define SET_CAR(cc,r) asm("mcr"#cc" p15, 0, "#r", c15, c1, 0 "); /**< @internalTechnology */ |
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298 |
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299 #elif defined(__CPU_ARMV6) // end of elif __CPU_XSCALE |
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300 |
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301 #if !defined(__CPU_ARM1136_ERRATUM_411920_FIXED) && (defined(__CPU_ARM1136__) || defined(__CPU_ARM1176__)) |
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302 /** @internalTechnology */ |
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303 #define FLUSH_ICACHE(cc,r,rt) asm("mrs "#rt", cpsr"); \ |
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304 CPSIDAIF; \ |
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305 asm("mcr"#cc" p15, 0, "#r", c7, c5, 0 "); \ |
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306 asm("mcr"#cc" p15, 0, "#r", c7, c5, 0 "); \ |
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307 asm("mcr"#cc" p15, 0, "#r", c7, c5, 0 "); \ |
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308 asm("mcr"#cc" p15, 0, "#r", c7, c5, 0 "); \ |
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309 asm("msr cpsr_c, "#rt); \ |
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310 asm("nop"); \ |
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311 asm("nop"); \ |
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312 asm("nop"); \ |
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313 asm("nop"); \ |
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314 asm("nop"); \ |
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315 asm("nop"); \ |
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316 asm("nop"); \ |
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317 asm("nop"); \ |
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318 asm("nop"); \ |
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319 asm("nop"); \ |
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320 asm("nop"); |
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321 |
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322 #else |
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323 #define FLUSH_ICACHE(cc,r) asm("mcr"#cc" p15, 0, "#r", c7, c5, 0 "); /**< @internalTechnology */ |
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324 #endif // else !(__CPU_ARM1136_ERRATUM_411920_FIXED) && (__CPU_ARM1136__ || __CPU_ARM1176__) |
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325 #if defined(__CPU_ARM1136_ERRATUM_371025_FIXED) || !defined(__CPU_ARM1136__) |
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326 |
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327 #if !defined(__CPU_ARM1176_ERRATUM_720013_FIXED) && defined(__CPU_ARM1176__) |
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328 #define FLUSH_ICACHE_LINE(cc,r,tmp) asm("mcr"#cc" p15, 0, "#r", c7, c5, 1 "); \ |
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329 asm("mcr"#cc" p15, 0, "#r", c7, c5, 1 "); /**< @internalTechnology */ |
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330 #else |
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331 #define FLUSH_ICACHE_LINE(cc,r,tmp) asm("mcr"#cc" p15, 0, "#r", c7, c5, 1 "); /**< @internalTechnology */ |
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332 #endif // !defined(__CPU_ARM1176_ERRATUM_720013_FIXED) && defined(__CPU_ARM1176__) |
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333 |
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334 #else // workaround for erratum 371025 of 1136... |
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335 /** @internalTechnology */ |
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336 #define FLUSH_ICACHE_LINE(cc,r,tmp) asm("orr"#cc" "#tmp", "#r", #0xC0000000 "); \ |
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337 asm("bic"#cc" "#tmp", "#tmp", #1 "); \ |
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338 asm("mcr"#cc" p15, 0, "#tmp", c7, c5, 2 "); \ |
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339 asm("sub"#cc" "#tmp", "#tmp", #0x40000000 "); \ |
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340 asm("mcr"#cc" p15, 0, "#tmp", c7, c5, 2 "); \ |
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341 asm("sub"#cc" "#tmp", "#tmp", #0x40000000 "); \ |
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342 asm("mcr"#cc" p15, 0, "#tmp", c7, c5, 2 "); \ |
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343 asm("sub"#cc" "#tmp", "#tmp", #0x40000000 "); \ |
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344 asm("mcr"#cc" p15, 0, "#tmp", c7, c5, 2 "); |
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345 #endif //else (__CPU_ARM1136_ERRATUM_371025_FIXED) || !(__CPU_ARM1136__) |
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346 |
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347 #if !defined(__CPU_ARM1176_ERRATUM_720013_FIXED) && defined(__CPU_ARM1176__) |
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348 // It is commented out to ensure it is not used on 1176 cores with 720013 erratum |
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349 // #define FLUSH_ICACHE_INDEX(cc,r) asm("mcr"#cc" p15, 0, "#r", c7, c5, 2 "); |
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350 #else |
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351 #define FLUSH_ICACHE_INDEX(cc,r) asm("mcr"#cc" p15, 0, "#r", c7, c5, 2 "); /**< @internalTechnology */ |
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352 #endif //!defined(__CPU_ARM1176_ERRATUM_720013_FIXED) && defined(__CPU_ARM1176__) |
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353 #define PURGE_DCACHE_LINE(cc,r) asm("mcr"#cc" p15, 0, "#r", c7, c6, 1 "); /**< @internalTechnology */ |
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354 #define PURGE_DCACHE_INDEX(cc,r) asm("mcr"#cc" p15, 0, "#r", c7, c6, 2 "); /**< @internalTechnology */ |
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355 #define CLEAN_DCACHE_LINE(cc,r) asm("mcr"#cc" p15, 0, "#r", c7, c10, 1 "); /**< @internalTechnology */ |
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356 |
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357 #define CLEAN_DCACHE_INDEX(cc,r) asm("mcr"#cc" p15, 0, "#r", c7, c10, 2 "); /**< @internalTechnology */ |
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358 #define FLUSH_DCACHE_LINE(cc,r) asm("mcr"#cc" p15, 0, "#r", c7, c14, 1 "); /**< @internalTechnology */ |
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359 #define FLUSH_DCACHE_INDEX(cc,r) asm("mcr"#cc" p15, 0, "#r", c7, c14, 2 "); /**< @internalTechnology */ |
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360 #define FLUSH_ITLB(cc,r) asm("mcr"#cc" p15, 0, "#r", c8, c5, 0 "); /**< @internalTechnology */ |
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361 #define FLUSH_DTLB(cc,r) asm("mcr"#cc" p15, 0, "#r", c8, c6, 0 "); /**< @internalTechnology */ |
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362 #define FLUSH_IDTLB(cc,r) asm("mcr"#cc" p15, 0, "#r", c8, c7, 0 "); /**< @internalTechnology */ |
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363 |
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364 |
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365 // addr must include ASID |
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366 #if defined (__CPU_ARM11MP__) |
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367 #define FLUSH_ITLB_ENTRY(cc,addr) asm("mcr"#cc" p15, 0, "#addr", c8, c5, 3 "); /**< @internalTechnology */ |
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368 #define FLUSH_DTLB_ENTRY(cc,addr) asm("mcr"#cc" p15, 0, "#addr", c8, c6, 3 "); /**< @internalTechnology */ |
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369 #else //(__CPU_ARM11MP__) |
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370 #define FLUSH_ITLB_ENTRY(cc,addr) asm("mcr"#cc" p15, 0, "#addr", c8, c5, 1 "); /**< @internalTechnology */ |
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371 #define FLUSH_DTLB_ENTRY(cc,addr) asm("mcr"#cc" p15, 0, "#addr", c8, c6, 1 "); /**< @internalTechnology */ |
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372 #endif // else (__CPU_ARM11MP__) |
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373 #define FLUSH_ITLB_ASID(cc,asid) asm("mcr"#cc" p15, 0, "#asid", c8, c5, 2 "); /**< @internalTechnology */ |
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374 #define FLUSH_DTLB_ASID(cc,asid) asm("mcr"#cc" p15, 0, "#asid", c8, c6, 2 "); /**< @internalTechnology */ |
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375 |
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376 #define DRAIN_WRITE_BUFFER(cc,r,rd) asm("mcr"#cc" p15, 0, "#r", c7, c10, 4 "); |
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377 #define DATA_MEMORY_BARRIER(cc,r) asm("mcr"#cc" p15, 0, "#r", c7, c10, 5 "); |
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378 #define FLUSH_PREFETCH_BUFFER(cc,r) asm("mcr"#cc" p15, 0, "#r", c7, c5, 4 "); /**< @internalTechnology */ |
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379 #define FLUSH_BTB(cc,r) asm("mcr"#cc" p15, 0, "#r", c7, c5, 6 "); /**< @internalTechnology */ |
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380 #define CPWAIT(cc,r) /**< @internalTechnology */ // not sure about this |
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381 #define GET_CAR(cc,r) asm("mrc"#cc" p15, 0, "#r", c1, c0, 2 "); /**< @internalTechnology */ |
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382 #define SET_CAR(cc,r) asm("mcr"#cc" p15, 0, "#r", c1, c0, 2 "); /**< @internalTechnology */ |
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383 |
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384 #if defined(__CPU_PAGE_TABLES_FULLY_CACHED) |
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385 #define CACHE_MAINTENANCE_PDE_PTE_UPDATED(r) CLEAN_DCACHE_LINE(,r);\ |
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386 DRAIN_WRITE_BUFFER(,r,r); |
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387 #else |
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388 #define CACHE_MAINTENANCE_PDE_PTE_UPDATED(r) DRAIN_WRITE_BUFFER(,r,r); |
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389 #endif //end of __CPU_PAGE_TABLES_FULLY_CACHED |
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390 |
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391 #elif defined(__CPU_ARMV7) // end of elif (__CPU_ARMV6) |
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392 |
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393 // Define new-style cache/TLB maintenance instructions |
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394 #if defined(__CPU_CORTEX_A9__) && !defined(__CPU_ARM_A9_ERRATUM_571618_FIXED) |
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395 // ARM Cortex-A9 MPCore erratum 571618 workaround |
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396 // Execute memory barrier before interruptible CP15 operations |
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397 #define ICIALLU asm("mcr p15, 0, r0, c7, c10, 5 "); \ |
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398 asm("mcr p15, 0, r0, c7, c5, 0 "); /**< @internalTechnology */ |
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399 #else |
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400 #define ICIALLU asm("mcr p15, 0, r0, c7, c5, 0 "); /**< @internalTechnology */ |
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401 #endif // end of else (__CPU_CORTEX_A9__) && !(__CPU_ARM_A9_ERRATUM_571618_FIXED) |
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402 #define ICIMVAU(r) asm("mcr p15, 0, "#r", c7, c5, 1 "); /**< @internalTechnology */ |
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403 #define BPIALL asm("mcr p15, 0, r0, c7, c5, 6 "); /**< @internalTechnology */ |
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404 #define BPIMVA(r) asm("mcr p15, 0, "#r", c7, c5, 7 "); /**< @internalTechnology */ |
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405 #define DCIMVAC(r) asm("mcr p15, 0, "#r", c7, c6, 1 "); /**< @internalTechnology */ |
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406 #define DCISW(r) asm("mcr p15, 0, "#r", c7, c6, 2 "); /**< @internalTechnology */ |
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407 #define DCCMVAC(r) asm("mcr p15, 0, "#r", c7, c10, 1 "); /**< @internalTechnology */ |
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408 #define DCCSW(r) asm("mcr p15, 0, "#r", c7, c10, 2 "); /**< @internalTechnology */ |
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409 #define DCCMVAU(r) asm("mcr p15, 0, "#r", c7, c11, 1 "); /**< @internalTechnology */ |
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410 #define DCCIMVAC(r) asm("mcr p15, 0, "#r", c7, c14, 1 "); /**< @internalTechnology */ |
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411 #define DCCISW(r) asm("mcr p15, 0, "#r", c7, c14, 2 "); /**< @internalTechnology */ |
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412 |
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413 #ifdef __SMP__ |
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414 #if defined(__CPU_CORTEX_A9__) && !defined(__CPU_ARM_A9_ERRATUM_571618_FIXED) |
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415 // ARM Cortex-A9 MPCore erratum 571618 workaround |
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416 // Execute memory barrier before interruptible CP15 operations |
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417 #define ICIALLUIS asm("mcr p15, 0, r0, c7, c10, 5 "); \ |
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418 asm("mcr p15, 0, r0, c7, c1, 0 "); /**< @internalTechnology */ |
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419 #else |
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420 #define ICIALLUIS asm("mcr p15, 0, r0, c7, c1, 0 "); /**< @internalTechnology */ |
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421 #endif //end of else (__CPU_CORTEX_A9__) && !(__CPU_ARM_A9_ERRATUM_571618_FIXED) |
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422 #define BPIALLIS asm("mcr p15, 0, r0, c7, c1, 6 "); /**< @internalTechnology */ |
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423 #endif // end of __SMP__ |
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424 |
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425 #ifdef __CPU_SPLIT_TLB |
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426 #define ITLBIALL asm("mcr p15, 0, r0, c8, c5, 0 "); /**< @internalTechnology */ |
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427 #define ITLBIMVA(r) asm("mcr p15, 0, "#r", c8, c5, 1 "); /**< @internalTechnology */ |
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428 #define ITLBIASID(r) asm("mcr p15, 0, "#r", c8, c5, 2 "); /**< @internalTechnology */ |
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429 #define DTLBIALL asm("mcr p15, 0, r0, c8, c6, 0 "); /**< @internalTechnology */ |
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430 #define DTLBIMVA(r) asm("mcr p15, 0, "#r", c8, c6, 1 "); /**< @internalTechnology */ |
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431 #define DTLBIASID(r) asm("mcr p15, 0, "#r", c8, c6, 2 "); /**< @internalTechnology */ |
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432 #endif |
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433 #define UTLBIALL asm("mcr p15, 0, r0, c8, c7, 0 "); /**< @internalTechnology */ |
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434 #define UTLBIMVA(r) asm("mcr p15, 0, "#r", c8, c7, 1 "); /**< @internalTechnology */ |
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435 #if defined(__CPU_CORTEX_A9__) && !defined(__CPU_ARM_A9_ERRATUM_571618_FIXED) |
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436 // ARM Cortex-A9 MPCore erratum 571618 workaround |
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437 // Execute memory barrier before interruptible CP15 operations |
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438 #define UTLBIASID(r) asm("mcr p15, 0, r0, c7, c10, 5 "); \ |
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439 asm("mcr p15, 0, "#r", c8, c7, 2 "); /**< @internalTechnology */ |
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440 #else |
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441 #define UTLBIASID(r) asm("mcr p15, 0, "#r", c8, c7, 2 "); /**< @internalTechnology */ |
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442 #endif // end of else (__CPU_CORTEX_A9__) && !(__CPU_ARM_A9_ERRATUM_571618_FIXED) |
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443 |
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444 #ifdef __CPU_SUPPORTS_TLBIMVAA |
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445 #ifdef __CPU_SPLIT_TLB |
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446 #define ITLBIMVAA(r) asm("mcr p15, 0, "#r", c8, c5, 3 "); /**< @internalTechnology */ |
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447 #define DTLBIMVAA(r) asm("mcr p15, 0, "#r", c8, c6, 3 "); /**< @internalTechnology */ |
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448 #endif // end of __CPU_SPLIT_TLB |
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449 #define UTLBIMVAA(r) asm("mcr p15, 0, "#r", c8, c7, 3 "); /**< @internalTechnology */ |
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450 #endif // end of __CPU_SUPPORTS_TLBIMVAA |
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451 |
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452 #ifdef __SMP__ |
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453 #ifdef __CPU_SPLIT_TLB |
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454 #define ITLBIALLIS asm("mcr p15, 0, r0, c8, c3, 0 "); /**< @internalTechnology */ |
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455 #define ITLBIMVAIS(r) asm("mcr p15, 0, "#r", c8, c3, 1 "); /**< @internalTechnology */ |
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456 #if defined(__CPU_CORTEX_A9__) && !defined(__CPU_ARM_A9_ERRATUM_571618_FIXED) |
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457 // ARM Cortex-A9 MPCore erratum 571618 workaround |
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458 // Execute memory barrier before interruptible CP15 operations |
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459 #define ITLBIASIDIS(r) asm("mcr p15, 0, r0, c7, c10, 5 "); \ |
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460 asm("mcr p15, 0, "#r", c8, c3, 2 "); /**< @internalTechnology */ |
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461 #else |
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462 #define ITLBIASIDIS(r) asm("mcr p15, 0, "#r", c8, c3, 2 "); /**< @internalTechnology */ |
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463 #endif // end of else (__CPU_CORTEX_A9__) && !(__CPU_ARM_A9_ERRATUM_571618_FIXED) |
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464 #define DTLBIALLIS asm("mcr p15, 0, r0, c8, c3, 0 "); /**< @internalTechnology */ |
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465 #define DTLBIMVAIS(r) asm("mcr p15, 0, "#r", c8, c3, 1 "); /**< @internalTechnology */ |
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466 #if defined(__CPU_CORTEX_A9__) && !defined(__CPU_ARM_A9_ERRATUM_571618_FIXED) |
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467 // ARM Cortex-A9 MPCore erratum 571618 workaround |
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468 // Execute memory barrier before interruptible CP15 operations |
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469 #define DTLBIASIDIS(r) asm("mcr p15, 0, r0, c7, c10, 5 "); \ |
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470 asm("mcr p15, 0, "#r", c8, c3, 2 "); /**< @internalTechnology */ |
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471 #else |
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472 #define DTLBIASIDIS(r) asm("mcr p15, 0, "#r", c8, c3, 2 "); /**< @internalTechnology */ |
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473 #endif // end of else (__CPU_CORTEX_A9__) && !(__CPU_ARM_A9_ERRATUM_571618_FIXED) |
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474 #endif // end of __CPU_SPLIT_TLB |
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475 #define UTLBIALLIS asm("mcr p15, 0, r0, c8, c3, 0 "); /**< @internalTechnology */ |
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476 #define UTLBIMVAIS(r) asm("mcr p15, 0, "#r", c8, c3, 1 "); /**< @internalTechnology */ |
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477 #if defined(__CPU_CORTEX_A9__) && !defined(__CPU_ARM_A9_ERRATUM_571618_FIXED) |
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478 // ARM Cortex-A9 MPCore erratum 571618 workaround |
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479 // Execute memory barrier before interruptible CP15 operations |
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480 #define UTLBIASIDIS(r) asm("mcr p15, 0, r0, c7, c10, 5 "); \ |
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481 asm("mcr p15, 0, "#r", c8, c3, 2 "); /**< @internalTechnology */ |
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482 #else |
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483 #define UTLBIASIDIS(r) asm("mcr p15, 0, "#r", c8, c3, 2 "); /**< @internalTechnology */ |
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484 #endif // end of else (__CPU_CORTEX_A9__) && !(__CPU_ARM_A9_ERRATUM_571618_FIXED) |
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485 |
|
486 #ifdef __CPU_SUPPORTS_TLBIMVAA |
|
487 #ifdef __CPU_SPLIT_TLB |
|
488 #define ITLBIMVAAIS(r) asm("mcr p15, 0, "#r", c8, c3, 3 "); /**< @internalTechnology */ |
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489 #define DTLBIMVAAIS(r) asm("mcr p15, 0, "#r", c8, c3, 3 "); /**< @internalTechnology */ |
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490 #endif // end of __CPU_SPLIT_TLB |
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491 #define UTLBIMVAAIS(r) asm("mcr p15, 0, "#r", c8, c3, 3 "); /**< @internalTechnology */ |
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492 #endif // end of __CPU_SUPPORTS_TLBIMVAA |
|
493 #endif // end of __SMP__ |
|
494 |
|
495 |
|
496 #define DRAIN_WRITE_BUFFER(cc,r,rd) __DATA_SYNC_BARRIER__(r) |
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497 #define DATA_MEMORY_BARRIER(cc,r) __DATA_MEMORY_BARRIER__(r) |
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498 #define FLUSH_PREFETCH_BUFFER(cc,r) __INST_SYNC_BARRIER__(r) /**< @internalTechnology */ |
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499 //#define FLUSH_BTB(cc,r) asm("mcr"#cc" p15, 0, "#r", c7, c5, 6 "); /**< @internalTechnology */ |
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500 |
|
501 #define CPWAIT(cc,r) /**< @internalTechnology */ // not sure about this |
|
502 #define GET_CAR(cc,r) asm("mrc"#cc" p15, 0, "#r", c1, c0, 2 "); /**< @internalTechnology */ |
|
503 #define SET_CAR(cc,r) asm("mcr"#cc" p15, 0, "#r", c1, c0, 2 "); \ |
|
504 __INST_SYNC_BARRIER__(r) /**< @internalTechnology */ |
|
505 |
|
506 #if !defined(__CPU_SUPPORTS_PAGE_TABLE_WALK_TO_L1_CACHE) && defined(__CPU_PAGE_TABLES_FULLY_CACHED) |
|
507 #define CACHE_MAINTENANCE_PDE_PTE_UPDATED(r) DCCMVAU(r); \ |
|
508 __DATA_SYNC_BARRIER__(r); |
|
509 #else |
|
510 #define CACHE_MAINTENANCE_PDE_PTE_UPDATED(r) __DATA_SYNC_BARRIER__(r); |
|
511 #endif // end of !(__CPU_SUPPORTS_PAGE_TABLE_WALK_TO_L1_CACHE) && (__CPU_PAGE_TABLES_FULLY_CACHED) |
|
512 |
|
513 #endif // end of of elif (__CPU_ARMV7) |
|
514 |
|
515 |
|
516 /** |
|
517 CPU_ARM1136_ERRATUM_317041: Bits [4:3] of Translation Table Base address registers (TTBR0, TTBR1) |
|
518 do not read back correctly, but instead always return 0. |
|
519 @internalComponent |
|
520 @released |
|
521 */ |
|
522 #if defined(__CPU_ARM1136__) && defined(__HAS_EXTERNAL_CACHE__) && !defined(__CPU_ARM1136_ERRATUM_317041_FIXED) |
|
523 #define UPDATE_PW_CACHING_ATTRIBUTES(cc,r) asm("orr"#cc" "#r", "#r", #0x18") |
|
524 #else |
|
525 #define UPDATE_PW_CACHING_ATTRIBUTES(cc,r) |
|
526 #endif |
|
527 |
|
528 // Instruction macros |
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529 |
|
530 #if defined(__CPU_ARMV6) || defined(__CPU_ARMV7) |
|
531 #define SRSgen(P,U,W,mode) asm(".word %a0" : : "i" ((TInt)(0xf84d0500|(P<<24)|(U<<23)|(W<<21)|(mode)))); |
|
532 #define SRSIA(mode) SRSgen(0,1,0,mode) |
|
533 #define SRSIAW(mode) SRSgen(0,1,1,mode) |
|
534 #define SRSDB(mode) SRSgen(1,0,0,mode) |
|
535 #define SRSDBW(mode) SRSgen(1,0,1,mode) |
|
536 #define SRSIB(mode) SRSgen(1,1,0,mode) |
|
537 #define SRSIBW(mode) SRSgen(1,1,1,mode) |
|
538 #define SRSDA(mode) SRSgen(0,0,0,mode) |
|
539 #define SRSDAW(mode) SRSgen(0,0,1,mode) |
|
540 #define RFEgen(P,U,W,base) asm(".word %a0" : : "i" ((TInt)(0xf8100a00|(P<<24)|(U<<23)|(W<<21)|(base<<16)))); |
|
541 #define RFEIA(base) RFEgen(0,1,0,base) |
|
542 #define RFEIAW(base) RFEgen(0,1,1,base) |
|
543 #define RFEDB(base) RFEgen(1,0,0,base) |
|
544 #define RFEDBW(base) RFEgen(1,0,1,base) |
|
545 #define RFEIB(base) RFEgen(1,1,0,base) |
|
546 #define RFEIBW(base) RFEgen(1,1,1,base) |
|
547 #define RFEDA(base) RFEgen(0,0,0,base) |
|
548 #define RFEDAW(base) RFEgen(0,0,1,base) |
|
549 #elif defined(__CPU_XSCALE__) // end of (__CPU_ARMV6) || (__CPU_ARMV7) |
|
550 #define MAR(acc,RdLo,RdHi) MCRR(0,0,RdLo,RdHi,acc) |
|
551 #define MARcc(cc,acc,RdLo,RdHi) MCRR(cc,0,0,RdLo,RdHi,acc) |
|
552 #define MRA(acc,RdLo,RdHi) MRRC(0,0,RdLo,RdHi,acc) |
|
553 #define MRAcc(cc,acc,RdLo,RdHi) MRRC(cc,0,0,RdLo,RdHi,acc) |
|
554 #define MIAgen(cc,acc,Rm,Rs,opc3) asm(".word %a0" : : "i" ((TInt)0x0e200010|((cc)<<28)|((opc3)<<16)|((Rs)<<12)|((acc)<<5)|(Rm))); |
|
555 #define MIA(acc,Rm,Rs) MIAgen(CC_AL,acc,Rm,Rs,0) |
|
556 #define MIAPH(acc,Rm,Rs) MIAgen(CC_AL,acc,Rm,Rs,8) |
|
557 #define MIABB(acc,Rm,Rs) MIAgen(CC_AL,acc,Rm,Rs,12) |
|
558 #define MIATB(acc,Rm,Rs) MIAgen(CC_AL,acc,Rm,Rs,13) |
|
559 #define MIABT(acc,Rm,Rs) MIAgen(CC_AL,acc,Rm,Rs,14) |
|
560 #define MIATT(acc,Rm,Rs) MIAgen(CC_AL,acc,Rm,Rs,15) |
|
561 #define MIAcc(cc,acc,Rm,Rs) MIAgen(cc,acc,Rm,Rs,0) |
|
562 #define MIAPHcc(cc,acc,Rm,Rs) MIAgen(cc,acc,Rm,Rs,8) |
|
563 #define MIABBcc(cc,acc,Rm,Rs) MIAgen(cc,acc,Rm,Rs,12) |
|
564 #define MIATBcc(cc,acc,Rm,Rs) MIAgen(cc,acc,Rm,Rs,13) |
|
565 #define MIABTcc(cc,acc,Rm,Rs) MIAgen(cc,acc,Rm,Rs,14) |
|
566 #define MIATTcc(cc,acc,Rm,Rs) MIAgen(cc,acc,Rm,Rs,15) |
|
567 #endif // end of elif (__CPU_XSCALE__) |
|
568 |
|
569 #ifdef __CPU_ARM_HAS_CPS |
|
570 #define CPSgen(im,mm,f,mode) asm(".word %a0" : : "i" ((TInt)(0xf1000000|((im)<<18)|((mm)<<17)|((f)<<6)|(mode)))) |
|
571 #if __ARM_ASSEMBLER_ISA__ >= 6 |
|
572 #define CPSIDAIF asm("cpsidaif ") |
|
573 #define CPSIDAI asm("cpsidai ") |
|
574 #define CPSIDIF asm("cpsidif ") |
|
575 #define CPSIDI asm("cpsidi ") |
|
576 #define CPSIDF asm("cpsidf ") |
|
577 #define CPSIEAIF asm("cpsieaif ") |
|
578 #define CPSIEI asm("cpsiei ") |
|
579 #define CPSIEF asm("cpsief ") |
|
580 #define CPSIEIF asm("cpsieif ") |
|
581 #else |
|
582 #define CPSIDAIF CPSgen(3,0,7,0) // disable all interrupts, leave mode alone |
|
583 #define CPSIDAI CPSgen(3,0,6,0) // disable IRQs, leave mode alone |
|
584 #define CPSIDIF CPSgen(3,0,3,0) // disable IRQs and FIQs, leave mode alone |
|
585 #define CPSIDI CPSgen(3,0,2,0) // disable IRQs, leave mode alone |
|
586 #define CPSIDF CPSgen(3,0,1,0) // disable FIQs, leave mode alone |
|
587 #define CPSIEAIF CPSgen(2,0,7,0) // enable all interrupts, leave mode alone |
|
588 #define CPSIEI CPSgen(2,0,2,0) // enable IRQs, leave mode alone |
|
589 #define CPSIEF CPSgen(2,0,1,0) // enable FIQs, leave mode alone |
|
590 #define CPSIEIF CPSgen(2,0,3,0) // enable IRQs and FIQs, leave mode alone |
|
591 #endif // end of __ARM_ASSEMBLER_ISA__ >= 6 |
|
592 #define CPSIDAIFM(mode) CPSgen(3,1,7,mode) // disable all interrupts and change mode |
|
593 #define CPSIDIFM(mode) CPSgen(3,1,3,mode) // disable all interrupts and change mode |
|
594 #define CPSIDAIM(mode) CPSgen(3,1,6,mode) // disable IRQs and change mode |
|
595 #define CPSIDIM(mode) CPSgen(3,1,2,mode) // disable IRQs and change mode |
|
596 #define CPSIDFM(mode) CPSgen(3,1,1,mode) // disable FIQs and change mode |
|
597 #define CPSIEAIFM(mode) CPSgen(2,1,7,mode) // enable all interrupts and change mode |
|
598 #define CPSIEIM(mode) CPSgen(2,1,2,mode) // enable IRQs and change mode |
|
599 #define CPSIEFM(mode) CPSgen(2,1,1,mode) // enable FIQs and change mode |
|
600 #define CPSIEIFM(mode) CPSgen(2,1,3,mode) // enable IRQs and FIQs, and change mode |
|
601 #define CPSCHM(mode) CPSgen(0,1,0,mode) // change mode, leave interrupt masks alone |
|
602 #endif // end of __CPU_ARM_HAS_CPS |
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603 |
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604 // Processor modes |
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605 #define MODE_USR 0x10 |
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606 #define MODE_FIQ 0x11 |
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607 #define MODE_IRQ 0x12 |
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608 #define MODE_SVC 0x13 |
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609 #define MODE_ABT 0x17 |
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610 #define MODE_UND 0x1b |
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611 #define MODE_SYS 0x1f |
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612 |
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613 // Macros for changing processor made and interrupt status |
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614 // |
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615 // Two instructions are necessary prior to ARMv6, and these may be interleaved. |
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616 // |
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617 // SET_MODE - sets mode and intrrupts status |
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618 // SET_INTS - sets interrupts status (requires knowing the current mode at compile time) |
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619 // INTS_ON - enables interrupts (requires the cpsr value be available at run time) |
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620 // INTS_OFF - disables interrupts (requires the cpsr value be available at run time) |
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621 |
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622 #ifdef __CPU_ARM_HAS_CPS |
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623 |
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624 #define INTS_ALL_OFF IDIF |
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625 #define INTS_IRQ_OFF IDI |
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626 #define INTS_FIQ_ON IEF |
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627 #define INTS_ALL_ON IEIF |
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628 |
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629 #define CONCAT2(a,b) a##b |
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630 #define CONCAT3(a,b,c) a##b##c |
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631 |
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632 #define SET_MODE_1(rd, newMode, newInts) |
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633 #define SET_MODE_2(rd, newMode, newInts) CONCAT3(CPS, newInts, M)(newMode) |
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634 |
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635 #define SET_INTS_1(rd, currentMode, newInts) |
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636 #define SET_INTS_2(rd, currentMode, newInts) CONCAT2(CPS, newInts) |
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637 |
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638 #define INTS_ON_1(rd, rCpsr, newInts) |
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639 #define INTS_ON_2(rd, rCpsr, newInts) CONCAT2(CPS, newInts) |
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640 |
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641 #define INTS_OFF_1(rd, rCpsr, newInts) |
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642 #define INTS_OFF_2(rd, rCpsr, newInts) CONCAT2(CPS, newInts) |
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643 |
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644 #else // __CPU_ARM_HAS_CPS |
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645 |
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646 #define INTS_ALL_OFF 0xc0 |
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647 #define INTS_IRQ_OFF 0x80 |
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648 #define INTS_FIQ_ON 0x80 |
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649 #define INTS_ALL_ON 0x00 |
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650 |
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651 #define SET_MODE_1(rd, newMode, newInts) asm("mov "#rd", #%a0" : : "i" (newMode | newInts)) |
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652 #define SET_MODE_2(rd, newMode, newInts) asm("msr cpsr_c, "#rd) |
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653 |
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654 #define SET_INTS_1(rd, currentMode, newInts) SET_MODE_1(rd, currentMode, newInts) |
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655 #define SET_INTS_2(rd, currentMode, newInts) SET_MODE_2(rd, currentMode, newInts) |
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656 |
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657 #define INTS_ON_1(rd, rCpsr, newInts) asm("bic "#rd", "#rCpsr", #%a0" : : "i" (newInts ^ 0xc0)) |
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658 #define INTS_ON_2(rd, rCpsr, newInts) asm("msr cpsr_c, "#rd) |
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659 |
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660 #define INTS_OFF_1(rd, rCpsr, newInts) asm("orr "#rd", "#rCpsr", #%a0" : : "i" (newInts)) |
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661 #define INTS_OFF_2(rd, rCpsr, newInts) asm("msr cpsr_c, "#rd) |
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662 |
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663 #endif // end of __CPU_ARM_HAS_CPS |
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664 |
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665 #define SET_MODE(rd, newMode, newInts) SET_MODE_1(rd, newMode, newInts); SET_MODE_2(rd, newMode, newInts) |
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666 #define SET_INTS(rd, currentMode, newInts) SET_INTS_1(rd, currentMode, newInts); SET_INTS_2(rd, currentMode, newInts) |
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667 #define INTS_ON(rd, rCpsr, newInts) INTS_ON_1(rd, rCpsr, newInts); INTS_ON_2(rd, rCpsr, newInts) |
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668 #define INTS_OFF(rd, rCpsr, newInts) INTS_OFF_1(rd, rCpsr, newInts); INTS_OFF_2(rd, rCpsr, newInts) |
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669 |
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670 #define __chill() |
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671 |
|
672 #if defined(__SMP__) && !defined(__CPU_ARM_HAS_LDREX_STREX_V6K) |
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673 #error SMP not allowed without v6K |
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674 #endif |
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675 #if defined(__SMP__) && !defined(__CPU_HAS_CP15_THREAD_ID_REG) |
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676 #error SMP not allowed without thread ID registers |
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677 #endif |
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678 |
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679 #endif // end of __CPU_ARM |
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680 |
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681 #if defined(__CPU_X86) && defined(__EPOC32__) |
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682 #define __CPU_HAS_MMU |
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683 #define __CPU_HAS_CACHE |
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684 #define __CPU_SUPPORTS_FAST_PROCESS_SWITCH |
|
685 |
|
686 // Page/directory tables are cached on X86. |
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687 #define __CPU_PAGE_TABLES_FULLY_CACHED |
|
688 |
|
689 #if defined(__VC32__) |
|
690 #define X86_PAUSE _asm rep nop |
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691 #define __chill() do { _asm rep nop } while(0) |
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692 #elif defined(__GCC32__) |
|
693 #define X86_PAUSE __asm__ __volatile__("pause "); |
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694 #define __chill() __asm__ __volatile__("pause ") |
|
695 #else |
|
696 #error Unknown x86 compiler |
|
697 #endif |
|
698 |
|
699 #if defined(__cplusplus) |
|
700 extern "C" { |
|
701 #endif |
|
702 #if defined(__VC32__) |
|
703 extern int _inp(unsigned short); // input byte (compiler intrinsic) |
|
704 extern unsigned short _inpw(unsigned short); // input word (compiler intrinsic) |
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705 extern unsigned long _inpd(unsigned short); // input dword (compiler intrinsic) |
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706 extern int _outp(unsigned short, int); // output byte (compiler intrinsic) |
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707 extern unsigned short _outpw(unsigned short, unsigned short); // output word (compiler intrinsic) |
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708 extern unsigned long _outpd(unsigned short, unsigned long); // output dword (compiler intrinsic) |
|
709 |
|
710 #pragma intrinsic(_inp, _inpw, _inpd, _outp, _outpw, _outpd) |
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711 |
|
712 #define x86_in8(port) ((TUint8)_inp(port)) |
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713 #define x86_in16(port) ((TUint16)_inpw(port)) |
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714 #define x86_in32(port) ((TUint32)_inpd(port)) |
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715 #define x86_out8(port,data) ((void)_outp((port),(TUint8)(data))) |
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716 #define x86_out16(port,data) ((void)_outpw((port),(TUint16)(data))) |
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717 #define x86_out32(port,data) ((void)_outpd((port),(TUint32)(data))) |
|
718 |
|
719 #elif defined(__GCC32__) // end of (__VC32__) |
|
720 inline TUint8 _inpb(TUint16 port) |
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721 { |
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722 TUint8 ret; |
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723 __asm__ __volatile__("in al, dx" : "=a" (ret) : "d" (port)); |
|
724 return ret; |
|
725 } |
|
726 |
|
727 inline TUint16 _inpw(TUint16 port) |
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728 { |
|
729 TUint8 ret; |
|
730 __asm__ __volatile__("in ax, dx" : "=a" (ret) : "d" (port)); |
|
731 return ret; |
|
732 } |
|
733 |
|
734 inline TUint32 _inpd(TUint16 port) |
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735 { |
|
736 TUint32 ret; |
|
737 __asm__ __volatile__("in eax, dx" : "=a" (ret) : "d" (port)); |
|
738 return ret; |
|
739 } |
|
740 |
|
741 inline void _outpb(TUint16 port, TUint8 data) |
|
742 { |
|
743 __asm__ __volatile__("out dx, al" : : "d" (port), "a" (data)); |
|
744 } |
|
745 |
|
746 inline void _outpw(TUint16 port, TUint16 data) |
|
747 { |
|
748 __asm__ __volatile__("out dx, ax" : : "d" (port), "a" (data)); |
|
749 } |
|
750 |
|
751 inline void _outpd(TUint16 port, TUint32 data) |
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752 { |
|
753 __asm__ __volatile__("out dx, eax" : : "d" (port), "a" (data)); |
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754 } |
|
755 |
|
756 #define x86_in8(port) (_inpb(port)) |
|
757 #define x86_in16(port) (_inpw(port)) |
|
758 #define x86_in32(port) (_inpd(port)) |
|
759 #define x86_out8(port,data) (_outpb((port),(TUint8)(data))) |
|
760 #define x86_out16(port,data) (_outpw((port),(TUint16)(data))) |
|
761 #define x86_out32(port,data) (_outpd((port),(TUint32)(data))) |
|
762 |
|
763 #else // end of elif (__GCC32__) |
|
764 #error Unknown x86 compiler |
|
765 #endif |
|
766 #if defined(__cplusplus) |
|
767 } |
|
768 #endif // end of (__VC32__) elif __GCC32__ else |
|
769 |
|
770 #endif //__CPU_X86 && __EPOC32__ |
|
771 |
|
772 |
|
773 #undef __USER_MEMORY_GUARDS_ENABLED__ |
|
774 #if defined(_DEBUG) && !defined(__KERNEL_APIS_DISABLE_USER_MEMORY_GUARDS__) |
|
775 #if defined(__MEMMODEL_MULTIPLE__) || defined(__MEMMODEL_FLEXIBLE__) |
|
776 #if defined(__CPU_ARM) |
|
777 #define __USER_MEMORY_GUARDS_ENABLED__ |
|
778 #endif |
|
779 #endif |
|
780 #endif // end of (_DEBUG) && !(__KERNEL_APIS_DISABLE_USER_MEMORY_GUARDS__) |
|
781 |
|
782 #ifndef __USER_MEMORY_GUARDS_ENABLED__ |
|
783 |
|
784 #define USER_MEMORY_GUARD_SAVE_WORDS 0 |
|
785 #define USER_MEMORY_DOMAIN 0 |
|
786 |
|
787 #define USER_MEMORY_GUARD_SAVE(save) |
|
788 #define USER_MEMORY_GUARD_RESTORE(save,temp) |
|
789 #define USER_MEMORY_GUARD_ON(cc,save,temp) |
|
790 #define USER_MEMORY_GUARD_OFF(cc,save,temp) |
|
791 #define USER_MEMORY_GUARD_ON_IF_MODE_USR(temp) |
|
792 #define USER_MEMORY_GUARD_OFF_IF_MODE_USR(temp) |
|
793 #define USER_MEMORY_GUARD_ASSERT_ON(temp) |
|
794 #define USER_MEMORY_GUARD_ASSERT_OFF_IF_MODE_USR(psr) |
|
795 |
|
796 #else // __USER_MEMORY_GUARDS_ENABLED__ |
|
797 |
|
798 #define USER_MEMORY_GUARD_SAVE_WORDS 2 |
|
799 #define USER_MEMORY_DOMAIN 15 |
|
800 #define USER_MEMORY_DOMAIN_MASK (3 << (2*USER_MEMORY_DOMAIN)) |
|
801 #define USER_MEMORY_DOMAIN_CLIENT (1 << (2*USER_MEMORY_DOMAIN)) |
|
802 |
|
803 // Save the DACR in the named register |
|
804 #define USER_MEMORY_GUARD_SAVE(save) \ |
|
805 asm("mrc p15, 0, "#save", c3, c0, 0"); /* save<-DACR */ |
|
806 |
|
807 // Restore access to domain 15 (user pages) to the state previously saved |
|
808 // In this case, 'save' may not be the same register as 'temp' |
|
809 #define USER_MEMORY_GUARD_RESTORE(save,temp) \ |
|
810 asm("mrc p15, 0, "#temp", c3, c0, 0"); /* temp<-DACR */ \ |
|
811 asm("bic "#temp", "#temp", #%a0" : : "i" USER_MEMORY_DOMAIN_MASK); \ |
|
812 asm("and "#save", "#save", #%a0" : : "i" USER_MEMORY_DOMAIN_MASK); \ |
|
813 asm("orr "#temp", "#temp", "#save ); \ |
|
814 asm("mcr p15, 0, "#temp", c3, c0, 0"); /* DACR<-temp */ \ |
|
815 __INST_SYNC_BARRIER__(temp) |
|
816 |
|
817 // Disable access to domain 15 (user pages) |
|
818 // 'save' may be the same register as 'temp', but in that case the use as |
|
819 // a temporary takes precedence and the value left in 'save' is undefined |
|
820 #define USER_MEMORY_GUARD_ON(cc,save,temp) \ |
|
821 asm("mrc"#cc" p15, 0, "#save", c3, c0, 0"); /* save<-DACR */ \ |
|
822 asm("bic"#cc" "#temp", "#save", #%a0" : : "i" USER_MEMORY_DOMAIN_MASK); \ |
|
823 asm("mcr"#cc" p15, 0, "#temp", c3, c0, 0"); /* DACR<-temp */ \ |
|
824 __INST_SYNC_BARRIER__(temp) |
|
825 |
|
826 // Enable access to domain 15 (user pages) as a client |
|
827 // 'save' may be the same register as 'temp', but in that case the use as |
|
828 // a temporary takes precedence and the value left in 'save' is undefined |
|
829 #define USER_MEMORY_GUARD_OFF(cc,save,temp) \ |
|
830 asm("mrc"#cc" p15, 0, "#save", c3, c0, 0"); /* save<-DACR */ \ |
|
831 asm("orr"#cc" "#temp", "#save", #%a0" : : "i" USER_MEMORY_DOMAIN_CLIENT); \ |
|
832 asm("mcr"#cc" p15, 0, "#temp", c3, c0, 0"); /* DACR<-temp */ \ |
|
833 __INST_SYNC_BARRIER__(temp) |
|
834 |
|
835 // Disable access to domain 15 (user pages) if SPSR indicates mode_usr |
|
836 // The specified 'temp' register is left with an undefined value |
|
837 #define USER_MEMORY_GUARD_ON_IF_MODE_USR(temp) \ |
|
838 asm("mrs "#temp", spsr"); \ |
|
839 asm("tst "#temp", #0x0f"); \ |
|
840 USER_MEMORY_GUARD_ON(eq,temp,temp) |
|
841 |
|
842 // Enable access to domain 15 (user pages) if SPSR indicates mode_usr |
|
843 // The specified 'temp' register is left with an undefined value |
|
844 #define USER_MEMORY_GUARD_OFF_IF_MODE_USR(temp) \ |
|
845 asm("mrs "#temp", spsr"); \ |
|
846 asm("tst "#temp", #0x0f"); \ |
|
847 USER_MEMORY_GUARD_OFF(eq,temp,temp) |
|
848 |
|
849 // Assert that access to domain 15 (user pages) is disabled |
|
850 #define USER_MEMORY_GUARD_ASSERT_ON(temp) \ |
|
851 asm("mrc p15, 0, "#temp", c3, c0, 0"); /* temp<-DACR */ \ |
|
852 asm("tst "#temp", #%a0" : : "i" USER_MEMORY_DOMAIN_MASK); \ |
|
853 asm("cdpne p15, 0, c0, c0, c0, 0"); /* fault if nonzero */ |
|
854 |
|
855 // Assert that access to domain 15 (user pages) is enabled if the value |
|
856 // in 'psr' says we came from/are going back to user mode |
|
857 #define USER_MEMORY_GUARD_ASSERT_OFF_IF_MODE_USR(psr) \ |
|
858 asm("tst "#psr", #0x0f"); /* check for mode_usr */ \ |
|
859 asm("mrceq p15, 0, "#psr", c3, c0, 0"); /* psr<-DACR */ \ |
|
860 asm("tsteq "#psr", #%a0" : : "i" USER_MEMORY_DOMAIN_MASK); \ |
|
861 asm("cdpeq p15, 0, c0, c0, c0, 0"); /* fault if no access */ |
|
862 |
|
863 #endif // end of else __USER_MEMORY_GUARDS_ENABLED__ |
|
864 |
|
865 #endif // __NK_CPU_H__ |