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1 // Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies). |
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2 // All rights reserved. |
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3 // This component and the accompanying materials are made available |
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4 // under the terms of the License "Eclipse Public License v1.0" |
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5 // which accompanies this distribution, and is available |
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6 // at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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7 // |
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8 // Initial Contributors: |
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9 // Nokia Corporation - initial contribution. |
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10 // |
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11 // Contributors: |
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12 // |
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13 // Description: |
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14 // e32\include\nkernsmp\arm\arm_scu.h |
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15 // Register definitions for ARM Snoop Control Unit |
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16 // |
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17 // WARNING: This file contains some APIs which are internal and are subject |
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18 // to change without notice. Such APIs should therefore not be used |
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19 // outside the Kernel and Hardware Services package. |
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20 // |
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21 |
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22 #ifndef __ARM_SCU_H__ |
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23 #define __ARM_SCU_H__ |
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24 #include <e32def.h> |
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25 |
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26 #ifdef __STANDALONE_NANOKERNEL__ |
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27 #undef __IN_KERNEL__ |
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28 #define __IN_KERNEL__ |
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29 #endif |
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30 |
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31 #if defined(__CPU_ARM11MP__) |
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32 struct ArmScu |
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33 { |
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34 volatile TUint32 iCtrl; // 00 Control register |
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35 volatile TUint32 iConfig; // 04 Configuration register (RO) |
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36 volatile TUint32 iCpuStatus; // 08 SCU CPU Status register |
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37 volatile TUint32 iInvalidateAll; // 0C Invalidate All register (WO) |
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38 volatile TUint32 iPMCtrl; // 10 Performance Monitor Control register |
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39 volatile TUint32 iMonitorEvents0; // 14 Monitor Counter Events 0 |
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40 volatile TUint32 iMonitorEvents1; // 18 Monitor Counter Events 1 |
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41 volatile TUint32 iMonitorCount0; // 1C Monitor Counter 0 |
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42 volatile TUint32 iMonitorCount1; // 20 Monitor Counter 1 |
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43 volatile TUint32 iMonitorCount2; // 24 Monitor Counter 2 |
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44 volatile TUint32 iMonitorCount3; // 28 Monitor Counter 3 |
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45 volatile TUint32 iMonitorCount4; // 2C Monitor Counter 4 |
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46 volatile TUint32 iMonitorCount5; // 30 Monitor Counter 5 |
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47 volatile TUint32 iMonitorCount6; // 34 Monitor Counter 6 |
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48 volatile TUint32 iMonitorCount7; // 38 Monitor Counter 7 |
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49 volatile TUint32 i_Skip_1[49]; // 3C unused |
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50 }; |
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51 |
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52 __ASSERT_COMPILE(sizeof(ArmScu)==0x100); |
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53 |
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54 enum TArmScuCtrl |
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55 { |
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56 E_ArmScuCtrl_Enable =1u, // SCU Enable |
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57 E_ArmScuCtrl_AccessShift =1u, |
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58 E_ArmScuCtrl_AccessMask =0x1eu, // bits 1-4 = SCU access control for CPU0-3 |
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59 E_ArmScuCtrl_IIAliasShift =5u, |
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60 E_ArmScuCtrl_IIAliasMask =0x1e0u, // bits 5-8 = Interrupt Interface Alias enable for CPU0-3 |
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61 E_ArmScuCtrl_PIAliasShift =9u, |
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62 E_ArmScuCtrl_PIAliasMask =0x1e00u, // bits 9-12 = Peripheral Interface Alias enable for CPU0-3 |
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63 }; |
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64 |
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65 enum TArmScuPMCR |
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66 { |
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67 E_ArmScuPMCR_Enable =1u, // 0=all counters disabled |
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68 E_ArmScuPMCR_ResetAll =2u, // write 1 resets all counters |
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69 E_ArmScuPMCR_IntEn0 =0x100u, // Interrupt Enable for MN0 |
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70 E_ArmScuPMCR_IntEn1 =0x200u, // Interrupt Enable for MN1 |
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71 E_ArmScuPMCR_IntEn2 =0x400u, // Interrupt Enable for MN2 |
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72 E_ArmScuPMCR_IntEn3 =0x800u, // Interrupt Enable for MN3 |
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73 E_ArmScuPMCR_IntEn4 =0x1000u, // Interrupt Enable for MN4 |
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74 E_ArmScuPMCR_IntEn5 =0x2000u, // Interrupt Enable for MN5 |
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75 E_ArmScuPMCR_IntEn6 =0x4000u, // Interrupt Enable for MN6 |
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76 E_ArmScuPMCR_IntEn7 =0x8000u, // Interrupt Enable for MN7 |
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77 E_ArmScuPMCR_Ovfw0 =0x10000u, // Overflow Flag for MN0 (write 1 to clear) |
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78 E_ArmScuPMCR_Ovfw1 =0x20000u, // Overflow Flag for MN1 |
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79 E_ArmScuPMCR_Ovfw2 =0x40000u, // Overflow Flag for MN2 |
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80 E_ArmScuPMCR_Ovfw3 =0x80000u, // Overflow Flag for MN3 |
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81 E_ArmScuPMCR_Ovfw4 =0x100000u, // Overflow Flag for MN4 |
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82 E_ArmScuPMCR_Ovfw5 =0x200000u, // Overflow Flag for MN5 |
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83 E_ArmScuPMCR_Ovfw6 =0x400000u, // Overflow Flag for MN6 |
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84 E_ArmScuPMCR_Ovfw7 =0x800000u, // Overflow Flag for MN7 |
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85 }; |
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86 |
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87 |
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88 #elif defined(__CPU_CORTEX_A9__) |
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89 struct ArmScu |
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90 { |
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91 volatile TUint32 iCtrl; // 00 Control register |
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92 volatile TUint32 iConfig; // 04 Configuration register (RO) |
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93 volatile TUint32 iCpuStatus; // 08 SCU CPU Power Status register |
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94 volatile TUint32 iInvalidateAll; // 0C Invalidate All register (WO) |
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95 volatile TUint32 i_Skip_1[12]; // 10-3F unused |
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96 volatile TUint32 i_FSAR; // 40 Filtering Start Address Register |
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97 volatile TUint32 i_FEAR; // 44 Filtering End Address Register |
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98 volatile TUint32 i_Skip_2[2]; // 48-4F unused |
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99 volatile TUint32 i_SAC; // 50 SCU Access Control Register |
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100 volatile TUint32 i_SSAC; // 54 SCU Secure Access Control Register |
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101 volatile TUint32 i_Skip_3[42]; // 58-FF unused |
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102 }; |
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103 |
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104 __ASSERT_COMPILE(sizeof(ArmScu)==0x100); |
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105 |
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106 enum TArmScuCtrl |
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107 { |
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108 E_ArmScuCtrl_Enable =1u, // SCU Enable |
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109 E_ArmScuCtrl_AFEnable =2u, // SCU Address Filtering Enable |
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110 E_ArmScuCtrl_ParityEnable =4u, // SCU Parity Enable |
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111 }; |
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112 |
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113 enum TArmScuSAC |
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114 { |
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115 E_ArmScuSAC_CPU0 =1u, // If set, CPU0 can access SCU registers |
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116 E_ArmScuSAC_CPU1 =2u, // If set, CPU1 can access SCU registers |
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117 E_ArmScuSAC_CPU2 =4u, // If set, CPU2 can access SCU registers |
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118 E_ArmScuSAC_CPU3 =8u, // If set, CPU3 can access SCU registers |
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119 }; |
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120 |
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121 enum TArmScuSSAC |
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122 { |
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123 E_ArmScuSSAC_CPU0 =1u, // If set, CPU0 can access SCU registers in nonsecure state |
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124 E_ArmScuSSAC_CPU1 =2u, // If set, CPU1 can access SCU registers in nonsecure state |
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125 E_ArmScuSSAC_CPU2 =4u, // If set, CPU2 can access SCU registers in nonsecure state |
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126 E_ArmScuSSAC_CPU3 =8u, // If set, CPU3 can access SCU registers in nonsecure state |
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127 E_ArmScuSSAC_Timer0 =16u, // If set, CPU0 private timer is accessible in nonsecure state |
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128 E_ArmScuSSAC_Timer1 =32u, // If set, CPU1 private timer is accessible in nonsecure state |
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129 E_ArmScuSSAC_Timer2 =64u, // If set, CPU2 private timer is accessible in nonsecure state |
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130 E_ArmScuSSAC_Timer3 =128u, // If set, CPU3 private timer is accessible in nonsecure state |
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131 }; |
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132 |
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133 #else |
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134 #error Unknown SCU |
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135 #endif |
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136 |
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137 enum TArmScuConfig |
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138 { |
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139 E_ArmScuCfg_NCpusMask =3u, // bits0,1 = number of CPUs - 1 |
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140 E_ArmScuCfg_CpuSMPShift =4u, |
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141 E_ArmScuCfg_CpuSMPMask =0xf0u, // bits4-7 = CPU0-3 SMP mode indicator |
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142 E_ArmScuCfg_TagShift =8u, |
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143 E_ArmScuCfg_TagMask =0xff00u, // two bits per CPU, tag RAM size = 16KB<<n (n=0,1,2 n=3 reserved) |
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144 }; |
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145 |
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146 // Bits 2n,2n+1 of CPU status refer to CPU n |
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147 enum TArmScuCPUStatus |
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148 { |
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149 E_ArmScuCpuStat_Normal =0u, // normal mode |
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150 // 1 reserved |
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151 E_ArmScuCpuStat_Dormant =2u, // dormant mode |
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152 E_ArmScuCpuStat_PowerDown =3u, // power down mode |
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153 }; |
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154 |
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155 #endif // __ARM_SCU_H__ |