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1 // Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies). |
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2 // All rights reserved. |
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3 // This component and the accompanying materials are made available |
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4 // under the terms of the License "Eclipse Public License v1.0" |
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5 // which accompanies this distribution, and is available |
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6 // at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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7 // |
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8 // Initial Contributors: |
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9 // Nokia Corporation - initial contribution. |
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10 // |
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11 // Contributors: |
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12 // |
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13 // Description: |
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14 // e32\common\x86\atomic_skeleton.h |
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15 // |
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16 // |
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17 |
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18 /** |
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19 Read an 8/16/32 bit quantity with acquire semantics |
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20 |
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21 @param a Address of data to be read - must be naturally aligned |
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22 @return The value read |
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23 */ |
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24 EXPORT_C __NAKED__ __TUintX__ __fname__(__e32_atomic_load_acq)(const volatile TAny* /*a*/) |
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25 { |
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26 asm("mov ecx, [esp+4] "); |
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27 asm("mov " __A_REG__ ", [ecx] "); |
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28 #ifdef __BARRIERS_NEEDED__ |
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29 asm("lock add dword ptr [esp], 0 "); |
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30 #endif |
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31 asm("ret "); |
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32 } |
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33 |
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34 |
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35 /** Write an 8/16/32 bit quantity with release semantics |
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36 |
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37 @param a Address of data to be written - must be naturally aligned |
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38 @param v The value to be written |
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39 @return The value written |
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40 */ |
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41 EXPORT_C __NAKED__ __TUintX__ __fname__(__e32_atomic_store_rel)(volatile TAny* /*a*/, __TUintX__ /*v*/) |
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42 { |
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43 asm("mov ecx, [esp+4] "); |
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44 asm("mov " __D_REG__ ", [esp+8] "); |
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45 asm("mov " __A_REG__ ", " __D_REG__ ); |
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46 asm(__LOCK__ "xchg [ecx], " __D_REG__ ); |
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47 asm("ret "); |
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48 } |
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49 |
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50 |
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51 /** Write an 8/16/32 bit quantity with full barrier semantics |
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52 |
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53 @param a Address of data to be written - must be naturally aligned |
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54 @param v The value to be written |
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55 @return The value written |
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56 */ |
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57 EXPORT_C __NAKED__ __TUintX__ __fname__(__e32_atomic_store_ord)(volatile TAny* /*a*/, __TUintX__ /*v*/) |
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58 { |
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59 __redir__(__e32_atomic_store_rel); |
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60 } |
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61 |
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62 |
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63 /** Write an 8/16/32 bit quantity to memory and return the original value of the memory. |
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64 Relaxed ordering. |
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65 |
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66 @param a Address of data to be written - must be naturally aligned |
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67 @param v The value to be written |
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68 @return The original value of *a |
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69 */ |
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70 EXPORT_C __NAKED__ __TUintX__ __fname__(__e32_atomic_swp_rlx)(volatile TAny* /*a*/, __TUintX__ /*v*/) |
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71 { |
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72 __redir__(__e32_atomic_swp_ord); |
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73 } |
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74 |
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75 |
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76 /** Write an 8/16/32 bit quantity to memory and return the original value of the memory. |
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77 Acquire semantics. |
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78 |
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79 @param a Address of data to be written - must be naturally aligned |
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80 @param v The value to be written |
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81 @return The original value of *a |
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82 */ |
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83 EXPORT_C __NAKED__ __TUintX__ __fname__(__e32_atomic_swp_acq)(volatile TAny* /*a*/, __TUintX__ /*v*/) |
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84 { |
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85 __redir__(__e32_atomic_swp_ord); |
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86 } |
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87 |
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88 |
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89 /** Write an 8/16/32 bit quantity to memory and return the original value of the memory. |
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90 Release semantics. |
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91 |
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92 @param a Address of data to be written - must be naturally aligned |
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93 @param v The value to be written |
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94 @return The original value of *a |
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95 */ |
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96 EXPORT_C __NAKED__ __TUintX__ __fname__(__e32_atomic_swp_rel)(volatile TAny* /*a*/, __TUintX__ /*v*/) |
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97 { |
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98 __redir__(__e32_atomic_swp_ord); |
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99 } |
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100 |
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101 |
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102 /** Write an 8/16/32 bit quantity to memory and return the original value of the memory. |
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103 Full barrier semantics. |
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104 |
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105 @param a Address of data to be written - must be naturally aligned |
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106 @param v The value to be written |
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107 @return The original value of *a |
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108 */ |
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109 EXPORT_C __NAKED__ __TUintX__ __fname__(__e32_atomic_swp_ord)(volatile TAny* /*a*/, __TUintX__ /*v*/) |
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110 { |
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111 asm("mov ecx, [esp+4] "); |
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112 asm("mov " __A_REG__ ", [esp+8] "); |
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113 asm(__LOCK__ "xchg [ecx], " __A_REG__ ); |
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114 asm("ret "); |
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115 } |
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116 |
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117 |
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118 /** 8/16/32 bit compare and swap, relaxed ordering. |
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119 |
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120 Atomically performs the following operation: |
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121 if (*a == *q) { *a = v; return TRUE; } |
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122 else { *q = *a; return FALSE; } |
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123 |
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124 @param a Address of data to be written - must be naturally aligned |
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125 @param q Address of location containing expected value |
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126 @param v The new value to be written if the old value is as expected |
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127 @return TRUE if *a was updated, FALSE otherwise |
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128 */ |
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129 EXPORT_C __NAKED__ TBool __fname__(__e32_atomic_cas_rlx)(volatile TAny* /*a*/, __TUintX__* /*q*/, __TUintX__ /*v*/) |
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130 { |
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131 __redir__(__e32_atomic_cas_ord); |
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132 } |
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133 |
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134 |
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135 /** 8/16/32 bit compare and swap, acquire semantics. |
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136 |
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137 Atomically performs the following operation: |
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138 if (*a == *q) { *a = v; return TRUE; } |
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139 else { *q = *a; return FALSE; } |
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140 |
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141 @param a Address of data to be written - must be naturally aligned |
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142 @param q Address of location containing expected value |
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143 @param v The new value to be written if the old value is as expected |
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144 @return TRUE if *a was updated, FALSE otherwise |
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145 */ |
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146 EXPORT_C __NAKED__ TBool __fname__(__e32_atomic_cas_acq)(volatile TAny* /*a*/, __TUintX__* /*q*/, __TUintX__ /*v*/) |
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147 { |
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148 __redir__(__e32_atomic_cas_ord); |
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149 } |
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150 |
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151 |
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152 /** 8/16/32 bit compare and swap, release semantics. |
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153 |
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154 Atomically performs the following operation: |
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155 if (*a == *q) { *a = v; return TRUE; } |
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156 else { *q = *a; return FALSE; } |
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157 |
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158 @param a Address of data to be written - must be naturally aligned |
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159 @param q Address of location containing expected value |
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160 @param v The new value to be written if the old value is as expected |
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161 @return TRUE if *a was updated, FALSE otherwise |
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162 */ |
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163 EXPORT_C __NAKED__ TBool __fname__(__e32_atomic_cas_rel)(volatile TAny* /*a*/, __TUintX__* /*q*/, __TUintX__ /*v*/) |
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164 { |
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165 __redir__(__e32_atomic_cas_ord); |
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166 } |
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167 |
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168 |
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169 /** 8/16/32 bit compare and swap, full barrier semantics. |
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170 |
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171 Atomically performs the following operation: |
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172 if (*a == *q) { *a = v; return TRUE; } |
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173 else { *q = *a; return FALSE; } |
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174 |
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175 @param a Address of data to be written - must be naturally aligned |
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176 @param q Address of location containing expected value |
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177 @param v The new value to be written if the old value is as expected |
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178 @return TRUE if *a was updated, FALSE otherwise |
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179 */ |
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180 EXPORT_C __NAKED__ TBool __fname__(__e32_atomic_cas_ord)(volatile TAny* /*a*/, __TUintX__* /*q*/, __TUintX__ /*v*/) |
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181 { |
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182 asm("mov ecx, [esp+4] "); |
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183 asm("mov eax, [esp+8] "); |
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184 asm("mov " __D_REG__ ", [esp+12] "); |
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185 asm("mov " __A_REG__ ", [eax] "); |
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186 asm(__LOCK__ "cmpxchg [ecx], " __D_REG__ ); |
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187 asm("jne short 2f "); |
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188 asm("mov eax, 1 "); |
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189 asm("ret "); |
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190 asm("2: "); |
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191 asm("mov edx, [esp+8] "); |
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192 asm("mov [edx], " __A_REG__ ); |
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193 asm("xor eax, eax "); |
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194 asm("ret "); |
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195 } |
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196 |
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197 |
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198 /** 8/16/32 bit atomic add, relaxed ordering. |
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199 |
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200 Atomically performs the following operation: |
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201 oldv = *a; *a = oldv + v; return oldv; |
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202 |
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203 @param a Address of data to be updated - must be naturally aligned |
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204 @param v The value to be added |
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205 @return The original value of *a |
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206 */ |
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207 EXPORT_C __NAKED__ __TUintX__ __fname__(__e32_atomic_add_rlx)(volatile TAny* /*a*/, __TUintX__ /*v*/) |
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208 { |
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209 __redir__(__e32_atomic_add_ord); |
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210 } |
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211 |
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212 |
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213 /** 8/16/32 bit atomic add, acquire semantics. |
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214 |
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215 Atomically performs the following operation: |
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216 oldv = *a; *a = oldv + v; return oldv; |
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217 |
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218 @param a Address of data to be updated - must be naturally aligned |
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219 @param v The value to be added |
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220 @return The original value of *a |
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221 */ |
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222 EXPORT_C __NAKED__ __TUintX__ __fname__(__e32_atomic_add_acq)(volatile TAny* /*a*/, __TUintX__ /*v*/) |
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223 { |
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224 __redir__(__e32_atomic_add_ord); |
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225 } |
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226 |
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227 |
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228 /** 8/16/32 bit atomic add, release semantics. |
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229 |
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230 Atomically performs the following operation: |
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231 oldv = *a; *a = oldv + v; return oldv; |
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232 |
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233 @param a Address of data to be updated - must be naturally aligned |
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234 @param v The value to be added |
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235 @return The original value of *a |
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236 */ |
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237 EXPORT_C __NAKED__ __TUintX__ __fname__(__e32_atomic_add_rel)(volatile TAny* /*a*/, __TUintX__ /*v*/) |
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238 { |
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239 __redir__(__e32_atomic_add_ord); |
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240 } |
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241 |
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242 |
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243 /** 8/16/32 bit atomic add, full barrier semantics. |
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244 |
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245 Atomically performs the following operation: |
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246 oldv = *a; *a = oldv + v; return oldv; |
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247 |
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248 @param a Address of data to be updated - must be naturally aligned |
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249 @param v The value to be added |
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250 @return The original value of *a |
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251 */ |
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252 EXPORT_C __NAKED__ __TUintX__ __fname__(__e32_atomic_add_ord)(volatile TAny* /*a*/, __TUintX__ /*v*/) |
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253 { |
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254 asm("mov ecx, [esp+4] "); |
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255 asm("mov " __A_REG__ ", [esp+8] "); |
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256 asm(__LOCK__ "xadd [ecx], " __A_REG__ ); |
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257 asm("ret "); |
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258 } |
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259 |
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260 |
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261 /** 8/16/32 bit atomic bitwise logical AND, relaxed ordering. |
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262 |
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263 Atomically performs the following operation: |
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264 oldv = *a; *a = oldv & v; return oldv; |
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265 |
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266 @param a Address of data to be updated - must be naturally aligned |
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267 @param v The value to be ANDed with *a |
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268 @return The original value of *a |
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269 */ |
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270 EXPORT_C __NAKED__ __TUintX__ __fname__(__e32_atomic_and_rlx)(volatile TAny* /*a*/, __TUintX__ /*v*/) |
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271 { |
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272 __redir__(__e32_atomic_and_ord); |
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273 } |
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274 |
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275 |
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276 /** 8/16/32 bit atomic bitwise logical AND, acquire semantics. |
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277 |
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278 Atomically performs the following operation: |
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279 oldv = *a; *a = oldv & v; return oldv; |
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280 |
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281 @param a Address of data to be updated - must be naturally aligned |
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282 @param v The value to be ANDed with *a |
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283 @return The original value of *a |
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284 */ |
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285 EXPORT_C __NAKED__ __TUintX__ __fname__(__e32_atomic_and_acq)(volatile TAny* /*a*/, __TUintX__ /*v*/) |
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286 { |
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287 __redir__(__e32_atomic_and_ord); |
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288 } |
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289 |
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290 |
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291 /** 8/16/32 bit atomic bitwise logical AND, release semantics. |
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292 |
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293 Atomically performs the following operation: |
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294 oldv = *a; *a = oldv & v; return oldv; |
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295 |
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296 @param a Address of data to be updated - must be naturally aligned |
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297 @param v The value to be ANDed with *a |
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298 @return The original value of *a |
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299 */ |
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300 EXPORT_C __NAKED__ __TUintX__ __fname__(__e32_atomic_and_rel)(volatile TAny* /*a*/, __TUintX__ /*v*/) |
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301 { |
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302 __redir__(__e32_atomic_and_ord); |
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303 } |
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304 |
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305 |
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306 /** 8/16/32 bit atomic bitwise logical AND, full barrier semantics. |
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307 |
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308 Atomically performs the following operation: |
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309 oldv = *a; *a = oldv & v; return oldv; |
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310 |
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311 @param a Address of data to be updated - must be naturally aligned |
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312 @param v The value to be ANDed with *a |
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313 @return The original value of *a |
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314 */ |
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315 EXPORT_C __NAKED__ __TUintX__ __fname__(__e32_atomic_and_ord)(volatile TAny* /*a*/, __TUintX__ /*v*/) |
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316 { |
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317 asm("mov ecx, [esp+4] "); |
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318 asm("mov " __A_REG__ ", [ecx] "); |
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319 asm("1: "); |
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320 asm("mov " __D_REG__ ", [esp+8] "); |
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321 asm("and " __D_REG__ ", " __A_REG__ ); |
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322 asm(__LOCK__ "cmpxchg [ecx], " __D_REG__ ); |
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323 asm("jne short 1b "); |
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324 asm("ret "); |
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325 } |
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326 |
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327 |
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328 /** 8/16/32 bit atomic bitwise logical inclusive OR, relaxed ordering. |
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329 |
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330 Atomically performs the following operation: |
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331 oldv = *a; *a = oldv | v; return oldv; |
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332 |
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333 @param a Address of data to be updated - must be naturally aligned |
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334 @param v The value to be ORed with *a |
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335 @return The original value of *a |
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336 */ |
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337 EXPORT_C __NAKED__ __TUintX__ __fname__(__e32_atomic_ior_rlx)(volatile TAny* /*a*/, __TUintX__ /*v*/) |
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338 { |
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339 __redir__(__e32_atomic_ior_ord); |
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340 } |
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341 |
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342 |
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343 /** 8/16/32 bit atomic bitwise logical inclusive OR, acquire semantics. |
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344 |
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345 Atomically performs the following operation: |
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346 oldv = *a; *a = oldv | v; return oldv; |
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347 |
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348 @param a Address of data to be updated - must be naturally aligned |
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349 @param v The value to be ORed with *a |
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350 @return The original value of *a |
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351 */ |
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352 EXPORT_C __NAKED__ __TUintX__ __fname__(__e32_atomic_ior_acq)(volatile TAny* /*a*/, __TUintX__ /*v*/) |
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353 { |
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354 __redir__(__e32_atomic_ior_ord); |
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355 } |
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356 |
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357 |
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358 /** 8/16/32 bit atomic bitwise logical inclusive OR, release semantics. |
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359 |
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360 Atomically performs the following operation: |
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361 oldv = *a; *a = oldv | v; return oldv; |
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362 |
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363 @param a Address of data to be updated - must be naturally aligned |
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364 @param v The value to be ORed with *a |
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365 @return The original value of *a |
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366 */ |
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367 EXPORT_C __NAKED__ __TUintX__ __fname__(__e32_atomic_ior_rel)(volatile TAny* /*a*/, __TUintX__ /*v*/) |
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368 { |
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369 __redir__(__e32_atomic_ior_ord); |
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370 } |
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371 |
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372 |
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373 /** 8/16/32 bit atomic bitwise logical inclusive OR, full barrier semantics. |
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374 |
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375 Atomically performs the following operation: |
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376 oldv = *a; *a = oldv | v; return oldv; |
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377 |
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378 @param a Address of data to be updated - must be naturally aligned |
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379 @param v The value to be ORed with *a |
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380 @return The original value of *a |
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381 */ |
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382 EXPORT_C __NAKED__ __TUintX__ __fname__(__e32_atomic_ior_ord)(volatile TAny* /*a*/, __TUintX__ /*v*/) |
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383 { |
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384 asm("mov ecx, [esp+4] "); |
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385 asm("mov " __A_REG__ ", [ecx] "); |
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386 asm("1: "); |
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387 asm("mov " __D_REG__ ", [esp+8] "); |
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388 asm("or " __D_REG__ ", " __A_REG__ ); |
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389 asm(__LOCK__ "cmpxchg [ecx], " __D_REG__ ); |
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390 asm("jne short 1b "); |
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391 asm("ret "); |
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392 } |
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393 |
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394 |
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395 /** 8/16/32 bit atomic bitwise logical exclusive OR, relaxed ordering. |
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396 |
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397 Atomically performs the following operation: |
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398 oldv = *a; *a = oldv ^ v; return oldv; |
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399 |
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400 @param a Address of data to be updated - must be naturally aligned |
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401 @param v The value to be XORed with *a |
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402 @return The original value of *a |
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403 */ |
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404 EXPORT_C __NAKED__ __TUintX__ __fname__(__e32_atomic_xor_rlx)(volatile TAny* /*a*/, __TUintX__ /*v*/) |
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405 { |
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406 __redir__(__e32_atomic_xor_ord); |
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407 } |
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408 |
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409 |
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410 /** 8/16/32 bit atomic bitwise logical exclusive OR, acquire semantics. |
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411 |
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412 Atomically performs the following operation: |
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413 oldv = *a; *a = oldv ^ v; return oldv; |
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414 |
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415 @param a Address of data to be updated - must be naturally aligned |
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416 @param v The value to be XORed with *a |
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417 @return The original value of *a |
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418 */ |
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419 EXPORT_C __NAKED__ __TUintX__ __fname__(__e32_atomic_xor_acq)(volatile TAny* /*a*/, __TUintX__ /*v*/) |
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420 { |
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421 __redir__(__e32_atomic_xor_ord); |
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422 } |
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423 |
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424 |
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425 /** 8/16/32 bit atomic bitwise logical exclusive OR, release semantics. |
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426 |
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427 Atomically performs the following operation: |
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428 oldv = *a; *a = oldv ^ v; return oldv; |
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429 |
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430 @param a Address of data to be updated - must be naturally aligned |
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431 @param v The value to be XORed with *a |
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432 @return The original value of *a |
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433 */ |
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434 EXPORT_C __NAKED__ __TUintX__ __fname__(__e32_atomic_xor_rel)(volatile TAny* /*a*/, __TUintX__ /*v*/) |
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435 { |
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436 __redir__(__e32_atomic_xor_ord); |
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437 } |
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438 |
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439 |
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440 /** 8/16/32 bit atomic bitwise logical exclusive OR, full barrier semantics. |
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441 |
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442 Atomically performs the following operation: |
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443 oldv = *a; *a = oldv ^ v; return oldv; |
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444 |
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445 @param a Address of data to be updated - must be naturally aligned |
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446 @param v The value to be XORed with *a |
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447 @return The original value of *a |
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448 */ |
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449 EXPORT_C __NAKED__ __TUintX__ __fname__(__e32_atomic_xor_ord)(volatile TAny* /*a*/, __TUintX__ /*v*/) |
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450 { |
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451 asm("mov ecx, [esp+4] "); |
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452 asm("mov " __A_REG__ ", [ecx] "); |
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453 asm("1: "); |
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454 asm("mov " __D_REG__ ", [esp+8] "); |
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455 asm("xor " __D_REG__ ", " __A_REG__ ); |
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456 asm(__LOCK__ "cmpxchg [ecx], " __D_REG__ ); |
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457 asm("jne short 1b "); |
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458 asm("ret "); |
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459 } |
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460 |
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461 |
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462 /** 8/16/32 bit atomic bitwise universal function, relaxed ordering. |
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463 |
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464 Atomically performs the following operation: |
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465 oldv = *a; *a = (oldv & u) ^ v; return oldv; |
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466 |
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467 @param a Address of data to be updated - must be naturally aligned |
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468 @param u The value to be ANDed with *a |
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469 @param v The value to be XORed with (*a&u) |
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470 @return The original value of *a |
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471 */ |
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472 EXPORT_C __NAKED__ __TUintX__ __fname__(__e32_atomic_axo_rlx)(volatile TAny* /*a*/, __TUintX__ /*u*/, __TUintX__ /*v*/) |
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473 { |
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474 __redir__(__e32_atomic_axo_ord); |
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475 } |
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476 |
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477 |
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478 /** 8/16/32 bit atomic bitwise universal function, acquire semantics. |
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479 |
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480 Atomically performs the following operation: |
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481 oldv = *a; *a = (oldv & u) ^ v; return oldv; |
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482 |
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483 @param a Address of data to be updated - must be naturally aligned |
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484 @param u The value to be ANDed with *a |
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485 @param v The value to be XORed with (*a&u) |
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486 @return The original value of *a |
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487 */ |
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488 EXPORT_C __NAKED__ __TUintX__ __fname__(__e32_atomic_axo_acq)(volatile TAny* /*a*/, __TUintX__ /*u*/, __TUintX__ /*v*/) |
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489 { |
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490 __redir__(__e32_atomic_axo_ord); |
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491 } |
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492 |
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493 |
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494 /** 8/16/32 bit atomic bitwise universal function, release semantics. |
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495 |
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496 Atomically performs the following operation: |
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497 oldv = *a; *a = (oldv & u) ^ v; return oldv; |
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498 |
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499 @param a Address of data to be updated - must be naturally aligned |
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500 @param u The value to be ANDed with *a |
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501 @param v The value to be XORed with (*a&u) |
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502 @return The original value of *a |
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503 */ |
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504 EXPORT_C __NAKED__ __TUintX__ __fname__(__e32_atomic_axo_rel)(volatile TAny* /*a*/, __TUintX__ /*u*/, __TUintX__ /*v*/) |
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505 { |
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506 __redir__(__e32_atomic_axo_ord); |
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507 } |
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508 |
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509 |
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510 /** 8/16/32 bit atomic bitwise universal function, full barrier semantics. |
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511 |
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512 Atomically performs the following operation: |
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513 oldv = *a; *a = (oldv & u) ^ v; return oldv; |
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514 |
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515 @param a Address of data to be updated - must be naturally aligned |
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516 @param u The value to be ANDed with *a |
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517 @param v The value to be XORed with (*a&u) |
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518 @return The original value of *a |
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519 */ |
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520 EXPORT_C __NAKED__ __TUintX__ __fname__(__e32_atomic_axo_ord)(volatile TAny* /*a*/, __TUintX__ /*u*/, __TUintX__ /*v*/) |
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521 { |
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522 asm("mov ecx, [esp+4] "); |
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523 asm("mov " __A_REG__ ", [ecx] "); |
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524 asm("1: "); |
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525 asm("mov " __D_REG__ ", [esp+8] "); |
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526 asm("and " __D_REG__ ", " __A_REG__ ); |
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527 asm("xor " __D_REG__ ", [esp+12] "); |
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528 asm(__LOCK__ "cmpxchg [ecx], " __D_REG__ ); |
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529 asm("jne short 1b "); |
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530 asm("ret "); |
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531 } |
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532 |
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533 |
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534 /** 8/16/32 bit threshold and add, unsigned, relaxed ordering. |
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535 |
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536 Atomically performs the following operation: |
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537 oldv = *a; if (oldv>=t) *a=oldv+u else *a=oldv+v; return oldv; |
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538 |
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539 @param a Address of data to be updated - must be naturally aligned |
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540 @param t The threshold to compare *a to (unsigned compare) |
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541 @param u The value to be added to *a if it is originally >= t |
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542 @param u The value to be added to *a if it is originally < t |
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543 @return The original value of *a |
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544 */ |
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545 EXPORT_C __NAKED__ __TUintX__ __fname__(__e32_atomic_tau_rlx)(volatile TAny* /*a*/, __TUintX__ /*t*/, __TUintX__ /*u*/, __TUintX__ /*v*/) |
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546 { |
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547 __redir__(__e32_atomic_tau_ord); |
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548 } |
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549 |
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550 |
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551 /** 8/16/32 bit threshold and add, unsigned, acquire semantics. |
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552 |
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553 Atomically performs the following operation: |
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554 oldv = *a; if (oldv>=t) *a=oldv+u else *a=oldv+v; return oldv; |
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555 |
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556 @param a Address of data to be updated - must be naturally aligned |
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557 @param t The threshold to compare *a to (unsigned compare) |
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558 @param u The value to be added to *a if it is originally >= t |
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559 @param u The value to be added to *a if it is originally < t |
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560 @return The original value of *a |
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561 */ |
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562 EXPORT_C __NAKED__ __TUintX__ __fname__(__e32_atomic_tau_acq)(volatile TAny* /*a*/, __TUintX__ /*t*/, __TUintX__ /*u*/, __TUintX__ /*v*/) |
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563 { |
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564 __redir__(__e32_atomic_tau_ord); |
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565 } |
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566 |
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567 |
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568 /** 8/16/32 bit threshold and add, unsigned, release semantics. |
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569 |
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570 Atomically performs the following operation: |
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571 oldv = *a; if (oldv>=t) *a=oldv+u else *a=oldv+v; return oldv; |
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572 |
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573 @param a Address of data to be updated - must be naturally aligned |
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574 @param t The threshold to compare *a to (unsigned compare) |
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575 @param u The value to be added to *a if it is originally >= t |
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576 @param u The value to be added to *a if it is originally < t |
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577 @return The original value of *a |
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578 */ |
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579 EXPORT_C __NAKED__ __TUintX__ __fname__(__e32_atomic_tau_rel)(volatile TAny* /*a*/, __TUintX__ /*t*/, __TUintX__ /*u*/, __TUintX__ /*v*/) |
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580 { |
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581 __redir__(__e32_atomic_tau_ord); |
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582 } |
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583 |
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584 |
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585 /** 8/16/32 bit threshold and add, unsigned, full barrier semantics. |
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586 |
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587 Atomically performs the following operation: |
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588 oldv = *a; if (oldv>=t) *a=oldv+u else *a=oldv+v; return oldv; |
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589 |
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590 @param a Address of data to be updated - must be naturally aligned |
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591 @param t The threshold to compare *a to (unsigned compare) |
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592 @param u The value to be added to *a if it is originally >= t |
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593 @param u The value to be added to *a if it is originally < t |
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594 @return The original value of *a |
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595 */ |
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596 EXPORT_C __NAKED__ __TUintX__ __fname__(__e32_atomic_tau_ord)(volatile TAny* /*a*/, __TUintX__ /*t*/, __TUintX__ /*u*/, __TUintX__ /*v*/) |
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597 { |
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598 asm("mov ecx, [esp+4] "); |
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599 asm("mov " __A_REG__ ", [ecx] "); |
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600 asm("1: "); |
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601 asm("mov " __D_REG__ ", [esp+12] "); |
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602 asm("cmp " __A_REG__ ", [esp+8] "); |
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603 asm("jae short 2f "); |
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604 asm("mov " __D_REG__ ", [esp+16] "); |
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605 asm("2: "); |
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606 asm("add " __D_REG__ ", " __A_REG__ ); |
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607 asm(__LOCK__ "cmpxchg [ecx], " __D_REG__ ); |
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608 asm("jne short 1b "); |
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609 asm("ret "); |
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610 } |
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611 |
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612 |
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613 /** 8/16/32 bit threshold and add, signed, relaxed ordering. |
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614 |
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615 Atomically performs the following operation: |
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616 oldv = *a; if (oldv>=t) *a=oldv+u else *a=oldv+v; return oldv; |
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617 |
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618 @param a Address of data to be updated - must be naturally aligned |
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619 @param t The threshold to compare *a to (signed compare) |
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620 @param u The value to be added to *a if it is originally >= t |
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621 @param u The value to be added to *a if it is originally < t |
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622 @return The original value of *a |
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623 */ |
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624 EXPORT_C __NAKED__ __TIntX__ __fname__(__e32_atomic_tas_rlx)(volatile TAny* /*a*/, __TIntX__ /*t*/, __TIntX__ /*u*/, __TIntX__ /*v*/) |
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625 { |
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626 __redir__(__e32_atomic_tas_ord); |
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627 } |
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628 |
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629 |
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630 /** 8/16/32 bit threshold and add, signed, acquire semantics. |
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631 |
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632 Atomically performs the following operation: |
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633 oldv = *a; if (oldv>=t) *a=oldv+u else *a=oldv+v; return oldv; |
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634 |
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635 @param a Address of data to be updated - must be naturally aligned |
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636 @param t The threshold to compare *a to (signed compare) |
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637 @param u The value to be added to *a if it is originally >= t |
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638 @param u The value to be added to *a if it is originally < t |
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639 @return The original value of *a |
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640 */ |
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641 EXPORT_C __NAKED__ __TIntX__ __fname__(__e32_atomic_tas_acq)(volatile TAny* /*a*/, __TIntX__ /*t*/, __TIntX__ /*u*/, __TIntX__ /*v*/) |
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642 { |
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643 __redir__(__e32_atomic_tas_ord); |
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644 } |
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645 |
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646 |
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647 /** 8/16/32 bit threshold and add, signed, release semantics. |
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648 |
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649 Atomically performs the following operation: |
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650 oldv = *a; if (oldv>=t) *a=oldv+u else *a=oldv+v; return oldv; |
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651 |
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652 @param a Address of data to be updated - must be naturally aligned |
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653 @param t The threshold to compare *a to (signed compare) |
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654 @param u The value to be added to *a if it is originally >= t |
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655 @param u The value to be added to *a if it is originally < t |
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656 @return The original value of *a |
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657 */ |
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658 EXPORT_C __NAKED__ __TIntX__ __fname__(__e32_atomic_tas_rel)(volatile TAny* /*a*/, __TIntX__ /*t*/, __TIntX__ /*u*/, __TIntX__ /*v*/) |
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659 { |
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660 __redir__(__e32_atomic_tas_ord); |
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661 } |
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662 |
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663 |
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664 /** 8/16/32 bit threshold and add, signed, full barrier semantics. |
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665 |
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666 Atomically performs the following operation: |
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667 oldv = *a; if (oldv>=t) *a=oldv+u else *a=oldv+v; return oldv; |
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668 |
|
669 @param a Address of data to be updated - must be naturally aligned |
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670 @param t The threshold to compare *a to (signed compare) |
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671 @param u The value to be added to *a if it is originally >= t |
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672 @param u The value to be added to *a if it is originally < t |
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673 @return The original value of *a |
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674 */ |
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675 EXPORT_C __NAKED__ __TIntX__ __fname__(__e32_atomic_tas_ord)(volatile TAny* /*a*/, __TIntX__ /*t*/, __TIntX__ /*u*/, __TIntX__ /*v*/) |
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676 { |
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677 asm("mov ecx, [esp+4] "); |
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678 asm("mov " __A_REG__ ", [ecx] "); |
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679 asm("1: "); |
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680 asm("mov " __D_REG__ ", [esp+12] "); |
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681 asm("cmp " __A_REG__ ", [esp+8] "); |
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682 asm("jge short 2f "); |
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683 asm("mov " __D_REG__ ", [esp+16] "); |
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684 asm("2: "); |
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685 asm("add " __D_REG__ ", " __A_REG__ ); |
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686 asm(__LOCK__ "cmpxchg [ecx], " __D_REG__ ); |
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687 asm("jne short 1b "); |
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688 asm("ret "); |
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689 } |
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690 |
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691 |