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1 // Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies). |
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2 // All rights reserved. |
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3 // This component and the accompanying materials are made available |
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4 // under the terms of the License "Eclipse Public License v1.0" |
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5 // which accompanies this distribution, and is available |
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6 // at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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7 // |
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8 // Initial Contributors: |
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9 // Nokia Corporation - initial contribution. |
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10 // |
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11 // Contributors: |
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12 // |
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13 // Description: |
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14 // e32\include\nkernsmp\arm\ncern.h |
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15 // |
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16 // WARNING: This file contains some APIs which are internal and are subject |
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17 // to change without notice. Such APIs should therefore not be used |
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18 // outside the Kernel and Hardware Services package. |
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19 // |
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20 |
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21 /** |
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22 @file |
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23 @publishedPartner |
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24 @prototype |
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25 */ |
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26 |
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27 #ifndef __NCERN_H__ |
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28 #define __NCERN_H__ |
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29 |
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30 #ifdef __FIQ_IS_UNCONTROLLED__ |
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31 #define __ASM_CLI() CPSIDI /* Disable all interrupts */ |
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32 #define __ASM_STI() CPSIEI /* Enable all interrupts */ |
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33 #define __ASM_CLI1() CPSIDI /* Disable IRQ only */ |
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34 #define __ASM_STI1() CPSIEI /* Enable IRQ only */ |
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35 #define __ASM_CLI2() /* Disable FIQ only */ |
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36 #define __ASM_STI2() /* Enable FIQ only */ |
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37 |
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38 #define __ASM_CLI_MODE(mode) CPSIDIM(mode) /* Disable all interrupts and change mode */ |
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39 #define __ASM_STI_MODE(mode) CPSIEIM(mode) /* Enable all interrupts and change mode */ |
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40 #define __ASM_CLI1_MODE(mode) CPSIDIM(mode) /* Disable IRQ only and change mode */ |
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41 #define __ASM_STI1_MODE(mode) CPSIEIM(mode) /* Enable IRQ only and change mode */ |
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42 #define __ASM_CLI2_MODE(mode) CPSCHM(mode) /* Disable FIQ only and change mode */ |
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43 #define __ASM_STI2_MODE(mode) CPSCHM(mode) /* Enable FIQ only and change mode */ |
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44 |
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45 #else |
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46 #define __ASM_CLI() CPSIDIF /* Disable all interrupts */ |
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47 #define __ASM_STI() CPSIEIF /* Enable all interrupts */ |
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48 #define __ASM_CLI1() CPSIDI /* Disable IRQ only */ |
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49 #define __ASM_STI1() CPSIEI /* Enable IRQ only */ |
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50 #define __ASM_CLI2() CPSIDF /* Disable FIQ only */ |
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51 #define __ASM_STI2() CPSIEF /* Enable FIQ only */ |
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52 |
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53 #define __ASM_CLI_MODE(mode) CPSIDIFM(mode) /* Disable all interrupts and change mode */ |
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54 #define __ASM_STI_MODE(mode) CPSIEIFM(mode) /* Enable all interrupts and change mode */ |
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55 #define __ASM_CLI1_MODE(mode) CPSIDIM(mode) /* Disable IRQ only and change mode */ |
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56 #define __ASM_STI1_MODE(mode) CPSIEIM(mode) /* Enable IRQ only and change mode */ |
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57 #define __ASM_CLI2_MODE(mode) CPSIDFM(mode) /* Disable FIQ only and change mode */ |
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58 #define __ASM_STI2_MODE(mode) CPSIEFM(mode) /* Enable FIQ only and change mode */ |
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59 #endif |
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60 |
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61 /** Information needed to boot an AP (ARM specific) |
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62 |
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63 @internalTechnology |
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64 */ |
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65 struct SArmAPBootInfo : public SAPBootInfo |
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66 { |
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67 TLinAddr iAPBootLin; // linear address of AP boot page (uncached) |
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68 T_UintPtr iAPBootPhys; // physical address of AP boot page (uncached) |
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69 TLinAddr iAPBootCodeLin; // linear address of AP boot code (part of bootstrap) |
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70 T_UintPtr iAPBootCodePhys; // physical address of AP boot code (part of bootstrap) |
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71 T_UintPtr iAPBootPageDirPhys; // physical address of AP boot page directory |
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72 TLinAddr iInitR13Fiq; // initial value for R13_fiq |
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73 TLinAddr iInitR13Irq; // initial value for R13_irq |
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74 TLinAddr iInitR13Abt; // initial value for R13_abt |
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75 TLinAddr iInitR13Und; // initial value for R13_und |
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76 }; |
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77 |
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78 |
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79 /** Timer frequency specification |
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80 |
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81 Stores a frequency as a fraction of a (separately stored) maximum. |
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82 The frequency must be at least 1/256 of the maximum. |
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83 |
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84 @internalTechnology |
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85 @prototype |
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86 */ |
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87 struct STimerMult |
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88 { |
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89 TUint32 iFreq; // frequency as a fraction of maximum possible, multiplied by 2^32 |
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90 TUint32 iInverse; // 2^24/(iFreq/2^32) = 2^56/iFreq |
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91 }; |
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92 |
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93 /** Variant interface block |
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94 @internalTechnology |
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95 @prototype |
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96 */ |
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97 struct SVariantInterfaceBlock : public SInterfaceBlockBase |
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98 { |
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99 TUint64 iMaxCpuClock; // maximum possible CPU clock frequency on this system |
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100 TUint16 iTimerGap1; |
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101 TUint16 iTimerGap2; |
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102 TUint32 iMaxTimerClock; // maximum possible local timer clock frequency |
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103 TLinAddr iScuAddr; // address of SCU |
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104 TLinAddr iGicDistAddr; // address of GIC Distributor |
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105 TLinAddr iGicCpuIfcAddr; // address of GIC CPU interface (must be same for all CPUs) |
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106 TLinAddr iLocalTimerAddr; // address of per-CPU timer (must be same for all CPUs) |
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107 volatile STimerMult* iTimerMult[KMaxCpus]; // timer[i] frequency / iMaxTimerClock * 2^32 |
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108 volatile TUint32* iCpuMult[KMaxCpus]; // CPU[i] frequency / iMaxCpuClock * 2^32 |
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109 }; |
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110 |
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111 // End of file |
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112 #endif |