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1 // Copyright (c) 1994-2009 Nokia Corporation and/or its subsidiary(-ies). |
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2 // All rights reserved. |
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3 // This component and the accompanying materials are made available |
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4 // under the terms of the License "Eclipse Public License v1.0" |
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5 // which accompanies this distribution, and is available |
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6 // at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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7 // |
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8 // Initial Contributors: |
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9 // Nokia Corporation - initial contribution. |
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10 // |
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11 // Contributors: |
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12 // |
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13 // Description: |
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14 // e32\kernel\arm\ckernel.cpp |
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15 // |
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16 // |
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17 |
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18 #include <arm_mem.h> |
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19 #include <arm_vfp.h> |
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20 |
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21 #define iMState iWaitLink.iSpare1 |
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22 #define iExiting iWaitLink.iSpare2 |
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23 |
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24 GLREF_C void __ArmVectorReset(); |
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25 GLREF_C void __ArmVectorUndef(); |
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26 GLREF_C void __ArmVectorSwi(); |
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27 GLREF_C void __ArmVectorAbortPrefetch(); |
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28 GLREF_C void __ArmVectorAbortData(); |
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29 GLREF_C void __ArmVectorReserved(); |
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30 GLREF_C void __ArmVectorIrq(); |
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31 GLREF_C void __ArmVectorFiq(); |
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32 |
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33 extern "C" void ExcFault(TAny* aExcInfo); |
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34 |
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35 /******************************************** |
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36 * Thread |
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37 ********************************************/ |
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38 |
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39 DArmPlatThread::~DArmPlatThread() |
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40 { |
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41 DThread::Destruct(); |
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42 } |
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43 |
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44 TInt DArmPlatThread::Context(TDes8& aDes) |
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45 { |
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46 TArmRegSet& s=*(TArmRegSet*)aDes.Ptr(); |
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47 aDes.SetLength(sizeof(s)); |
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48 TInt r=KErrNone; |
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49 if (iThreadType!=EThreadUser || this==TheCurrentThread) |
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50 r=KErrAccessDenied; |
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51 else if (iExiting) |
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52 r=KErrDied; |
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53 else |
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54 { |
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55 TUint32 unused; |
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56 NKern::ThreadGetUserContext(&iNThread,&s,unused); |
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57 } |
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58 return r; |
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59 } |
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60 |
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61 DProcess* P::NewProcess() |
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62 { |
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63 return new DArmPlatProcess; |
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64 } |
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65 |
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66 #ifdef __CPU_HAS_VFP |
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67 #ifdef __VFP_V3 |
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68 const TInt KVfpContextSize = (1 + (32 * 2)) * 4; // FPSCR + 32 dword registers |
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69 #else |
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70 const TInt KVfpContextSize = (3 + (16 * 2)) * 4; // FPSCR + FPINST + FPINST2 + 16 dword registers |
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71 #endif |
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72 #endif |
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73 TInt DArmPlatProcess::GetNewThread(DThread*& aThread, SThreadCreateInfo& aInfo) |
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74 // |
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75 // Create a new DArmPlatThread object |
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76 // If aThread=NULL on entry, allocate it on the kernel heap, |
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77 // otherwise do in-place construction. |
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78 // |
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79 { |
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80 DArmPlatThread* pT=(DArmPlatThread*)aThread; |
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81 if (!pT) |
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82 { |
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83 TInt size = sizeof(DArmPlatThread); |
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84 #ifdef __CPU_HAS_VFP |
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85 size += KVfpContextSize; |
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86 #endif |
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87 __KTRACE_OPT(KTHREAD,Kern::Printf("GetNewThread size=%04x",size)); |
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88 pT = (DArmPlatThread*)Kern::AllocZ(size); |
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89 } |
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90 if (!pT) |
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91 return KErrNoMemory; |
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92 new (pT) DArmPlatThread; |
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93 aThread = pT; |
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94 pT->iOwningProcess=this; |
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95 |
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96 #ifdef __CPU_HAS_VFP |
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97 pT->iNThread.iExtraContext = (TUint8*)pT + sizeof(DArmPlatThread); |
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98 *(TUint32*)(pT->iNThread.iExtraContext) = Arm::VfpDefaultFpScr; |
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99 // Inherit parent VFP FPSCR value if applicable |
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100 if ((TInt)aInfo.iType != (TInt)EThreadInitial) |
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101 { |
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102 if (pT->iOwningProcess == Kern::CurrentThread().iOwningProcess) |
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103 { |
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104 if (Arm::FpExc() & VFP_FPEXC_EN) |
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105 { |
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106 *(TUint32*)(pT->iNThread.iExtraContext) = Arm::FpScr() & VFP_FPSCR_MODE_MASK; |
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107 } |
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108 } |
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109 } |
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110 #endif |
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111 |
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112 return KErrNone; |
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113 } |
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114 |
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115 extern void DumpExcInfo(TArmExcInfo& a); |
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116 void DumpExcInfoX(TArmExcInfo& a) |
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117 { |
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118 DumpExcInfo(a); |
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119 NThread* nthread = NCurrentThread(); |
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120 if (nthread == NULL) |
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121 Kern::Printf("No current thread"); |
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122 else |
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123 { |
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124 DThread* thread = Kern::NThreadToDThread(NCurrentThread()); |
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125 if (thread) |
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126 { |
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127 TFullName thread_name; |
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128 thread->TraceAppendFullName(thread_name, EFalse); |
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129 Kern::Printf("Thread full name=%S", &thread_name); |
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130 Kern::Printf("Thread ID=%d, KernCSLocked=%d",TheCurrentThread->iId,NKern::KernelLocked()); |
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131 } |
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132 else |
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133 Kern::Printf("Thread N/A, KernCSLocked=%d",NKern::KernelLocked()); |
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134 } |
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135 } |
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136 |
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137 extern void DumpFullRegSet(SFullArmRegSet& a); |
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138 extern void GetUndefinedInstruction(TArmExcInfo* /*aContext*/); |
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139 extern void PushExcInfoOnUserStack(TArmExcInfo*, TInt); |
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140 extern "C" { |
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141 extern SFullArmRegSet DefaultRegSet; |
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142 } |
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143 |
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144 #ifdef __CPU_HAS_VFP |
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145 GLREF_C TInt HandleVFPOperation(TAny* aPtr); |
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146 #endif |
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147 |
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148 void Exc::Dispatch(TAny* aPtr, NThread*) |
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149 { |
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150 #ifdef __CPU_ARM_ABORT_MODEL_UPDATED |
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151 #error Processors implementing the 'Base Register Updated' Abort Model are no longer supported |
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152 #endif |
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153 |
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154 TArmExcInfo* pR=(TArmExcInfo*)aPtr; |
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155 TInt mode=pR->iCpsr & EMaskMode; |
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156 |
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157 TBool faultHandled = EFalse; |
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158 |
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159 #ifdef __DEMAND_PAGING__ |
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160 faultHandled |= M::DemandPagingFault(aPtr) == KErrNone; |
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161 #endif |
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162 |
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163 if(!faultHandled) |
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164 faultHandled |= M::RamDefragFault(aPtr) == KErrNone; |
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165 |
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166 if(faultHandled) |
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167 { |
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168 #ifdef __ATOMIC64_USE_SLOW_EXEC__ |
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169 if (mode==ESvcMode && pR->iExcCode==EArmExceptionDataAbort && IsMagicAtomic64(pR->iR15)) |
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170 { |
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171 // Magic atomic instruction so return to next instruction to stop any |
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172 // writes to memory being executed and ensure interrupts are enabled. |
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173 pR->iR15 += 4; |
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174 pR->iCpsr &= ~KAllInterruptsMask; |
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175 } |
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176 #endif |
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177 return; |
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178 } |
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179 |
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180 if (mode==ESvcMode && pR->iExcCode==EArmExceptionDataAbort && IsMagic(pR->iR15)) |
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181 { |
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182 // skip instruction that caused the exception, set the zero flag and place faulted address in r12 |
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183 __KTRACE_OPT(KPANIC,DumpExcInfoX(*pR)); |
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184 pR->iR15 += 4; |
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185 pR->iCpsr |= ECpuZf; |
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186 pR->iR12 = pR->iFaultAddress; |
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187 return; |
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188 } |
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189 |
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190 DThread* pT=TheCurrentThread; |
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191 TExcTrap* xt=pT->iExcTrap; |
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192 if (xt) |
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193 { |
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194 __KTRACE_OPT(KPANIC,DumpExcInfoX(*pR)); |
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195 // current thread wishes to handle exceptions |
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196 (*xt->iHandler)(xt,pT,aPtr); |
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197 } |
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198 |
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199 if (NKern::HeldFastMutex()) // thread held fast mutex when exception occurred |
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200 Exc::Fault(aPtr); |
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201 |
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202 #ifdef __CPU_HAS_VFP |
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203 if (pR->iExcCode==EArmExceptionUndefinedOpcode) |
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204 { |
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205 // Get the undefined instruction |
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206 GetUndefinedInstruction(pR); |
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207 |
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208 const TUint32 opcode = pR->iFaultAddress; |
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209 TInt cpnum = -1; |
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210 |
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211 #ifdef __SUPPORT_THUMB_INTERWORKING |
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212 if (!(pR->iCpsr & ECpuThumb)) { |
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213 #endif |
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214 // check for coprocessor instructions |
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215 // 10987654321098765432109876543210 |
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216 // CDP: cond1110op1 CRn CRd cp_#op20CRm |
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217 // LDC: cond110PUNW1Rn CRd cp_#offset |
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218 // STC: cond110PUNW0Rn CRd cp_#offset |
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219 // MRC: cond1110op11CRn Rd cp_#op21CRm |
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220 // MCR: cond1110op10CRn Rd cp_#op21CRm |
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221 // ext: cond11000x0xRn CRd cp_#offset |
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222 //CDP2: 11111110xxxxxxxxxxxxxxxxxxx0xxxx |
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223 //LDC2: 1111110xxxx1xxxxxxxxxxxxxxxxxxxx |
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224 //STC2: 1111110xxxx0xxxxxxxxxxxxxxxxxxxx |
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225 //MRC2: 11111110xxx1xxxxxxxxxxxxxxx1xxxx |
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226 //MCR2: 11111110xxx0xxxxxxxxxxxxxxx1xxxx |
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227 //MRRC: cond11100101Rn Rd cp_#opc CRm |
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228 //MCRR: cond11100100Rn Rd cp_#opc CRm |
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229 // |
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230 //NEON data processing: |
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231 // 1111001xxxxxxxxxxxxxxxxxxxxxxxxx |
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232 //NEON element/structure load/store: |
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233 // 11110100xxx0xxxxxxxxxxxxxxxxxxxx |
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234 // |
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235 // Coprocessor instructions have 2nd hex digit (bits 24-27) C,D,E. |
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236 // The coprocessor number is in bits 8-11. |
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237 // NEON instructions have 1st hex digits F2, F3, or F4x where x is even |
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238 // No coprocessor number, route to cp 10 |
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239 |
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240 TUint32 hex2 = (opcode>>24) & 0x0f; |
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241 |
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242 if (hex2==0xc || hex2==0xd || hex2==0xe) |
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243 cpnum=(opcode>>8)&0x0f; |
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244 #ifdef __CPU_ARMV7 |
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245 else if ((opcode>>28)==0xf && (hex2==2 || hex2==3 || (hex2==4 && ((opcode>>20)&1)==0))) |
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246 cpnum=VFP_CPID_S; |
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247 #endif |
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248 |
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249 #ifdef __SUPPORT_THUMB_INTERWORKING |
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250 } |
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251 #endif |
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252 #ifdef __CPU_ARMV7 |
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253 else |
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254 { |
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255 // Check for coprocessor instructions (thumb mode, so only first halfword) |
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256 // 5432109876543210 5432109876543210 |
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257 // CDP: 11101110op1 CRn CRd cp_#op20CRm |
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258 // LDC: 1110110PUNW1Rn CRd cp_#offset |
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259 // STC: 1110110PUNW0Rn CRd cp_#offset |
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260 // MRC: 11101110op11CRn Rd cp_#op21CRm |
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261 // MCR: 11101110op10CRn Rd cp_#op21CRm |
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262 // CDP2: 11111110xxxxxxxx xxxxxxxxxx0xxxxx |
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263 // LDC2: 1111110xxxx1xxxx xxxxxxxxxxxxxxxx |
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264 // STC2: 1111110xxxx0xxxx xxxxxxxxxxxxxxxx |
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265 // MRC2: 11111110xxx1xxxx xxxxxxxxxx1xxxxx |
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266 // MCR2: 11111110xxx0xxxx xxxxxxxxxx1xxxxx |
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267 // MRRC: 111011100101Rn Rd cp_#opc CRm |
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268 // MCRR: 111011100100Rn Rd cp_#opc CRm |
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269 // |
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270 // Operations starting 1111 are not currently valid for VFP/NEON |
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271 // but are handled here in case of future development or |
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272 // alternative coprocessors |
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273 // |
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274 // NEON data processing: |
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275 // 111x1111xxxxxxxx xxxxxxxxxxxxxxxx |
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276 // NEON element/structure load/store: |
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277 // 11111001xxx0xxxx xxxxxxxxxxxxxxxx |
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278 // |
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279 // Coprocessor instructions have first hex digit E or F |
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280 // and second C, D or E |
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281 // The coprocessor number is in bits 8-11 of the second halfword |
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282 // NEON instructions have first 2 hex digits EF, FF or F9 |
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283 // No coprocessor number, route to cp 10 |
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284 |
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285 const TUint32 hex12 = opcode >> 8; |
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286 |
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287 if ((hex12 & 0xe0) == 0xe0) |
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288 { |
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289 const TUint32 hex2 = hex12 & 0xf; |
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290 if (hex2 == 0xc || hex2 == 0xd || hex2 == 0xe) |
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291 { |
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292 TArmExcInfo nextInstruction = *pR; |
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293 nextInstruction.iR15 += 2; |
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294 GetUndefinedInstruction(&nextInstruction); |
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295 cpnum = (nextInstruction.iFaultAddress >> 8) & 0x0f; |
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296 } |
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297 else |
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298 { |
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299 if (hex12 == 0xef || hex12 == 0xf9 || hex12 == 0xff) |
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300 cpnum = VFP_CPID_S; |
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301 } |
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302 } |
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303 } |
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304 #endif // __CPU_ARMV7 |
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305 |
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306 if (cpnum >= 0) |
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307 { |
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308 __KTRACE_OPT(KEVENT,Kern::Printf("VFP Instruction %08x", opcode)); |
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309 TInt r = HandleVFPOperation(pR); |
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310 if (r==KErrNone) |
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311 return; |
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312 __KTRACE_OPT(KEVENT,Kern::Printf("VFP Instruction returned %d", r)); |
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313 } |
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314 } |
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315 #endif // __CPU_HAS_VFP |
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316 |
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317 NKern::LockSystem(); |
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318 if (pT->iThreadType==EThreadUser && mode==EUserMode) |
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319 { |
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320 TExcType type=(TExcType)12; |
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321 if (pT->IsExceptionHandled(type)) |
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322 { |
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323 pT->iFlags |= KThreadFlagLastChance; |
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324 NKern::UnlockSystem(); |
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325 |
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326 // tweak context to call exception handler |
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327 PushExcInfoOnUserStack(pR, type); |
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328 pR->iR15 = (TUint32)pT->iOwningProcess->iReentryPoint; |
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329 pR->iR4 = KModuleEntryReasonException; |
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330 #ifdef __SUPPORT_THUMB_INTERWORKING |
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331 pR->iCpsr &= ~ECpuThumb; |
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332 #endif |
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333 return; |
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334 } |
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335 } |
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336 // Fault system before attempting to signal kernel event handler as going to |
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337 // crash anyway so no point trying to handle the event. Also, stops |
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338 // D_EXC hanging system on crash of critical/permanent thread. |
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339 if (pT->iFlags & (KThreadFlagSystemCritical|KThreadFlagSystemPermanent)) |
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340 Exc::Fault(aPtr); |
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341 NKern::UnlockSystem(); |
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342 |
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343 TUint m = DKernelEventHandler::Dispatch(EEventHwExc, pR, NULL); |
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344 if (m & (TUint)DKernelEventHandler::EExcHandled) |
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345 return; |
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346 |
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347 // __KTRACE_OPT(KPANIC,DumpExcInfoX(*pR)); |
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348 DumpExcInfoX(*pR); |
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349 |
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350 // panic current thread |
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351 K::PanicKernExec(ECausedException); |
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352 } |
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353 |
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354 EXPORT_C void Exc::Fault(TAny* aExcInfo) |
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355 { |
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356 #ifdef __SMP__ |
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357 TSubScheduler* ss = &SubScheduler(); |
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358 if (!ss) |
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359 ss = &TheSubSchedulers[0]; |
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360 ss->i_ExcInfo = aExcInfo; |
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361 SFullArmRegSet* a = (SFullArmRegSet*)ss->i_Regs; |
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362 if (!a) |
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363 a = &DefaultRegSet; |
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364 #else |
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365 TheScheduler.i_ExcInfo = aExcInfo; |
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366 SFullArmRegSet* a = (SFullArmRegSet*)TheScheduler.i_Regs; |
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367 #endif |
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368 if (aExcInfo) |
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369 { |
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370 Arm::SaveState(*a); |
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371 Arm::UpdateState(*a, *(TArmExcInfo*)aExcInfo); |
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372 } |
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373 TExcInfo e; |
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374 e.iCodeAddress = (TAny*)a->iN.iR15; |
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375 e.iDataAddress = (TAny*)a->iB[0].iDFAR; |
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376 e.iExtraData = (TInt)a->iB[0].iDFSR; |
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377 // __KTRACE_OPT(KPANIC,DumpExcInfoX(*pR)); |
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378 DumpFullRegSet(*a); |
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379 TheSuperPage().iKernelExcId = a->iExcCode; |
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380 TheSuperPage().iKernelExcInfo = e; |
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381 Kern::Fault("Exception", K::ESystemException); |
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382 } |
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383 |
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384 extern "C" void ExcFault(TAny* aExcInfo) |
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385 { |
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386 Exc::Fault(aExcInfo); |
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387 } |
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388 |
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389 void DArmPlatThread::DoExit2() |
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390 { |
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391 #ifdef __CPU_HAS_VFP |
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392 for (TInt cpu = 0; cpu < NKern::NumberOfCpus(); cpu++) |
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393 { |
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394 // Ensure that if this thread object is re-used then it gets a fresh context |
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395 if (Arm::VfpThread[cpu] == &iNThread) |
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396 Arm::VfpThread[cpu] = NULL; |
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397 #ifndef __SMP__ |
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398 Arm::ModifyFpExc(VFP_FPEXC_EX | VFP_FPEXC_EN, 0); // Disable VFP here for unicore |
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399 #endif |
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400 } |
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401 #endif |
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402 } |
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403 |
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404 |
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405 /** Sets the function used to handle bounces from VFP hardware. |
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406 |
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407 Used by a VFP coprocessor support kernel extension to register its |
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408 bounce handler. |
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409 |
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410 @publishedPartner |
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411 @released |
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412 */ |
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413 EXPORT_C void Arm::SetVfpBounceHandler(TVfpBounceHandler aHandler) |
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414 { |
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415 Arm::VfpBounceHandler = aHandler; |
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416 } |
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417 |
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418 |
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419 /** Sets the default value of FPSCR in the VFP hardware. |
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420 |
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421 Used by a VFP coprocessor support kernel extension to enable a |
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422 better default mode than RunFast. |
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423 |
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424 @publishedPartner |
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425 @released |
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426 */ |
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427 EXPORT_C void Arm::SetVfpDefaultFpScr(TUint32 aFpScr) |
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428 { |
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429 #ifdef __CPU_HAS_VFP |
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430 VfpDefaultFpScr = aFpScr; |
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431 #endif |
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432 } |
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433 |
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434 |
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435 #ifdef __CPU_HAS_VFP |
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436 |
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437 #ifndef __SMP__ |
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438 extern void DoSaveVFP(void*); |
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439 #endif |
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440 extern void DoRestoreVFP(const void*); |
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441 |
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442 GLDEF_C TInt HandleVFPOperation(TAny* aPtr) |
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443 { |
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444 NThread* pC = NCurrentThread(); |
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445 |
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446 if (Arm::FpExc() & VFP_FPEXC_EN) |
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447 { |
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448 // Coprocessor already enabled so it must be a real exception |
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449 if (Arm::VfpBounceHandler) |
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450 return Arm::VfpBounceHandler((TArmExcInfo*)aPtr); |
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451 else |
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452 return KErrGeneral; |
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453 } |
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454 |
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455 NKern::Lock(); |
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456 |
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457 // Enable access for this thread, clear any exceptional condition |
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458 TUint32 oldFpExc = Arm::ModifyFpExc(VFP_FPEXC_EX, VFP_FPEXC_EN); |
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459 |
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460 #ifndef __SMP__ |
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461 if (Arm::VfpThread[0] != pC) |
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462 { |
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463 // Only for unicore - SMP explicitly saves the current context and disables VFP |
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464 // when a thread is descheduled in case it runs on a different core next time |
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465 if (Arm::VfpThread[0]) |
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466 { |
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467 DoSaveVFP(Arm::VfpThread[0]->iExtraContext); |
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468 Arm::VfpThread[0]->ModifyFpExc(VFP_FPEXC_EN, 0); // Take access away from previous thread |
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469 } |
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470 DoRestoreVFP(pC->iExtraContext); // Restore this thread's context |
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471 Arm::VfpThread[0] = pC; |
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472 } |
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473 #else |
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474 const TInt currentCpu = NKern::CurrentCpu(); |
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475 if (Arm::VfpThread[currentCpu] != pC) |
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476 { |
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477 DoRestoreVFP(pC->iExtraContext); // Restore this thread's context |
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478 Arm::VfpThread[currentCpu] = pC; |
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479 } |
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480 #endif |
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481 |
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482 // Put FPEXC back how it was in case there was a pending exception, but keep enable bit on |
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483 Arm::SetFpExc(oldFpExc | VFP_FPEXC_EN); |
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484 NKern::Unlock(); |
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485 |
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486 return KErrNone; |
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487 } |
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488 #endif // __CPU_HAS_VFP |
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489 |
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490 #ifdef _DEBUG |
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491 extern "C" void __FaultIpcClientNotNull() |
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492 { |
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493 K::Fault(K::EIpcClientNotNull); |
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494 } |
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495 #endif |