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1 // Copyright (c) 1994-2009 Nokia Corporation and/or its subsidiary(-ies). |
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2 // All rights reserved. |
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3 // This component and the accompanying materials are made available |
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4 // under the terms of the License "Eclipse Public License v1.0" |
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5 // which accompanies this distribution, and is available |
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6 // at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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7 // |
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8 // Initial Contributors: |
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9 // Nokia Corporation - initial contribution. |
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10 // |
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11 // Contributors: |
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12 // |
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13 // Description: |
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14 // e32\memmodel\epoc\moving\arm\xkernel.cia |
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15 // |
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16 // |
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17 |
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18 #include <e32cia.h> |
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19 #include <arm_mem.h> |
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20 |
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21 __NAKED__ void DArmPlatChunk::MoveHomePdes(TLinAddr /*aOldAddr*/, TLinAddr /*aNewAddr*/) |
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22 { |
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23 asm("mov r2, r2, lsr #20 "); // r2=pde index for new addr |
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24 asm("subs r2, r2, r1, lsr #20 "); // subtract pde index for old addr |
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25 __JUMP(eq,lr); // if zero, nothing to do |
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26 asm("ldr r1, [r0, #%a0]" : : "i" _FOFF(DMemModelChunk,iNumPdes)); |
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27 asm("cmp r1, #0 "); |
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28 __JUMP(eq,lr); // if chunk empty, nothing to do |
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29 asm("ldr r1, [r0, #%a0]" : : "i" _FOFF(DMemModelChunk,iHomePdes)); |
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30 asm("add r1, r1, r2, asl #2 "); // move home pde address |
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31 asm("str r1, [r0, #%a0]" : : "i" _FOFF(DMemModelChunk,iHomePdes)); |
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32 __JUMP(,lr); |
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33 } |
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34 |
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35 __NAKED__ void DArmPlatChunk::MoveCurrentPdes(TLinAddr /*aOldAddr*/, TLinAddr /*aNewAddr*/) |
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36 { |
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37 asm("mov r2, r2, lsr #20 "); // r2=pde index for new addr |
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38 asm("subs r2, r2, r1, lsr #20 "); // subtract pde index for old addr |
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39 __JUMP(eq,lr); // if zero, nothing to do |
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40 asm("ldr r1, [r0, #%a0]" : : "i" _FOFF(DMemModelChunk,iNumPdes)); |
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41 asm("cmp r1, #0 "); |
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42 __JUMP(eq,lr); // if chunk empty, nothing to do |
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43 asm("ldr r1, [r0, #%a0]" : : "i" _FOFF(DMemModelChunk,iPdes)); |
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44 asm("add r1, r1, r2, asl #2 "); // move current pde address |
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45 asm("str r1, [r0, #%a0]" : : "i" _FOFF(DMemModelChunk,iPdes)); |
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46 __JUMP(,lr); |
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47 } |
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48 |
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49 __NAKED__ void DArmPlatChunk::AddPde(TInt /*aOffset*/) |
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50 { |
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51 asm("mov r1, r1, lsr #20 "); // r1=pde number |
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52 asm("ldr r2, [r0, #%a0]" : : "i" _FOFF(DMemModelChunk,iMaxSize)); |
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53 asm("cmp r2, #0x02000000 "); |
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54 asm("ldr r3, [r0, #%a0]" : : "i" _FOFF(DMemModelChunk,iPdeBitMap)); |
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55 asm("bhi add_pde_large "); |
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56 asm("mov ip, #1 "); |
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57 asm("orr r3, r3, ip, lsl r1 "); // set bit in bitmap |
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58 asm("str r3, [r0, #%a0]" : : "i" _FOFF(DMemModelChunk,iPdeBitMap)); |
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59 asm("b scan_small_bitmap "); |
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60 |
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61 asm("add_pde_large: "); |
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62 asm("stmfd sp!, {r4,lr} "); |
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63 asm("mov lr, r1, lsr #5 "); // lr=word number in bitmap |
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64 asm("and r1, r1, #31 "); // r1=bit number in word |
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65 asm("ldr r4, [r3, lr, lsl #2] "); |
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66 asm("mov ip, #1 "); |
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67 asm("orr r4, r4, ip, lsl r1 "); |
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68 asm("str r4, [r3, lr, lsl #2] "); // set bit in bitmap |
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69 asm("b scan_large_bitmap "); |
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70 } |
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71 |
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72 __NAKED__ void DArmPlatChunk::RemovePde(TInt /*anOffset*/) |
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73 { |
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74 asm("mov r1, r1, lsr #20 "); // r1=pde number |
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75 asm("ldr r2, [r0, #%a0]" : : "i" _FOFF(DMemModelChunk,iMaxSize)); |
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76 asm("cmp r2, #0x02000000 "); |
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77 asm("ldr r3, [r0, #%a0]" : : "i" _FOFF(DMemModelChunk,iPdeBitMap)); |
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78 asm("bhi rem_pde_large "); |
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79 asm("mov ip, #1 "); |
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80 asm("bics r3, r3, ip, lsl r1 "); // clear bit in bitmap |
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81 asm("str r3, [r0, #%a0]" : : "i" _FOFF(DMemModelChunk,iPdeBitMap)); |
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82 asm("beq empty_chunk "); // if chunk empty, skip rest |
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83 |
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84 asm("scan_small_bitmap: "); // r3 contains nonzero bitmap |
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85 #ifdef __CPU_ARM_HAS_CLZ |
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86 asm("sub r2, r3, #1 "); // ip will hold index of first pde |
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87 asm("eor r2, r2, r3 "); |
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88 CLZ(12,2); |
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89 asm("rsb r12, r12, #31 "); |
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90 asm("mov r3, r3, lsr r12 "); // shift bitmap so bit 0 set |
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91 CLZ(1, 3); |
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92 asm("rsb r1, r1, #32 "); // r1 will be 1+most significant 1 in r3 |
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93 #else |
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94 asm("mov ip, #0 "); // ip will hold index of first pde |
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95 asm("movs r2, r3, lsl #16 "); // test if bottom 16 bits zero |
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96 asm("moveq r3, r3, lsr #16 "); // if bottom 16 zero, shift right by 16 |
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97 asm("addeq ip, ip, #16 "); // and add 16 to lsb index |
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98 asm("tst r3, #0xff "); |
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99 asm("moveq r3, r3, lsr #8 "); |
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100 asm("addeq ip, ip, #8 "); |
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101 asm("tst r3, #0x0f "); |
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102 asm("moveq r3, r3, lsr #4 "); |
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103 asm("addeq ip, ip, #4 "); |
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104 asm("tst r3, #0x03 "); |
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105 asm("moveq r3, r3, lsr #2 "); |
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106 asm("addeq ip, ip, #2 "); |
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107 asm("tst r3, #0x01 "); |
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108 asm("moveq r3, r3, lsr #1 "); |
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109 asm("addeq ip, ip, #1 "); // ip=number of right shifts applied, r3 bit 0 set |
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110 asm("mov r1, #32 "); // r1 will be 1+most significant 1 in r3 |
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111 asm("cmp r3, #0x00010000 "); |
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112 asm("movcc r3, r3, lsl #16 "); |
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113 asm("subcc r1, r1, #16 "); |
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114 asm("cmp r3, #0x01000000 "); |
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115 asm("movcc r3, r3, lsl #8 "); |
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116 asm("subcc r1, r1, #8 "); |
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117 asm("cmp r3, #0x10000000 "); |
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118 asm("movcc r3, r3, lsl #4 "); |
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119 asm("subcc r1, r1, #4 "); |
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120 asm("cmp r3, #0x40000000 "); |
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121 asm("movcc r3, r3, lsl #2 "); |
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122 asm("subcc r1, r1, #2 "); |
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123 asm("cmp r3, #0x80000000 "); |
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124 asm("movcc r3, r3, lsl #1 "); |
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125 asm("subcc r1, r1, #1 "); |
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126 #endif |
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127 |
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128 asm("scan_bitmap_end: "); |
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129 asm("str r1, [r0, #%a0]" : : "i" _FOFF(DMemModelChunk,iNumPdes)); // r1 gives number of PDEs in range |
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130 asm("ldr r2, [r0, #%a0]" : : "i" _FOFF(DMemModelChunk,iBase)); |
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131 asm("add r2, ip, r2, lsr #20 "); // r2=pde index of first current pde |
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132 asm("mov r2, r2, lsl #2 "); |
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133 asm("add r2, r2, #%a0" : : "i" ((TInt)KPageDirectoryBase)); // r2->first current pde |
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134 asm("str r2, [r0, #%a0]" : : "i" _FOFF(DMemModelChunk,iPdes)); |
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135 asm("ldr r2, [r0, #%a0]" : : "i" _FOFF(DMemModelChunk,iHomeBase)); |
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136 asm("add r2, ip, r2, lsr #20 "); // r2=pde index of first home pde |
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137 asm("mov r2, r2, lsl #2 "); |
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138 asm("add r2, r2, #%a0" : : "i" ((TInt)KPageDirectoryBase)); // r2->first home pde |
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139 asm("str r2, [r0, #%a0]" : : "i" _FOFF(DMemModelChunk,iHomePdes)); |
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140 __JUMP(,lr); |
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141 |
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142 asm("empty_chunk: "); |
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143 asm("mov r1, #0 "); |
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144 asm("str r1, [r0, #%a0]" : : "i" _FOFF(DMemModelChunk,iNumPdes)); |
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145 asm("str r1, [r0, #%a0]" : : "i" _FOFF(DMemModelChunk,iPdes)); |
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146 asm("str r1, [r0, #%a0]" : : "i" _FOFF(DMemModelChunk,iHomePdes)); |
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147 __JUMP(,lr); |
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148 |
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149 asm("rem_pde_large: "); |
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150 asm("stmfd sp!, {r4,lr} "); |
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151 asm("mov lr, r1, lsr #5 "); // lr=word number in bitmap |
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152 asm("and r1, r1, #31 "); // r1=bit number in word |
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153 asm("ldr r4, [r3, lr, lsl #2] "); |
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154 asm("mov ip, #1 "); |
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155 asm("bic r4, r4, ip, lsl r1 "); |
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156 asm("str r4, [r3, lr, lsl #2] "); // set bit in bitmap |
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157 |
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158 asm("scan_large_bitmap: "); |
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159 // r0=this, r2=max size, r3->pde bit map |
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160 asm("add r2, r2, #0x1f00000 "); |
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161 asm("mov r2, r2, lsr #25 "); // r2=number of words in bitmap |
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162 asm("add r2, r3, r2, lsl #2 "); // r2=bitmap end address |
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163 asm("mov r4, r3 "); // save bitmap start address |
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164 |
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165 asm("scan_large_1: "); |
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166 asm("ldr ip, [r3], #4 "); |
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167 asm("cmp ip, #0 "); |
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168 asm("bne scan_large_2 "); // found non-empty word |
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169 asm("cmp r3, r2 "); |
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170 asm("bne scan_large_1 "); // if not reached end, do next word |
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171 asm("ldmfd sp!, {r4,lr} "); |
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172 asm("b empty_chunk "); // branch if no bits set |
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173 |
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174 asm("scan_large_2: "); |
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175 asm("sub r1, r3, r4 "); |
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176 asm("sub r1, r1, #4 "); |
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177 asm("mov r1, r1, lsl #3 "); // r1=bit number of lsb of this word |
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178 #ifdef __CPU_ARM_HAS_CLZ |
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179 asm("sub lr, ip, #1 "); // ip will hold index of first pde |
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180 asm("eor ip, lr, ip "); |
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181 CLZ(12, 12); |
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182 asm("rsb ip, ip, #31 "); |
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183 asm("add r1, r1, ip "); // r1 now = first occupied pde offset |
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184 #else |
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185 asm("movs lr, ip, lsl #16 "); |
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186 asm("moveq ip, ip, lsr #16 "); |
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187 asm("addeq r1, r1, #16 "); |
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188 asm("tst ip, #0xff "); |
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189 asm("moveq ip, ip, lsr #8 "); |
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190 asm("addeq r1, r1, #8 "); |
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191 asm("tst ip, #0x0f "); |
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192 asm("moveq ip, ip, lsr #4 "); |
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193 asm("addeq r1, r1, #4 "); |
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194 asm("tst ip, #0x03 "); |
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195 asm("moveq ip, ip, lsr #2 "); |
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196 asm("addeq r1, r1, #2 "); |
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197 asm("tst ip, #0x01 "); |
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198 asm("moveq ip, ip, lsr #1 "); |
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199 asm("addeq r1, r1, #1 "); // r1 now = first occupied pde offset |
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200 #endif |
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201 |
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202 asm("scan_large_3: "); |
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203 asm("ldr ip, [r2, #-4]! "); // fetch words from end of bitmap |
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204 asm("cmp ip, #0 "); |
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205 asm("beq scan_large_3 "); // we know there is at least one non-zero word |
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206 asm("sub r2, r2, r4 "); |
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207 asm("mov r2, r2, lsl #3 "); // r2=bit number of lsb of this word |
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208 #ifdef __CPU_ARM_HAS_CLZ |
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209 CLZ(12, 12); |
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210 asm("rsb ip, ip, #31 "); |
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211 asm("add r2, r2, ip "); // r2 now = last occupied pde offset |
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212 #else |
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213 asm("movs lr, ip, lsr #16 "); |
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214 asm("movne ip, lr "); |
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215 asm("addne r2, r2, #16 "); |
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216 asm("movs lr, ip, lsr #8 "); |
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217 asm("movne ip, lr "); |
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218 asm("addne r2, r2, #8 "); |
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219 asm("movs lr, ip, lsr #4 "); |
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220 asm("movne ip, lr "); |
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221 asm("addne r2, r2, #4 "); |
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222 asm("movs lr, ip, lsr #2 "); |
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223 asm("movne ip, lr "); |
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224 asm("addne r2, r2, #2 "); |
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225 asm("movs lr, ip, lsr #1 "); |
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226 asm("movne ip, lr "); |
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227 asm("addne r2, r2, #1 "); // r2 now = last occupied pde offset |
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228 #endif |
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229 asm("sub r3, r2, r1 "); // r3=last-first |
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230 asm("mov ip, r1 "); // ip=first |
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231 asm("add r1, r3, #1 "); // r1 = number of pdes in range |
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232 asm("ldmfd sp!, {r4,lr} "); |
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233 asm("b scan_bitmap_end "); // go back to set pde info |
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234 } |
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235 |
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236 __NAKED__ TBool Exc::IsMagic(TLinAddr /*anAddress*/) |
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237 // |
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238 // Return TRUE if anAddress is a 'magic' exception handling instruction |
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239 // |
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240 { |
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241 asm("adr r1, __magic_addresses "); // r1 points to list of magic addresses |
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242 asm("is_magic_1: "); |
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243 asm("ldr r2, [r1], #4 "); // r2=next magic address to check |
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244 asm("cmp r2, r0 "); // is r0=magic address? |
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245 asm("cmpne r2, #0 "); // if not, have we reached end of list? |
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246 asm("bne is_magic_1 "); // if neither, check next address |
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247 asm("movs r0, r2 "); // r0=0 if not magic, r0 unchanged if magic |
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248 __JUMP(,lr); |
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249 |
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250 asm("__magic_addresses: "); |
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251 asm(".word __magic_address_kusaferead "); |
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252 asm(".word __magic_address_saferead "); |
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253 asm(".word __magic_address_kusafewrite "); |
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254 asm(".word __magic_address_safewrite "); |
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255 asm(".word __magic_address_msg_lookup_1 "); // in preprocess handler |
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256 asm(".word __magic_address_readdesheader1 "); |
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257 asm(".word __magic_address_readdesheader2 "); |
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258 asm(".word __magic_address_readdesheader3 "); |
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259 #ifdef __MESSAGE_MACHINE_CODED_2__ |
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260 asm(".word __magic_address_msg_lookup_2 "); |
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261 #endif |
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262 #ifdef __CLIENT_REQUEST_MACHINE_CODED__ |
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263 asm(".word __magic_address_client_request_callback"); |
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264 asm(".word __magic_address_svr_accept_1 "); |
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265 asm(".word __magic_address_svr_accept_2 "); |
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266 asm(".word __magic_address_svr_accept_3 "); |
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267 asm(".word __magic_address_svr_accept_4 "); |
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268 asm(".word __magic_address_svr_accept_5 "); |
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269 asm(".word __magic_address_svr_accept_6 "); |
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270 asm(".word __magic_address_svr_accept_7 "); |
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271 asm(".word __magic_address_svr_accept_8 "); |
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272 #endif |
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273 #ifdef __REQUEST_COMPLETE_MACHINE_CODED__ |
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274 asm(".word __magic_address_reqc "); |
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275 asm(".word __magic_address_kern_request_complete "); |
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276 #endif |
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277 // list terminator |
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278 asm(".word 0 "); |
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279 } |
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280 |
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281 __NAKED__ TAny* MM::CurrentAddress(DThread* /*aThread*/, const TAny* /*aPtr*/, TInt /*aSize*/, TBool /*aWrite*/) |
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282 // |
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283 // Return the current base address corresponding to run address region |
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284 // aPtr to aPtr+aBase-1 in the context of aThread. |
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285 // aWrite indicates whether the address is intended for writing (aWrite=TRUE) or reading (aWrite=FALSE). |
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286 // Return NULL if the address range is not all accessible to aThread for access type specified by aWrite. |
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287 // aWrite=FALSE allows access to the ROM and RAM-loaded code chunks whereas aWrite=TRUE disallows these. |
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288 // NOTE THIS FUNCTION CONTAINS KNOWLEDGE OF FIXED LINEAR ADDRESSES (the RAM drive and HIVECS area). |
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289 // |
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290 // ALLERT! the ip register returns a pointer to the chunk which contains the addresses (null if none) |
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291 // |
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292 { |
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293 asm("CurrentAddress:"); |
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294 asm("ldr r0, [r0, #%a0]" : : "i" _FOFF(DThread, iOwningProcess)); |
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295 asm("stmfd sp!, {r4,r5,lr} "); |
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296 asm("eor r4, r1, #0x40000000 "); // r4<0x20000000u for RAM drive |
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297 asm("cmp r4, #0x20000000 "); // Check for RAM drive - ASSUMES RAM DRIVE IS AT 40000000-5FFFFFFF |
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298 asm("ldr lr, [r0, #%a0]!" : : "i" _FOFF(DMemModelProcess, iNumChunks)); // step r0 on to iChunks[0] |
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299 asm("bcc lookup_chunk_3 "); // branch if RAM drive |
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300 asm("subs lr, lr, #1 "); |
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301 asm("bcc lookup_chunk_2 "); // no chunks so do read check |
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302 asm("lookup_chunk_1: "); |
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303 asm("ldmib r0!, {r4,ip} "); // r4=data section base, ip=chunk ptr |
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304 asm("add r0, r0, #4 "); // move to next entry |
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305 asm("subs r4, r1, r4 "); // r4=offset |
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306 asm("ldrcs r5, [ip, #%a0]" : : "i" _FOFF(DChunk,iMaxSize)); // if offset>=0, r5=chunk max size |
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307 asm("cmpcs r4, r5 "); // and compare offset to max size |
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308 asm("subcss lr, lr, #1 "); // if offset>=max size, decrement counter |
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309 asm("bcs lookup_chunk_1 "); // loop if more chunks to check |
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310 asm("cmp lr, #0 "); // did we find chunk? |
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311 asm("ldrge r0, [ip, #%a0]" : : "i" _FOFF(DMemModelChunk,iHomeRegionOffset)); |
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312 asm("ldrge r5, [ip, #%a0]" : : "i" _FOFF(DMemModelChunk,iHomeRegionSize)); |
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313 asm("ldrge lr, [ip, #%a0]" : : "i" _FOFF(DChunk,iBase)); |
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314 asm("cmpge r4, r0 "); // if chunk not found or offset<iHomeRegionOffset, do read check |
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315 asm("blt lookup_chunk_2 "); |
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316 asm("add r0, r0, r5 "); // r0=home region offset+home region size |
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317 asm("add r5, r4, r2 "); // r5=offset after end of block |
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318 asm("cmp r5, r0 "); // check if offset after end<=iHomeRegionOffset+iHomeRegionSize |
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319 asm("addle r0, lr, r4 "); // if so, r0=current chunk base + offset |
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320 asm("ldmlefd sp!, {r4,r5,pc} "); // and we are done |
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321 |
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322 asm("lookup_chunk_2: "); // come here if address not found in a chunk |
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323 asm("mov ip, #0"); // ip = 0 to indicate chunk not found |
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324 asm("ldr r4, __code_limit "); |
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325 asm("mov r0, #0 "); |
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326 asm("cmn r1, #0x00100000 "); // address in hivecs area? |
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327 asm("ldr r4, [r4] "); // r4 = lowest legitimate code address |
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328 asm("ldmcsfd sp!, {r4,r5,pc} "); // if in hivecs, return NULL |
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329 asm("cmp r3, #0 "); // is this address intended for writing? |
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330 asm("ldmnefd sp!, {r4,r5,pc} "); // if it is, return NULL |
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331 asm("cmp r1, r4 "); // check if address is in RAM-loaded code or ROM |
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332 asm("ldmccfd sp!, {r4,r5,pc} "); // if not, return NULL |
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333 asm("adds r4, r1, r2 "); // r4 = end address of requested region |
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334 asm("ldmcsfd sp!, {r4,r5,pc} "); // if it wrapped, return NULL |
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335 asm("cmn r4, #0x100000 "); // if it didn't wrap, check if it reaches into hivecs area |
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336 asm("movls r0, r1 "); // if not, addr is OK for reading |
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337 asm("ldmfd sp!, {r4,r5,pc} "); |
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338 |
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339 asm("lookup_chunk_3: "); // come here if address in RAM drive |
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340 asm("mov ip, #0"); // ip = 0 to indicate chunk not found |
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341 asm("ldr r3, __f32 "); // r3=&K::TheFileServerProcess |
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342 asm("sub r4, r0, #%a0" : : "i" _FOFF(DMemModelProcess, iNumChunks)); // r4=aThread->iOwningProcess |
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343 asm("mov r0, #0 "); |
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344 asm("ldr r3, [r3] "); // r3=K::TheFileServerProcess |
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345 asm("add r5, r1, r2 "); // r5=end address of requested region + 1 |
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346 asm("cmp r5, #0x60000000 "); // is this past the end of the RAM drive? ASSUMES ADDRESS OF RAM DRIVE |
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347 asm("cmpls r3, r4 "); // if not, is aThread part of F32? |
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348 asm("moveq r0, r1 "); // if it is, allow the access and return the address unaltered |
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349 asm("ldmfd sp!, {r4,r5,pc} "); // else return NULL |
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350 |
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351 asm("__f32: "); |
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352 asm(".word " CSM_ZN1K20TheFileServerProcessE ); |
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353 asm("__code_limit: "); |
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354 asm(".word %a0" : : "i" ((TInt)&::TheMmu.iUserCodeBase) ); |
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355 } |
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356 |