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1 // Copyright (c) 1995-2009 Nokia Corporation and/or its subsidiary(-ies). |
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2 // All rights reserved. |
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3 // This component and the accompanying materials are made available |
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4 // under the terms of the License "Eclipse Public License v1.0" |
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5 // which accompanies this distribution, and is available |
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6 // at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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7 // |
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8 // Initial Contributors: |
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9 // Nokia Corporation - initial contribution. |
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10 // |
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11 // Contributors: |
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12 // |
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13 // Description: |
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14 // e32test\iic\t_iic.h |
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15 // |
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16 |
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17 #ifndef __T_IIC_H__ |
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18 #define __T_IIC_H__ |
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19 |
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20 |
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21 const TInt KIicClientMajorVersionNumber = 1; |
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22 const TInt KIicClientMinorVersionNumber = 0; |
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23 const TInt KIicClientBuildVersionNumber = KE32BuildVersionNumber; |
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24 |
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25 const TInt KPriorityTestNum = 6; // 1 blocking transaction + 5 test transactions |
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26 |
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27 // For IIC, |
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28 // If bit 31 is set and bit 30 cleared it is used to extend the Master-Slave channel; |
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29 // if bit 31 is cleared and bit 30 is set, it extends the Master channel; |
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30 // if both bits 31 and 30 are cleared it extends the Slave channel interface. |
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31 // However, |
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32 // since the kernel-side proxy clients interpret the msb being set as indicative of an |
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33 // asynchronous request, the values here will have the static extension pattern represented |
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34 // in bits 30 and 29, instead. In addition, to support communication with the slave-side proxy, |
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35 // the Slave extension value will be represented as bits 30 and 29 set, so that it can be distinguished |
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36 // from 'normal' synchronous operations. |
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37 // |
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38 const TUint KTestControlIoMask = 0x60000000; |
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39 const TUint KTestMasterControlIo = 0x20000000; |
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40 const TUint KTestSlaveControlIo = 0x60000000; |
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41 const TUint KTestMasterSlaveControlIo = 0x40000000; |
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42 const TUint KTestControlIoPilOffset = 0x00000002; // Corresponds to 1 higher than the number used by PIL |
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43 const TUint KTestControlUnitTestOffset = 0x10000000; |
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44 |
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45 // |
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46 // Enumerations TReqType and TBusType defined in kernel-side class TIicBusTransfer |
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47 // The user-side test, and the kernel-side proxy client require access to this |
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48 enum TReqType |
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49 { |
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50 EMasterRead, |
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51 EMasterWrite |
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52 }; |
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53 enum TBusType |
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54 { |
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55 EI2c = 0, |
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56 ESpi = 0x01, |
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57 EMicrowire = 0x02, |
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58 ECci = 0x03, |
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59 ESccb = 0x04, |
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60 EInvalidBus |
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61 }; |
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62 |
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63 #define MAX_TRANS_LENGTH 20 |
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64 |
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65 |
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66 #ifndef __KERNEL_MODE__ |
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67 // |
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68 // For convenience, selected kernel-side information is replicated here |
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69 // to allow the user-side test to populate buffers accordingly |
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70 // |
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71 // Bus-specific configuration |
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72 // |
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73 enum TEndianness |
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74 { |
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75 EBigEndian, |
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76 ELittleEndian |
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77 }; |
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78 |
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79 enum TBitOrder |
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80 { |
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81 ELsbFirst, |
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82 EMsbFirst |
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83 }; |
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84 |
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85 // |
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86 // Bus-specific configuration for SPI bus |
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87 // |
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88 |
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89 enum TSpiWordWidth |
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90 { |
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91 ESpiWordWidth_8, |
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92 ESpiWordWidth_10, |
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93 ESpiWordWidth_12, |
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94 ESpiWordWidth_16 |
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95 }; |
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96 |
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97 enum TSpiClkMode |
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98 { |
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99 ESpiPolarityLowRisingEdge, // Active high, odd edges |
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100 ESpiPolarityLowFallingEdge, // Active high, even edges |
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101 ESpiPolarityHighFallingEdge, // Active low, odd edges |
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102 ESpiPolarityHighRisingEdge // Active low, even edges |
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103 }; |
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104 |
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105 enum TSpiSsPinMode |
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106 { |
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107 ESpiCSPinActiveLow, // Active low |
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108 ESpiCSPinActiveHigh // Active high |
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109 }; |
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110 |
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111 class TConfigSpiV01 |
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112 { |
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113 public: |
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114 TSpiWordWidth iWordWidth; |
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115 TInt32 iClkSpeedHz; |
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116 TSpiClkMode iClkMode; |
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117 TInt32 iTimeoutPeriod; |
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118 TEndianness iEndianness; |
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119 TBitOrder iBitOrder; |
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120 TUint iTransactionWaitCycles; |
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121 TSpiSsPinMode iSSPinActiveMode; |
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122 }; |
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123 |
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124 typedef TPckgBuf <TConfigSpiV01> TConfigSpiBufV01; |
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125 |
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126 |
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127 // |
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128 // Bus-specific configuration for I2C bus |
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129 // |
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130 |
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131 enum TI2cAddrType |
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132 { |
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133 EI2cAddr7Bit, |
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134 EI2cAddr10Bit |
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135 }; |
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136 |
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137 class TConfigI2cV01 |
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138 { |
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139 public: |
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140 TI2cAddrType iAddrType; // 7 or 10-bit addressing |
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141 TInt32 iClkSpeedHz; |
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142 TEndianness iEndianness; |
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143 TInt32 iTimeoutPeriod; |
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144 }; |
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145 |
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146 typedef TPckgBuf <TConfigI2cV01> TConfigI2cBufV01; |
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147 |
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148 |
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149 inline static TInt CreateSpiBuf(TConfigSpiBufV01*& aBuf, |
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150 TSpiWordWidth aWordWidth, |
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151 TInt32 aClkSpeedHz, |
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152 TSpiClkMode aClkMode, |
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153 TInt32 aTimeoutPeriod, |
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154 TEndianness aEndianness, |
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155 TBitOrder aBitOrder, |
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156 TUint aTransactionWaitCycles, |
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157 TSpiSsPinMode aSSPinActiveMode) |
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158 // Utility function to create a buffer for the SPI bus |
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159 { |
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160 aBuf = new TConfigSpiBufV01(); |
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161 if(aBuf==NULL) |
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162 return KErrNoMemory; |
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163 TConfigSpiV01 *buf = &((*aBuf)()); |
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164 buf->iWordWidth = aWordWidth; |
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165 buf->iClkSpeedHz = aClkSpeedHz; |
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166 buf->iClkMode = aClkMode; |
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167 buf->iTimeoutPeriod = aTimeoutPeriod; |
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168 buf->iEndianness = aEndianness; |
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169 buf->iBitOrder = aBitOrder; |
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170 buf->iTransactionWaitCycles = aTransactionWaitCycles; |
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171 buf->iSSPinActiveMode = aSSPinActiveMode; |
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172 return KErrNone; |
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173 } |
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174 |
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175 inline static TInt CreateI2cBuf(TConfigI2cBufV01*& aBuf, |
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176 TI2cAddrType aAddrType, |
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177 TInt32 aClkSpeedHz, |
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178 TEndianness aEndianness, |
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179 TInt32 aTimeoutPeriod) |
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180 // Utility function to create a buffer for the I2C bus |
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181 { |
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182 aBuf = new TConfigI2cBufV01(); |
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183 if(aBuf==NULL) |
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184 return KErrNoMemory; |
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185 TConfigI2cV01 *buf = &((*aBuf)()); |
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186 buf->iAddrType = aAddrType; |
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187 buf->iClkSpeedHz = aClkSpeedHz; |
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188 buf->iEndianness = aEndianness; |
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189 buf->iTimeoutPeriod = aTimeoutPeriod; |
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190 return KErrNone; |
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191 } |
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192 |
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193 // |
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194 // Enumerations for channel type and channel duplex defined in kernel-side class DIicBusChannel |
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195 // duplicated for temporary test |
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196 enum TChannelType |
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197 { |
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198 EMaster = 0, |
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199 ESlave = 0x01, |
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200 EMasterSlave = 0x02, |
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201 EInvalidType |
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202 }; |
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203 enum TChannelDuplex |
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204 { |
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205 EHalfDuplex = 0, // supports only half duplex transactions (even if bus spec supports full duplex) |
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206 EFullDuplex = 0x1, // supports full duplex transactions (queud transactions may still be half duplex) |
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207 EInvalidDuplex |
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208 }; |
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209 // |
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210 // Bus realisation configuration |
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211 // |
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212 // 31 30 29 28 | 27 26 25 24 | 23 22 21 20 | 19 18 17 16 | 15 14 13 12 | 11 10 9 8 | 7 6 5 4 | 3 2 1 0 |
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213 // |
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214 // 31:29 - HS Master address (I2C only) |
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215 // 28 - HS address valid bit |
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216 // 27:23 - Reserved |
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217 // 22:20 - Bus type |
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218 // 19:15 - Channel number |
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219 // 14:10 - Transaction speed |
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220 // 9:0 - Slave address |
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221 #define HS_MASTER_ADDR_SHIFT 29 |
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222 #define HS_MASTER_ADDR_MASK 0x7 |
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223 #define HS_ADDR_VALID_SHIFT 28 |
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224 #define HS_ADDR_VALID_MASK 0x1 |
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225 #define BUS_TYPE_SHIFT 20 |
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226 #define BUS_TYPE_MASK 0x7 |
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227 #define CHANNEL_NO_SHIFT 15 |
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228 #define CHANNEL_NO_MASK 0x1F |
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229 #define TRANS_SPEED_SHIFT 10 |
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230 #define TRANS_SPEED_MASK 0x1F |
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231 #define SLAVE_ADDR_SHIFT 0 |
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232 #define SLAVE_ADDR_MASK 0x3FF |
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233 // |
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234 // Macros to access fields within Bus Realisation Configuration data, used on a per-transaction basis with IIC |
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235 #define SET_CONFIG_FIELD(aBusId,aField,aMask,aShift) aBusId=(aBusId&~(aMask<<aShift))|((aField&aMask)<<aShift); |
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236 #define GET_CONFIG_FIELD(aBusId,aMask,aShift) (((aBusId)>>(aShift))&(aMask)) |
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237 |
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238 #define GET_HS_MASTER_ADDR(aBusId) GET_CONFIG_FIELD(aBusId,HS_MASTER_ADDR_MASK,HS_MASTER_ADDR_SHIFT) |
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239 #define SET_HS_MASTER_ADDR(aBusId,aHsMasterAddr) SET_CONFIG_FIELD(aBusId,aHsMasterAddr,HS_MASTER_ADDR_MASK,HS_MASTER_ADDR_SHIFT) |
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240 #define GET_HS_VALID(aBusId) GET_CONFIG_FIELD(aBusId,HS_ADDR_VALID_MASK,HS_ADDR_VALID_SHIFT) |
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241 #define SET_HS_VALID(aBusId,aHsValid) SET_CONFIG_FIELD(aBusId,aHsValid,HS_ADDR_VALID_MASK,HS_ADDR_VALID_SHIFT) |
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242 #define GET_BUS_TYPE(aBusId) GET_CONFIG_FIELD(aBusId,BUS_TYPE_MASK,BUS_TYPE_SHIFT) |
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243 #define SET_BUS_TYPE(aBusId,aBusType) SET_CONFIG_FIELD(aBusId,aBusType,BUS_TYPE_MASK,BUS_TYPE_SHIFT) |
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244 #define GET_CHAN_NUM(aBusId) GET_CONFIG_FIELD(aBusId,CHANNEL_NO_MASK,CHANNEL_NO_SHIFT) |
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245 #define SET_CHAN_NUM(aBusId,aChanNum) SET_CONFIG_FIELD(aBusId,aChanNum,CHANNEL_NO_MASK,CHANNEL_NO_SHIFT) |
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246 #define SET_TRANS_SPEED(aBusId,aTransSpeed) SET_CONFIG_FIELD(aBusId,aTransSpeed,TRANS_SPEED_MASK,TRANS_SPEED_SHIFT) |
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247 #define GET_TRANS_SPEED(aBusId) GET_CONFIG_FIELD(aBusId,TRANS_SPEED_MASK,TRANS_SPEED_SHIFT) |
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248 #define SET_SLAVE_ADDR(aBusId,aSlaveAddr) SET_CONFIG_FIELD(aBusId,aSlaveAddr,SLAVE_ADDR_MASK,SLAVE_ADDR_SHIFT) |
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249 #define GET_SLAVE_ADDR(aBusId) GET_CONFIG_FIELD(aBusId,SLAVE_ADDR_MASK,SLAVE_ADDR_SHIFT) |
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250 |
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251 static const TUint8 KTransactionWithPreamble = 0x80; |
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252 static const TUint8 KTransactionWithMultiTransc = 0x40; |
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253 |
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254 enum TIicBusSlaveTrigger |
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255 { |
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256 ERxAllBytes = 0x01, |
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257 ERxUnderrun = 0x02, |
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258 ERxOverrun = 0x04, |
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259 ETxAllBytes = 0x08, |
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260 ETxUnderrun = 0x10, |
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261 ETxOverrun = 0x20, |
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262 EGeneralBusError = 0x40, |
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263 EAsyncCaptChan = 0x80 |
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264 }; |
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265 |
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266 #endif // #ifndef __KERNEL_MODE__ |
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267 |
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268 // |
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269 // User-Side abbreviation of kernel side classes TIicBusTransfer and TIicBusTransaction |
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270 // |
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271 struct TUsideTferDesc |
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272 { |
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273 TInt8 iType; // as one of TReqType |
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274 TInt8 iBufGranularity; // width of a transfer word in bits |
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275 TDes8* iBuffer; // the data for this transfer (packed into 8-bit words with padding) |
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276 TUsideTferDesc* iNext; |
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277 }; |
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278 |
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279 struct TUsideTracnDesc |
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280 { |
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281 TBusType iType; |
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282 TDes8* iHeader; |
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283 TUsideTferDesc* iHalfDuplexTrans; |
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284 TUsideTferDesc* iFullDuplexTrans; |
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285 TUint8 iFlags; // used to indicate if it supports a preamble |
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286 TAny* iPreambleArg; // used for preamble argument |
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287 TAny* iMultiTranscArg; // used for multi transc argument |
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288 }; |
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289 |
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290 class RBusDevIicClient : public RBusLogicalChannel |
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291 { |
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292 public: |
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293 enum TControl |
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294 { |
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295 // Master mode operations |
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296 EQTransSync=1, /**< Queue Transaction (Synchronous version) */ |
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297 // Slave mode operations |
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298 EInitSlaveClient, /**< Instigate Slave initialisation required to support testing */ |
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299 ECaptureChanSync, /**< Capture Channel (Synchronous version) */ |
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300 EReleaseChan, /**< ReleaseChannel */ |
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301 ERegisterRxBuffer, /**< Register a buffer for receiving data */ |
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302 ERegisterTxBuffer, /**< Register a buffer for transmitting data */ |
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303 ESetNotifTrigger /**< Set the notification triggers */ |
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304 }; |
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305 |
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306 enum TStaticExt |
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307 { |
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308 ECtlIoNone = 0, |
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309 ECtlIoDumpChan = 1, // KCtrlIoDumpChan - defined only for UDEB |
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310 // ControlIO codes for Master follow |
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311 ECtlIoBlockReqCompletion=(KTestMasterControlIo+KTestControlIoPilOffset), |
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312 ECtlIoUnblockReqCompletion, |
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313 ECtlIoDeRegChan, |
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314 ECtlIoTracnOne, |
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315 ECtlIoPriorityTest, |
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316 EGetTestResult, |
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317 ECtlIoSetTimeOutFlag, |
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318 ECtlIoTestFullDuplexTrans, |
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319 // ControlIO codes for Slave follow |
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320 ECtrlIoRxWords=(KTestSlaveControlIo+KTestControlIoPilOffset), |
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321 ECtrlIoTxWords, |
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322 ECtrlIoRxTxWords, |
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323 ECtrlIoTxChkBuf, |
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324 ECtlIoBusError, |
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325 ECtrlIoBlockNotification, |
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326 ECtrlIoUnblockNotification, |
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327 ECtrlIoUpdTimeout, |
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328 ECtrlIoNotifNoTrigger |
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329 }; |
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330 |
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331 enum TTestFullDuplexTrans |
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332 { |
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333 ETestValidFullDuplexTrans=1, |
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334 ETestInvalidFullDuplexTrans1, |
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335 ETestInvalidFullDuplexTrans2, |
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336 ETestLastNodeFullDuplexTrans, |
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337 ETestDiffNodeNoFullDuplexTrans, |
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338 ETestNone |
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339 }; |
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340 |
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341 enum TRequest |
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342 { |
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343 // Master mode operations |
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344 EQTransAsync=1, /**< Queue Transaction (Asynchronous version) */ |
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345 ECtrlIoTestBufReUse, |
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346 // Slave mode operations |
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347 ECaptureChanAsync, /**< Capture Channel (Asynchronous version) */ |
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348 ECtrlIoOvUndRunRxTx |
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349 }; |
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350 |
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351 enum TTestMessages |
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352 { |
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353 ETestIicChannelInlineFunc=KTestControlUnitTestOffset |
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354 }; |
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355 |
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356 #ifndef __KERNEL_MODE__ |
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357 public: |
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358 inline TInt TestIiicChannelInlineFunc(){return DoControl (ETestIicChannelInlineFunc, NULL, NULL);} |
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359 // Master mode functions |
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360 inline TInt Open(TDesC& aProxyName) {return (DoCreate(aProxyName,TVersion(KIicClientMajorVersionNumber,KIicClientMinorVersionNumber,KIicClientBuildVersionNumber),-1,NULL,NULL,EOwnerThread));} |
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361 |
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362 inline TInt QueueTransaction(TInt aBusId, TUsideTracnDesc* aTransaction) {return(DoControl(EQTransSync,(TAny*)aBusId,(TAny*)aTransaction));} |
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363 |
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364 inline void QueueTransaction(TRequestStatus& aStatus, TInt aBusId, TUsideTracnDesc* aTransaction) {DoRequest(EQTransAsync,aStatus,(TAny*)aBusId,(TAny*)aTransaction);} |
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365 |
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366 inline void CancelAsyncOperation(TRequestStatus* aStatus, TInt aBusId) {TInt* parms[2]; parms[0]=(TInt*)aStatus; parms[1]=(TInt*)aBusId;DoCancel((TInt)&parms[0]);} |
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367 |
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368 // Slave mode functions |
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369 inline TInt InitSlaveClient() {return(DoControl(EInitSlaveClient,NULL,NULL));} |
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370 inline TInt CaptureChannel(TInt aBusId, TDes8* aConfigHdr, TInt& aChannelId) {TInt* parms[2]; parms[0]=(TInt*)aBusId; parms[1]=&aChannelId;return(DoControl(ECaptureChanSync,(TAny*)aConfigHdr,(TAny*)(&parms[0])));} |
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371 |
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372 inline TInt CaptureChannel(TInt aBusId, TDes8* aConfigHdr, TInt& aChannelId, TRequestStatus& aStatus) {TInt* parms[2]; parms[0]=(TInt*)aBusId; parms[1]=&aChannelId;DoRequest(ECaptureChanAsync,aStatus,(TAny*)aConfigHdr,(TAny*)(&parms[0]));return KErrNone;} |
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373 |
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374 inline TInt ReleaseChannel(TInt aChannelId){return(DoControl(EReleaseChan,(TAny*)aChannelId,NULL));}; |
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375 inline TInt RegisterRxBuffer(TInt aChannelId, TInt8 aBufGranularity, TInt8 aNumWords, TInt8 aOffset){TInt8 parms[3]; parms[0]=aBufGranularity; parms[1]=aNumWords; parms[2]=aOffset;return(DoControl(ERegisterRxBuffer,(TAny*)aChannelId,(TAny*)(&parms[0])));}; |
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376 inline TInt RegisterTxBuffer(TInt aChannelId, TInt8 aBufGranularity, TInt8 aNumWords, TInt8 aOffset){TInt8 parms[3]; parms[0]=aBufGranularity; parms[1]=aNumWords; parms[2]=aOffset;return(DoControl(ERegisterTxBuffer,(TAny*)aChannelId,(TAny*)(&parms[0])));}; |
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377 inline TInt SetNotificationTrigger(TInt aChannelId, TInt aTrigger, TRequestStatus* aStatus){TInt parms[2]; parms[0]=aChannelId; parms[1]=aTrigger;return(DoControl(ESetNotifTrigger,(TAny*)aStatus,(TAny*)(&parms[0])));}; |
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378 |
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379 // ControlIO functions follow |
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380 inline TInt BlockReqCompletion(TInt aBusId) {return(DoControl(ECtlIoBlockReqCompletion,(TAny*)aBusId));} |
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381 inline TInt UnblockReqCompletion(TInt aBusId) {return(DoControl(ECtlIoUnblockReqCompletion,(TAny*)aBusId));} |
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382 inline TInt DeRegisterChan(TInt aBusId) {return(DoControl(ECtlIoDeRegChan,(TAny*)aBusId));} |
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383 inline TInt TestTracnOne(TInt aBusId) {return(DoControl(ECtlIoTracnOne, (TAny*)aBusId));} |
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384 inline TInt SetTimeOutFlag(TInt aBusId){return(DoControl(ECtlIoSetTimeOutFlag,(TAny*)aBusId));} |
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385 inline TInt CancelTimeOutFlag(TInt aBusId){return(DoControl(ECtlIoNone,(TAny*)aBusId));} |
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386 inline TInt TestPriority(TInt aBusId) {return(DoControl(ECtlIoPriorityTest, (TAny*)aBusId));} |
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387 |
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388 inline TInt TestValidFullDuplexTrans(TInt aBusId) {return(DoControl(ECtlIoTestFullDuplexTrans, (TAny*)aBusId, (TAny*)ETestValidFullDuplexTrans));} |
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389 inline TInt TestInvalidFullDuplexTrans1(TInt aBusId) {return(DoControl(ECtlIoTestFullDuplexTrans, (TAny*)aBusId, (TAny*)ETestInvalidFullDuplexTrans1));} |
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390 inline TInt TestInvalidFullDuplexTrans2(TInt aBusId) {return(DoControl(ECtlIoTestFullDuplexTrans, (TAny*)aBusId, (TAny*)ETestInvalidFullDuplexTrans2));} |
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391 |
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392 inline TInt TestLastNodeFullDuplexTrans(TInt aBusId) {return(DoControl(ECtlIoTestFullDuplexTrans, (TAny*)aBusId, (TAny*)ETestLastNodeFullDuplexTrans));} |
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393 inline TInt TestDiffNodeNumFullDuplexTrans(TInt aBusId) {return(DoControl(ECtlIoTestFullDuplexTrans, (TAny*)aBusId, (TAny*)ETestDiffNodeNoFullDuplexTrans));} |
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394 |
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395 inline void TestBufferReUse(TInt aBusId, TRequestStatus& aStatus) {DoRequest(ECtrlIoTestBufReUse,aStatus,(TAny*)aBusId,NULL);} |
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396 |
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397 inline TInt SimulateRxNWords(TInt aBusId, TInt aChannelId, TInt aNumWords){TInt parms[2]; parms[0]=aChannelId; parms[1]=aNumWords;return(DoControl(ECtrlIoRxWords,(TAny*)aBusId,(TAny*)(&parms[0])));}; |
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398 inline TInt SimulateTxNWords(TInt aBusId, TInt aChannelId, TInt aNumWords){TInt parms[2]; parms[0]=aChannelId; parms[1]=aNumWords;return(DoControl(ECtrlIoTxWords,(TAny*)aBusId,(TAny*)(&parms[0])));}; |
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399 inline TInt SimulateRxTxNWords(TInt aBusId, TInt aChannelId, TInt aNumRxWords, TInt aNumTxWords){TInt parms[3]; parms[0]=aChannelId; parms[1]=aNumRxWords; parms[2]=aNumTxWords;return(DoControl(ECtrlIoRxTxWords,(TAny*)aBusId,(TAny*)(&parms[0])));}; |
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400 inline TInt SimulateBusErr(TInt aBusId, TInt aChannelId) {return(DoControl(ECtlIoBusError,(TAny*)aBusId,(TAny*)aChannelId));} |
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401 inline TInt BlockNotification(TInt aBusId, TInt aChannelId) {return(DoControl(ECtrlIoBlockNotification,(TAny*)aBusId,(TAny*)aChannelId));} |
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402 inline TInt UnblockNotification(TInt aBusId, TInt aChannelId) {return(DoControl(ECtrlIoUnblockNotification,(TAny*)aBusId,(TAny*)aChannelId));} |
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403 inline TInt UpdateTimeoutValues(TInt aBusId, TInt aChannelId) {return(DoControl(ECtrlIoUpdTimeout,(TAny*)aBusId,(TAny*)aChannelId));} |
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404 inline TInt SetNotifNoTrigger(TInt aChannelId, TInt aTrigger){return(DoControl(ECtrlIoNotifNoTrigger,(TAny*)aChannelId,(TAny*)aTrigger));}; |
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405 |
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406 inline void TestOverrunUnderrun(TInt aBusId, TInt aChannelId, TRequestStatus& aStatus) {DoRequest(ECtrlIoOvUndRunRxTx,aStatus,(TAny*)aBusId,(TAny*)aChannelId);} |
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407 |
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408 #endif |
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409 }; |
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410 |
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411 |
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412 #ifdef __KERNEL_MODE__ |
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413 |
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414 // Definition of function prototype for a callback function provided by the PSL |
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415 // to be invoked when the part played by the hardware in processing a transfer |
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416 // has completed. |
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417 typedef void (*THwDoneCbFn)(TAny* ); |
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418 |
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419 #endif |
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420 |
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421 // Data used to support tests |
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422 |
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423 // Transaction One |
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424 // |
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425 const TUint8 KTransOneTferOne[21] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20}; |
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426 const TUint8 KTransOneTferTwo[8] = {17,18,19,20,21,22,23,24}; |
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427 const TUint8 KTransOneTferThree[6] = {87,85,83,81,79,77}; |
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428 const TUint8 KPriorityTestHeader[6] = {0,1,2,3,4,10}; |
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429 const TInt KPriorityTestPrio[6] = {1,2,3,4,5,0}; |
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430 |
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431 const TInt KRxBufSizeInBytes = 64; |
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432 const TInt KTxBufSizeInBytes = 64; |
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433 |
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434 #endif |