1 // Copyright (c) 1998-2009 Nokia Corporation and/or its subsidiary(-ies).

     2 // All rights reserved.

     3 // This component and the accompanying materials are made available

     4 // under the terms of the License "Eclipse Public License v1.0"

     5 // which accompanies this distribution, and is available

     6 // at the URL "http://www.eclipse.org/legal/epl-v10.html".

     7 //

     8 // Initial Contributors:

     9 // Nokia Corporation - initial contribution.

    10 //

    11 // Contributors:

    12 //

    13 // Description:

    14 // e32test\misc\strataflash32.cpp

    15 // 

    16 //

    17 

    18 #include <e32def.h>

    19 #include <e32def_private.h>

    20 #include "flash.h"

    21 

    22 #include <e32test.h>

    23 GLREF_C RTest test;

    24 

    25 class StrataFlash32 : public Flash

    26 	{

    27 public:

    28 	virtual TInt Read(TUint32 anAddr, TUint32 aSize, TUint8* aDest);

    29 	virtual TInt BlankCheck(TUint32 anAddr, TUint32 aSize);

    30 	virtual TInt Erase(TUint32 anAddr, TUint32 aSize);

    31 	virtual TInt Write(TUint32 anAddr, TUint32 aSize, const TUint8* aSrc);

    32 	};

    33 

    34 

    35 Flash* Flash::New(TUint32 /*anAddr*/)

    36 	{

    37 	return new StrataFlash32;

    38 	}

    39 

    40 TInt StrataFlash32::Read(TUint32 anAddr, TUint32 aSize, TUint8* aDest)

    41 	{

    42 	Mem::Move(aDest,(const TUint32*)anAddr,aSize);

    43 	return KErrNone;

    44 	}

    45 

    46 TInt StrataFlash32::BlankCheck(TUint32 anAddr, TUint32 aSize)

    47 	{

    48 	const TUint32* p=(const TUint32*)anAddr;

    49 	const TUint32* pE=p+(aSize+3)/4;

    50 	while(p<pE)

    51 		{

    52 		if (*p++!=0xffffffff)

    53 			return (TUint32)p-anAddr;

    54 		}

    55 	return 0;

    56 	}

    57 

    58 TInt StrataFlash32::Erase(TUint32 anAddr, TUint32 aSize)

    59 	{

    60 	TUint32 base=anAddr&~0x3ffff;	// round base address down to block

    61 	TUint32 end=anAddr+aSize;

    62 	end=(end+0x3ffff)&~0x3ffff;	// round end address up to block

    63 	TUint32 size=end-base;

    64 	volatile TUint32* p=(volatile TUint32*)base;

    65 	*p=0x00500050;	// clear status reg

    66 	for (; size; size-=0x40000, p+=0x40000/4)

    67 		{

    68 		*p=0x00200020;	// block erase

    69 		*p=0x00d000d0;	// block erase confirm

    70 		while ((*p & 0x00800080)!=0x00800080) {}

    71 		TUint32 s=*p;

    72 		*p=0x00500050;	// clear status reg

    73 		*p=0x00ff00ff;	// read mode

    74 		if (s&0x00200020)

    75 			{

    76 			// error

    77 			return (TUint32)p-anAddr+1;

    78 			}

    79 		}

    80 	return 0;

    81 	}

    82 

    83 TInt StrataFlash32::Write(TUint32 anAddr, TUint32 aSize, const TUint8* aSrc)

    84 	{

    85 	volatile TUint32* p=(volatile TUint32*)anAddr;

    86 	const TUint32* pS=(const TUint32*)aSrc;

    87 	aSize=(aSize+63)&~63;

    88 /*

    89 	const TUint32* pE=pS+aSize/4;

    90 	for (; pS<pE; pS++, p++)

    91 		{

    92 		*p=0x00400040;	// word write

    93 		*p=*pS;		// write data

    94 		while ((*p & 0x00800080)!=0x00800080);

    95 		TUint32 s=*p;

    96 		*p=0x00500050;	// clear status reg

    97 		*p=0x00ff00ff;	// read mode

    98 		if (s&0x00100010)

    99 			{

   100 			// error

   101 			return (TUint32)p-anAddr+1;

   102 			}

   103 		}

   104 */

   105 

   106 	TUint32 s=0;

   107 	*p=0x00500050;	// clear status reg

   108 	while(aSize)

   109 		{

   110 		TUint32 wb_offset=((TUint32)p)&0x3f;

   111 		TUint32 max_count=(64-wb_offset)/4;

   112 		TUint32 count=Min(aSize/4,max_count);

   113 		TUint32 cwd=count-1;

   114 		cwd|=(cwd<<16);

   115 

   116 		s=0;

   117 		do	{

   118 			*p=0x00e800e8;	// Write to Buffer

   119 			*p=0x00700070;	// Read status register

   120 			s=*p;

   121 			} while ((s&0x00800080)!=0x00800080);

   122 		s=*p;

   123 		*p=cwd;

   124 		TUint32 i;

   125 		for (i=0; i<count; ++i)

   126 			*p++=*pS++;

   127 		*p=0x00d000d0;	// Write confirm

   128 		aSize-=4*count;

   129 		while ((*p & 0x00800080)!=0x00800080) {}	// Wait for write to complete

   130 		s=*p;

   131 		if (s&0x00300030)

   132 			break;

   133 		}

   134 	*p=0x00500050;	// clear status reg

   135 	*p=0x00ff00ff;	// read mode

   136 	if (s&0x00300030)

   137 		{

   138 		// error

   139 		return (TUint32)p-anAddr+1;

   140 		}

   141 

   142 	return 0;

   143 	}

   144 

   145