equal
deleted
inserted
replaced
296 if(l1type==2 || l1type==3 || l1type==4) |
296 if(l1type==2 || l1type==3 || l1type==4) |
297 { |
297 { |
298 // we have an L1 data cache... |
298 // we have an L1 data cache... |
299 TUint32 csir = InternalCache::SizeIdRegister(0,0); |
299 TUint32 csir = InternalCache::SizeIdRegister(0,0); |
300 TUint sets = ((csir>>13)&0x7fff)+1; |
300 TUint sets = ((csir>>13)&0x7fff)+1; |
301 TUint ways = ((csir>>3)&0x3ff)+1; |
301 TUint ways = ((csir>>3)&0x3ff); |
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302 ways+=1; |
302 TUint lineSizeShift = (csir&7)+4; |
303 TUint lineSizeShift = (csir&7)+4; |
303 // assume L1 data cache is VIPT and alias checks broken and so we need data cache colouring... |
304 // assume L1 data cache is VIPT and alias checks broken and so we need data cache colouring... |
304 dColourCount = (sets<<lineSizeShift)>>KPageShift; |
305 dColourCount = (sets<<lineSizeShift)>>KPageShift; |
305 if(l1type==4) // unified cache, so set instruction cache colour as well... |
306 if(l1type==4) // unified cache, so set instruction cache colour as well... |
306 iColourCount = (sets<<lineSizeShift)>>KPageShift; |
307 iColourCount = (sets<<lineSizeShift)>>KPageShift; |
310 if(l1type==1 || l1type==3) |
311 if(l1type==1 || l1type==3) |
311 { |
312 { |
312 // we have a separate L1 instruction cache... |
313 // we have a separate L1 instruction cache... |
313 TUint32 csir = InternalCache::SizeIdRegister(1,0); |
314 TUint32 csir = InternalCache::SizeIdRegister(1,0); |
314 TUint sets = ((csir>>13)&0x7fff)+1; |
315 TUint sets = ((csir>>13)&0x7fff)+1; |
315 TUint ways = ((csir>>3)&0x3ff)+1; |
316 TUint ways = ((csir>>3)&0x3ff); |
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317 ways+=1; |
316 TUint lineSizeShift = (csir&7)+4; |
318 TUint lineSizeShift = (csir&7)+4; |
317 iColourCount = (sets<<lineSizeShift)>>KPageShift; |
319 iColourCount = (sets<<lineSizeShift)>>KPageShift; |
318 TRACEB(("L1ICache = 0x%x,0x%x,%d colourCount=%d",sets,ways,lineSizeShift,(sets<<lineSizeShift)>>KPageShift)); |
320 TRACEB(("L1ICache = 0x%x,0x%x,%d colourCount=%d",sets,ways,lineSizeShift,(sets<<lineSizeShift)>>KPageShift)); |
319 } |
321 } |
320 } |
322 } |
900 __NK_ASSERT_DEBUG(!iAliasLinAddr || aProcess == iAliasProcess); |
902 __NK_ASSERT_DEBUG(!iAliasLinAddr || aProcess == iAliasProcess); |
901 |
903 |
902 if(TUint(aAddr^KIPCAlias)<TUint(KIPCAliasAreaSize)) |
904 if(TUint(aAddr^KIPCAlias)<TUint(KIPCAliasAreaSize)) |
903 return KErrBadDescriptor; // prevent access to alias region |
905 return KErrBadDescriptor; // prevent access to alias region |
904 |
906 |
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907 #ifdef _DEBUG |
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908 if (KDebugNum(KFORCEKUPAGEFAULTS)) |
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909 { |
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910 TInt r = ThePager.FlushRegion(aProcess, aAddr, aSize); |
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911 if (r != KErrNone) |
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912 return r; |
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913 } |
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914 #endif |
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915 |
905 // Grab the mmu lock before opening a reference on os asid so that this thread |
916 // Grab the mmu lock before opening a reference on os asid so that this thread |
906 // is in an implicit critical section and therefore can't leak the reference by |
917 // is in an implicit critical section and therefore can't leak the reference by |
907 // dying before iAliasLinAddr is set. |
918 // dying before iAliasLinAddr is set. |
908 MmuLock::Lock(); |
919 MmuLock::Lock(); |
909 |
920 |