| branch | RCL_3 |
| changeset 256 | c1f20ce4abcf |
| parent 36 | 538db54a451d |
| child 257 | 3e88ff8f41d5 |
| 249:a179b74831c9 | 256:c1f20ce4abcf |
|---|---|
196 |
196 |
197 //#define __MINIMUM_MACHINE_CODE__ |
197 //#define __MINIMUM_MACHINE_CODE__ |
198 |
198 |
199 #if defined(__WINS__) |
199 #if defined(__WINS__) |
200 #define __NAKED__ __declspec( naked ) |
200 #define __NAKED__ __declspec( naked ) |
201 #ifndef __MINIMUM_MACHINE_CODE__ |
201 #if !defined(__MINIMUM_MACHINE_CODE__) && defined(__KERNEL_MODE__) |
202 //#define __MEM_MACHINE_CODED__ |
202 // Assembly language memmove() and memcpy() are used for WINS but only in the kernel, not euser |
203 #define __MEMMOVE_MACHINE_CODED__ |
|
203 #endif |
204 #endif |
204 #define __CPU_X86 |
205 #define __CPU_X86 |
205 #endif |
206 #endif |
206 |
207 |
207 #if defined(__X86__) |
208 #if defined(__X86__) |
366 #else |
367 #else |
367 #define __SWITCH_TO_ARM |
368 #define __SWITCH_TO_ARM |
368 #define __END_ARM |
369 #define __END_ARM |
369 #endif |
370 #endif |
370 |
371 |
371 #define CC_EQ 0 |
372 #define CC_EQ 0U |
372 #define CC_NE 1 |
373 #define CC_NE 1U |
373 #define CC_CS 2 |
374 #define CC_CS 2U |
374 #define CC_CC 3 |
375 #define CC_CC 3U |
375 #define CC_MI 4 |
376 #define CC_MI 4U |
376 #define CC_PL 5 |
377 #define CC_PL 5U |
377 #define CC_VS 6 |
378 #define CC_VS 6U |
378 #define CC_VC 7 |
379 #define CC_VC 7U |
379 #define CC_HI 8 |
380 #define CC_HI 8U |
380 #define CC_LS 9 |
381 #define CC_LS 9U |
381 #define CC_GE 10 |
382 #define CC_GE 10U |
382 #define CC_LT 11 |
383 #define CC_LT 11U |
383 #define CC_GT 12 |
384 #define CC_GT 12U |
384 #define CC_LE 13 |
385 #define CC_LE 13U |
385 #define CC_AL 14 |
386 #define CC_AL 14U |
386 |
387 |
387 #ifdef __CPU_ARM_HAS_CLZ |
388 #ifdef __CPU_ARM_HAS_CLZ |
388 #if __ARM_ASSEMBLER_ISA__ >= 5 |
389 #if __ARM_ASSEMBLER_ISA__ >= 5 |
389 #define CLZ(Rd,Rm) asm("clz r" #Rd ", r" #Rm) |
390 #define CLZ(Rd,Rm) asm("clz r" #Rd ", r" #Rm) |
390 #else |
391 #else |
603 #define __MSR_CPSR_C(cc,r) asm("msr"#cc" cpsr_c,"#r); |
604 #define __MSR_CPSR_C(cc,r) asm("msr"#cc" cpsr_c,"#r); |
604 #endif |
605 #endif |
605 |
606 |
606 // Causes undefined instruction exception on both ARM and THUMB |
607 // Causes undefined instruction exception on both ARM and THUMB |
607 #define __ASM_CRASH() asm(".word 0xe7ffdeff ") |
608 #define __ASM_CRASH() asm(".word 0xe7ffdeff ") |
608 #if defined(__GNUC__) |
609 #if defined(__GNUC__) |
609 #define __crash() asm(".word 0xe7ffdeff " : : : "memory") |
610 #define __crash() asm(".word 0xe7ffdeff " : : : "memory") |
611 #elif defined(__GCCXML__) |
|
612 #define __crash() (*((TInt *) 0x0) = 0xd1e) |
|
610 #elif defined(__ARMCC__) |
613 #elif defined(__ARMCC__) |
611 // RVCT doesn't let us inline an undefined instruction |
614 // RVCT doesn't let us inline an undefined instruction |
612 // use a CDP to CP15 instead - doesn't work on THUMB but never mind |
615 // use a CDP to CP15 instead - doesn't work on THUMB but never mind |
613 #if __ARMCC_VERSION < 310000 |
616 #if __ARMCC_VERSION < 310000 |
614 #define __crash() asm("cdp p15, 0, c0, c0, c0, 0 ") |
617 #define __crash() asm("cdp p15, 0, c0, c0, c0, 0 ") |
636 |
639 |
637 #ifdef __CPU_X86 |
640 #ifdef __CPU_X86 |
638 #define EXC_TRAP_CTX_SZ 10 // ebx, esp, ebp, esi, edi, ds, es, fs, gs, eip |
641 #define EXC_TRAP_CTX_SZ 10 // ebx, esp, ebp, esi, edi, ds, es, fs, gs, eip |
639 |
642 |
640 // Causes exception |
643 // Causes exception |
641 #if defined(__VC32__) || defined(__CW32__) |
644 #if defined(__VC32__) |
642 #define __crash() do { _asm int 0ffh } while(0) |
645 #define __crash() do { _asm int 255 } while(0) |
646 #elif defined(__CW32__) |
|
647 #define __crash() do { *(volatile TInt*)0 = 0; } while(0) |
|
643 #else |
648 #else |
644 #define __crash() asm("int 0xff " : : : "memory") |
649 #define __crash() asm("int 0xff " : : : "memory") |
645 #endif |
650 #endif |
646 |
651 |
647 #ifdef __VC32__ |
652 #ifdef __VC32__ |