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1 // Copyright (c) 2002-2010 Nokia Corporation and/or its subsidiary(-ies). |
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2 // All rights reserved. |
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3 // This component and the accompanying materials are made available |
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4 // under the terms of "Eclipse Public License v1.0" |
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5 // which accompanies this distribution, and is available |
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6 // at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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7 // |
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8 // Initial Contributors: |
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9 // Nokia Corporation - initial contribution. |
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10 // |
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11 // Contributors: |
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12 // |
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13 // Description: |
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14 // include/drivers/dmadefs.h |
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15 // DMA Framework - General class, enum, constant and type definitions. |
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16 // |
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17 // |
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18 |
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19 /** @file |
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20 @publishedPartner |
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21 */ |
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22 |
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23 #ifndef __DMADEFS_H__ |
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24 #define __DMADEFS_H__ |
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25 |
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26 |
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27 #include <e32def.h> |
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28 |
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29 |
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30 /** The client request callback type. |
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31 |
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32 */ |
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33 enum TDmaCallbackType |
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34 { |
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35 /** Transfer request completion callback |
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36 |
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37 @released |
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38 */ |
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39 EDmaCallbackRequestCompletion = 0x01, |
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40 /** Transfer request completion callback - source side |
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41 |
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42 @prototype |
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43 */ |
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44 EDmaCallbackRequestCompletion_Src = 0x02, |
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45 /** Transfer request completion callback - destination side |
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46 |
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47 @prototype |
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48 */ |
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49 EDmaCallbackRequestCompletion_Dst = 0x04, |
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50 |
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51 /** Descriptor completion callback |
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52 |
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53 @prototype |
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54 */ |
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55 EDmaCallbackDescriptorCompletion = 0x08, |
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56 /** Descriptor completion callback - source side |
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57 |
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58 @prototype |
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59 */ |
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60 EDmaCallbackDescriptorCompletion_Src = 0x10, |
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61 /** Descriptor completion callback - destination side |
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62 |
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63 @prototype |
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64 */ |
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65 EDmaCallbackDescriptorCompletion_Dst = 0x20, |
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66 |
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67 /** Frame completion callback |
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68 |
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69 @prototype |
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70 */ |
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71 EDmaCallbackFrameCompletion = 0x40, |
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72 /** Frame completion callback - source side |
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73 |
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74 @prototype |
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75 */ |
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76 EDmaCallbackFrameCompletion_Src = 0x80, |
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77 /** Frame completion callback - destination side |
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78 |
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79 @prototype |
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80 */ |
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81 EDmaCallbackFrameCompletion_Dst = 0x100, |
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82 |
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83 /** H/W descriptor pause event callback |
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84 |
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85 @prototype |
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86 */ |
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87 EDmaCallbackLinkedListPaused = 0x200, |
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88 /** H/W descriptor pause event callback - source side |
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89 |
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90 @prototype |
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91 */ |
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92 EDmaCallbackLinkedListPaused_Src = 0x400, |
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93 /** H/W descriptor pause event callback - destination side |
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94 |
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95 @prototype |
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96 */ |
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97 EDmaCallbackLinkedListPaused_Dst = 0x800 |
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98 }; |
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99 |
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100 |
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101 /** The outcome of the transfer request. |
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102 |
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103 @released |
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104 */ |
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105 enum TDmaResult |
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106 { |
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107 /** Completed without error */ |
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108 EDmaResultOK = 0, |
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109 /** There was an error */ |
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110 EDmaResultError |
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111 }; |
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112 |
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113 |
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114 /** To be used with address mode field of the DMA transfer config struct. |
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115 |
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116 @see TDmaTransferConfig::iAddrMode |
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117 */ |
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118 enum TDmaAddrMode |
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119 { |
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120 /** Constant addressing. The address remains the same for consecutive |
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121 accesses. |
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122 |
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123 @released |
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124 */ |
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125 KDmaAddrModeConstant, |
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126 /** Post-increment addressing. The address increases by the element size |
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127 after each access. |
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128 |
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129 @released |
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130 */ |
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131 KDmaAddrModePostIncrement, |
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132 /** Post-decrement addressing. The address decreases by the element size |
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133 after each access. |
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134 |
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135 @prototype |
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136 */ |
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137 KDmaAddrModePostDecrement, |
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138 /** 1D-index addressing. The address always increases by the element size |
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139 plus the element skip value after each access. |
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140 |
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141 @prototype |
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142 */ |
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143 KDmaAddrMode1DIndex, |
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144 /** 2D-index addressing. The address increases by the element size plus the |
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145 element skip value - but only within a frame. Once a full frame has been |
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146 transferred, the address increases by the element size plus the element |
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147 skip value plus the frame skip value. |
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148 |
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149 @prototype |
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150 */ |
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151 KDmaAddrMode2DIndex |
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152 }; |
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153 |
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154 |
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155 /** To be used with the burst size field of the DMA transfer config struct. |
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156 |
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157 @see SDmacCaps::iBurstTransactions |
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158 @see TDmaTransferConfig::iBurstSize |
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159 |
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160 @prototype |
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161 */ |
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162 enum TDmaBurstSize |
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163 { |
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164 /** Don't use burst transactions */ |
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165 KDmaNoBursts = -1, |
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166 /** Don't care (the default) */ |
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167 KDmaBurstSizeAny = 0x00, |
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168 /** 4 bytes */ |
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169 KDmaBurstSize4 = 0x04, |
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170 /** 8 bytes */ |
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171 KDmaBurstSize8 = 0x08, |
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172 /** 16 bytes */ |
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173 KDmaBurstSize16 = 0x10, |
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174 /** 32 bytes */ |
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175 KDmaBurstSize32 = 0x20, |
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176 /** 64 bytes */ |
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177 KDmaBurstSize64 = 0x40, |
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178 /** 128 bytes */ |
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179 KDmaBurstSize128 = 0x80 |
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180 }; |
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181 |
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182 |
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183 /** To be used with the flags field of the DMA transfer config struct. |
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184 |
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185 @see TDmaTransferConfig::iFlags |
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186 */ |
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187 enum TDmaTransferFlags |
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188 { |
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189 /** Location is address of a memory buffer (as opposed to a peripheral or a |
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190 register). |
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191 |
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192 @released |
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193 */ |
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194 KDmaMemAddr = 0x01, |
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195 /** Address is a physical address (as opposed to a linear one). |
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196 |
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197 If it is a memory address then KDmaMemIsContiguous will need to be set |
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198 as well. |
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199 |
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200 @released |
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201 */ |
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202 KDmaPhysAddr = 0x02, |
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203 /** Target memory is known to be physically contiguous, hence there is |
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204 no need for the framework to check for memory fragmentation. |
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205 |
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206 @released |
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207 */ |
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208 KDmaMemIsContiguous = 0x04, |
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209 /** Don't use packed access (if possible) |
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210 |
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211 @released |
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212 */ |
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213 KDmaDontUsePacked = 0x08, |
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214 /** Location is big endian (little endian if not set). |
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215 |
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216 To have any effect, this flag requires the DMAC to support endianness |
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217 conversion. |
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218 |
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219 @see SDmacCaps::iEndiannessConversion |
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220 |
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221 @prototype |
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222 */ |
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223 KDmaBigEndian = 0x10, |
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224 /** Don't do endianness conversion even if applicable. |
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225 |
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226 To have any effect, this flag requires the DMAC to support endianness |
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227 conversion. |
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228 |
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229 @see SDmacCaps::iEndiannessConversion |
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230 |
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231 @prototype |
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232 */ |
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233 KDmaLockEndian = 0x20, |
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234 /** Execute client request callback after each subtransfer (streaming / |
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235 loop case). |
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236 |
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237 This option is only taken into account if the respective |
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238 TDmaTransferConfig::iRepeatCount is non-zero. |
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239 |
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240 The callback will complete with a TDmaCallbackType of |
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241 EDmaCallbackRequestCompletion (even if the repeat counts for source and |
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242 destination are different), unless the flag |
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243 TDmaPILFlags::KDmaAsymCompletionCallback is set too, in which case what |
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244 is described there applies. |
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245 |
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246 @prototype |
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247 */ |
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248 KDmaCallbackAfterEveryTransfer = 0x40, |
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249 /** Execute client request callback after each completed hardware |
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250 descriptor. |
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251 |
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252 Requires the DMAC to support this feature. Unless the DMAC supports |
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253 asymmetric descriptor interrupts as well, this flag should not be set |
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254 on only one (source or destination) side. |
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255 |
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256 @see SDmacCaps::iDescriptorInterrupt |
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257 @see SDmacCaps::iAsymDescriptorInterrupt |
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258 |
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259 @prototype |
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260 */ |
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261 KDmaCallbackAfterEveryDescriptor = 0x80, |
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262 /** Execute client request callback after each completed frame. |
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263 |
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264 Requires the DMAC to support this feature. Unless the DMAC supports |
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265 asymmetric frame interrupts as well, this flag should not be set on |
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266 only one (source or destination) side. |
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267 |
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268 @see SDmacCaps::iFrameInterrupt |
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269 @see SDmacCaps::iAsymFrameInterrupt |
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270 |
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271 @prototype |
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272 */ |
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273 KDmaCallbackAfterEveryFrame = 0x100 |
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274 }; |
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275 |
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276 |
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277 /** To be used with the synchronization flags field of a DMA transfer |
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278 config struct. |
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279 |
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280 @see SDmacCaps::iSynchronizationTypes |
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281 @see TDmaTransferConfig::iSyncFlags |
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282 |
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283 @released |
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284 */ |
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285 enum TDmaTransferSyncFlags |
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286 { |
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287 /** Leave the decision on whether the transfer is hardware synchronized at |
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288 this end (either source or destination) to the framework. This is the |
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289 default. |
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290 */ |
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291 KDmaSyncAuto = 0x00, |
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292 /** Transfer is not hardware synchronized at this end (either source or |
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293 destination). |
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294 */ |
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295 KDmaSyncNone = 0x01, |
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296 /** Transfer is hardware synchronized at this end (either source or |
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297 destination). This option can also be used on its own, without any |
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298 of the following sync sizes. |
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299 */ |
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300 KDmaSyncHere = 0x02, |
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301 /** H/W synchronized at this end: transfer one ELEMENT (a number of |
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302 bytes, depending on the configured element size) per sync event. |
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303 */ |
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304 KDmaSyncSizeElement = 0x04, |
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305 /** H/W synchronized at this end: transfer one FRAME (a number of |
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306 elements, depending on the configured frame size) per sync event. |
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307 */ |
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308 KDmaSyncSizeFrame = 0x08, |
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309 /** H/W synchronized at this end: transfer one BLOCK (a number of |
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310 frames, depending on the configured transfer size) per sync |
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311 event. This is the most common use case. |
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312 */ |
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313 KDmaSyncSizeBlock = 0x10, |
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314 /** H/W synchronized at this end: transfer one PACKET (a number of |
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315 elements, depending on the configured packet size) per sync event. |
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316 In cases where the transfer block size is not a multiple of the |
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317 packet size the last packet will consist of the remaining elements. |
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318 */ |
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319 KDmaSyncSizePacket = 0x20 |
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320 }; |
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321 |
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322 |
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323 /** To be used with the Graphics operation field of a DMA transfer request. |
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324 |
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325 @see TDmaTransferArgs::iGraphicsOps |
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326 |
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327 @prototype |
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328 */ |
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329 enum TDmaGraphicsOps |
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330 { |
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331 /** Don't use any graphics acceleration feature (the default) */ |
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332 KDmaGraphicsOpNone = 0x00, |
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333 /** Enable graphics acceleration feature 'Constant Fill' */ |
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334 KDmaGraphicsOpConstantFill = 0x01, |
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335 /** Enable graphics acceleration feature 'TransparentCopy' */ |
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336 KDmaGraphicsOpTransparentCopy = 0x02 |
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337 }; |
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338 |
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339 |
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340 /** To be used with the PIL flags field of a DMA transfer request. |
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341 |
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342 @see TDmaTransferArgs::iFlags |
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343 */ |
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344 enum TDmaPILFlags |
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345 { |
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346 /** Request a different max transfer size (for instance for test |
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347 purposes). |
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348 |
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349 @released |
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350 */ |
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351 KDmaAltTransferLength = 0x01, |
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352 /** Execute client request callback in ISR context instead of from a |
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353 DFC. |
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354 |
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355 @released |
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356 */ |
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357 KDmaRequestCallbackFromIsr = 0x02, |
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358 /** Execute descriptor completion callback in ISR context instead of |
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359 from a DFC. This option is to be used in conjunction with the |
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360 TDmaTransferFlags::KDmaCallbackAfterEveryDescriptor flag. |
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361 |
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362 @prototype |
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363 */ |
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364 KDmaDescriptorCallbackFromIsr = 0x04, |
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365 /** Execute frame completion callback in ISR context instead of |
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366 from a DFC. This option is to be used in conjunction with the |
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367 TDmaTransferFlags::KDmaCallbackAfterEveryFrame flag. |
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368 |
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369 @prototype |
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370 */ |
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371 KDmaFrameCallbackFromIsr = 0x08, |
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372 /** Execute the client request callback separately for source and |
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373 destination subtransfers. |
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374 |
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375 This flag also determines the TDmaCallbackType value returned. If set, |
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376 the callback will complete with EDmaCallbackRequestCompletion_Src or |
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377 EDmaCallbackRequestCompletion_Dst, respectively, instead of with |
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378 EDmaCallbackRequestCompletion. |
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379 |
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380 Requires the DMAC to support this feature. |
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381 |
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382 @see SDmacCaps::iAsymCompletionInterrupt |
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383 |
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384 @prototype |
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385 */ |
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386 KDmaAsymCompletionCallback = 0x10, |
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387 /** Execute the descriptor completion callback separately for source |
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388 and destination subtransfers. |
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389 |
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390 This flag modifies the behaviour of the |
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391 TDmaTransferFlags::KDmaCallbackAfterEveryDescriptor flag and also |
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392 determines the TDmaCallbackType value returned. If set, the callback |
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393 will complete with EDmaCallbackDescriptorCompletion_Src or |
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394 EDmaCallbackDescriptorCompletion_Dst, respectively, instead of with |
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395 EDmaCallbackDescriptorCompletion. |
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396 |
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397 Requires the DMAC to support this feature. |
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398 |
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399 @see SDmacCaps::iAsymDescriptorInterrupt |
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400 |
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401 @prototype |
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402 */ |
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403 KDmaAsymDescriptorCallback = 0x20, |
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404 /** Execute the frame completion callback separately for source and |
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405 destination subtransfers. |
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406 |
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407 This flag modifies the behaviour of the |
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408 TDmaTransferFlags::KDmaCallbackAfterEveryFrame flag. If set, the |
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409 callback will complete with EDmaCallbackFrameCompletion_Src or |
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410 EDmaCallbackFrameCompletion_Dst, respectively, instead of with |
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411 EDmaCallbackFrameCompletion. |
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412 |
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413 Requires the DMAC to support this feature. |
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414 |
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415 @see SDmacCaps::iAsymFrameInterrupt |
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416 |
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417 @prototype |
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418 */ |
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419 KDmaAsymFrameCallback = 0x40, |
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420 /** This transfer (only) should use the channel priority indicated by |
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421 TDmaTransferArgs::iChannelPriority. |
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422 |
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423 @prototype |
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424 */ |
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425 KDmaRequestChannelPriority = 0x80 |
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426 }; |
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427 |
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428 |
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429 /** Values which can be used with the priority field when opening a channel |
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430 and/or when fragmenting a transfer request. |
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431 |
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432 @see TDmaChannel::SCreateInfo::iPriority |
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433 @see TDmaTransferArgs::iChannelPriority |
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434 |
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435 @prototype |
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436 */ |
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437 enum TDmaPriority |
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438 { |
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439 /** No transfer priority preference (don't care value) */ |
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440 KDmaPriorityNone = 0x0, |
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441 /** Platform-independent transfer priority 1 (lowest) */ |
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442 KDmaPriority1 = 0x80000001, |
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443 /** Platform-independent transfer priority 2 */ |
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444 KDmaPriority2 = 0x80000002, |
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445 /** Platform-independent transfer priority 3 */ |
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446 KDmaPriority3 = 0x80000003, |
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447 /** Platform-independent transfer priority 4 */ |
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448 KDmaPriority4 = 0x80000004, |
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449 /** Platform-independent transfer priority 5 */ |
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450 KDmaPriority5 = 0x80000005, |
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451 /** Platform-independent transfer priority 6 */ |
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452 KDmaPriority6 = 0x80000006, |
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453 /** Platform-independent transfer priority 7 */ |
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454 KDmaPriority7 = 0x80000007, |
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455 /** Platform-independent transfer priority 8 (highest) */ |
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456 KDmaPriority8 = 0x80000008 |
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457 }; |
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458 |
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459 |
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460 /** Contains the configuration values for either the source or the |
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461 destination side of a DMA transfer. |
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462 |
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463 Note that some fields (notably iElementSize, iElementsPerFrame and |
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464 iFramesPerTransfer) may only differ between source and destination if |
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465 the underlying DMAC supports this. |
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466 |
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467 @see SDmacCaps::iSrcDstAsymmetry |
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468 @see TDmaTransferArgs::iSrcConfig |
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469 @see TDmaTransferArgs::iDstConfig |
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470 |
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471 @released |
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472 */ |
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473 struct TDmaTransferConfig |
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474 { |
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475 friend struct TDmaTransferArgs; |
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476 |
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477 /** Default constructor. |
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478 |
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479 Initializes all fields with meaningful default values. |
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480 */ |
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481 #ifdef DMA_APIV2 |
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482 KIMPORT_C |
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483 #endif |
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484 TDmaTransferConfig(); |
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485 |
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486 /** Alternate constructor. |
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487 |
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488 Intended for general use ie. not 1D or 2D transfers |
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489 */ |
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490 #ifdef DMA_APIV2 |
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491 KIMPORT_C |
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492 #endif |
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493 TDmaTransferConfig ( |
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494 TUint32 aAddr, |
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495 TUint aTransferFlags, |
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496 TDmaAddrMode aAddrMode = KDmaAddrModePostIncrement, |
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497 TUint aSyncFlags = KDmaSyncAuto, |
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498 TDmaBurstSize aBurstSize = KDmaBurstSizeAny, |
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499 TUint aElementSize = 0, |
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500 TUint aElementsPerPacket = 0, |
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501 TUint aPslTargetInfo = 0, |
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502 TInt aRepeatCount = 0 |
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503 ); |
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504 |
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505 /** Alternate constructor. |
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506 |
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507 Intended for 1D and 2D transfers. |
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508 */ |
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509 #ifdef DMA_APIV2 |
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510 KIMPORT_C |
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511 #endif |
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512 TDmaTransferConfig ( |
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513 TUint32 aAddr, |
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514 TUint aElementSize, |
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515 TUint aElementsPerFrame, |
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516 TUint aFramesPerTransfer, |
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517 TInt aElementSkip, |
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518 TInt aFrameSkip, |
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519 TUint aTransferFlags, |
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520 TUint aSyncFlags = KDmaSyncAuto, |
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521 TDmaBurstSize aBurstSize = KDmaBurstSizeAny, |
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522 TUint aElementsPerPacket = 0, |
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523 TUint aPslTargetInfo = 0, |
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524 TInt aRepeatCount = 0 |
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525 ); |
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526 |
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527 /** Transfer start address */ |
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528 TUint32 iAddr; |
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529 /** Address mode */ |
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530 TDmaAddrMode iAddrMode; |
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531 /** Element size in bytes (1/2/4/8) */ |
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532 TUint iElementSize; |
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533 /** Number of elements per frame */ |
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534 TUint iElementsPerFrame; |
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535 /** Number of elements per packet */ |
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536 TUint iElementsPerPacket; |
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537 /** Number of frames to transfer (result is the transfer block) */ |
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538 TUint iFramesPerTransfer; |
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539 /** Element skip in bytes (for addr modes E1DIndex or E2DIndex) */ |
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540 TInt iElementSkip; |
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541 /** Frame skip in bytes (for addr mode E2DIndex) */ |
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542 TInt iFrameSkip; |
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543 /** Use burst transactions of the specified size (in bytes) |
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544 @see TDmaBurstSize |
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545 */ |
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546 TInt iBurstSize; |
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547 /** PIL src/dst config flags. |
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548 @see TDmaTransferFlags |
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549 */ |
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550 TUint32 iFlags; |
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551 /** Transfer synchronization flags. |
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552 @see TDmaTransferSyncFlags |
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553 */ |
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554 TUint32 iSyncFlags; |
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555 /** Information passed to the PSL */ |
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556 TUint iPslTargetInfo; |
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557 /** How often to repeat this (sub-)transfer: |
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558 0 no repeat (the default) |
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559 1..n once / n times |
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560 -1 endlessly. |
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561 |
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562 @prototype |
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563 */ |
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564 TInt iRepeatCount; |
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565 /** Structure contents delta vector. |
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566 |
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567 (usage tbd) |
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568 |
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569 @prototype |
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570 */ |
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571 TUint32 iDelta; |
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572 /** Reserved for future use */ |
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573 TUint32 iReserved; |
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574 |
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575 private: |
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576 /** Private constructor. |
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577 |
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578 Initializes fields with the values passed in by the legacy version of |
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579 the DDmaRequest::Fragment() call. |
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580 */ |
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581 TDmaTransferConfig(TUint32 aAddr, TUint aFlags, TBool aAddrInc); |
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582 }; |
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583 |
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584 |
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585 /** To be used by the client to pass DMA transfer request details to the |
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586 framework. |
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587 |
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588 Also used internally by the framework as a pseudo descriptor if the |
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589 controller doesn't support hardware descriptors (scatter/gather LLI). |
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590 |
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591 @see DDmaRequest::Fragment |
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592 |
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593 @released |
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594 */ |
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595 struct TDmaTransferArgs |
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596 { |
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597 friend class DDmaRequest; |
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598 friend class TDmaChannel; |
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599 friend class TDmac; |
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600 friend class DmaChannelMgr; |
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601 |
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602 /** Default constructor. |
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603 |
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604 Initializes all fields with meaningful default values. |
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605 */ |
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606 #ifdef DMA_APIV2 |
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607 KIMPORT_C |
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608 #endif |
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609 TDmaTransferArgs(); |
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610 |
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611 /** Alternate constructor. |
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612 |
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613 Intended for transfers where src and dst TDmaTransferConfig structs |
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614 share some of the same options, i.e. iDmaTransferFlags, iAddrMode, |
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615 iSyncFlags, iBurstSize, and iElementSize. |
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616 |
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617 @param aSrcAddr |
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618 @param aDstAddr |
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619 @param aCount Number of bytes to transfer |
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620 @param aDmaTransferFlags Bitmask of TDmaTransferFlags for src and dst |
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621 @param aDmaSyncFlags Bitmask of TDmaTransferSyncFlags for src and dst |
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622 @param aMode Address mode for src and dst |
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623 @param aDmaPILFlags Bitmask of TDmaPILFlags |
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624 @param aElementSize In bytes (1/2/4/8) for src and dst |
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625 @param aChannelPriority |
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626 @param aBurstSize for src and dst |
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627 @param aPslRequestInfo Info word passed to the PSL |
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628 @param aGraphicOp Graphics operation to be executed |
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629 @param aColour Colour value for graphics operation |
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630 */ |
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631 #ifdef DMA_APIV2 |
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632 KIMPORT_C |
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633 #endif |
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634 TDmaTransferArgs ( |
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635 TUint aSrcAddr, |
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636 TUint aDstAddr, |
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637 TUint aCount, |
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638 TUint aDmaTransferFlags, |
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639 TUint aDmaSyncFlags = KDmaSyncAuto, |
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640 TUint aDmaPILFlags = 0, |
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641 TDmaAddrMode aMode = KDmaAddrModePostIncrement, |
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642 TUint aElementSize = 0, |
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643 TUint aChannelPriority = KDmaPriorityNone, |
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644 TDmaBurstSize aBurstSize = KDmaBurstSizeAny, |
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645 TUint aPslRequestInfo = 0, |
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646 TDmaGraphicsOps aGraphicOp = KDmaGraphicsOpNone, |
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647 TUint32 aColour = 0 |
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648 ); |
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649 |
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650 /** Alternate constructor. |
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651 |
|
652 Intended for transfers needing specific options for source and |
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653 destination TDmaTransferConfig structs. |
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654 |
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655 @param aSrc Configuration values for the source |
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656 @param aDst Configuration values for the destination |
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657 @param aFlags @see TDmaPILFlags |
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658 @param aChannelPriority Use for this request (only) the indicated |
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659 channel priority. Requires KDmaRequestChannelPriority to be set in |
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660 iFlags as well. @see TDmaPriority |
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661 @param aPslRequestInfo Info word passed to the PSL |
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662 @param aGraphicOp Graphics operation to be executed |
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663 @param aColour Colour value for graphics operation |
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664 */ |
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665 #ifdef DMA_APIV2 |
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666 KIMPORT_C |
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667 #endif |
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668 TDmaTransferArgs ( |
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669 const TDmaTransferConfig& aSrc, |
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670 const TDmaTransferConfig& aDst, |
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671 TUint32 aFlags = 0, |
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672 TUint aChannelPriority = KDmaPriorityNone, |
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673 TUint aPslRequestInfo = 0, |
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674 TDmaGraphicsOps aGraphicOp = KDmaGraphicsOpNone, |
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675 TUint32 aColour = 0 |
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676 ); |
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677 |
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678 /** Configuration values for the source */ |
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679 TDmaTransferConfig iSrcConfig; |
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680 /** Configuration values for the destination */ |
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681 TDmaTransferConfig iDstConfig; |
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682 |
|
683 /** Number of bytes to transfer (optional). |
|
684 |
|
685 A non-zero value here must be consistent with iElementSize, |
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686 iElementsPerFrame and iFramesPerTransfer in iSrcConfig and iDstConfig |
|
687 if the latter are specified as well (or instead, they may be left at |
|
688 their default values of zero). |
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689 |
|
690 If zero, the PIL will fill in a value calculated from multiplying |
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691 iElementSize, iElementsPerFrame and iFramesPerTransfer in iSrcConfig, |
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692 so that the PSL can rely on it being always non-zero and valid. |
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693 */ |
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694 TUint iTransferCount; |
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695 /** Graphics operation to be executed */ |
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696 TDmaGraphicsOps iGraphicsOps; |
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697 /** Colour value for graphics operations */ |
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698 TUint32 iColour; |
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699 /** PIL common flags |
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700 @see TDmaPILFlags |
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701 */ |
|
702 TUint32 iFlags; |
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703 /** Use for this request (only) the indicated channel priority. |
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704 Requires KDmaRequestChannelPriority to be set in iFlags as well. |
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705 @see TDmaPriority |
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706 */ |
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707 TUint iChannelPriority; |
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708 /** Info word passed to the PSL */ |
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709 TUint iPslRequestInfo; |
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710 /** Stores the PSL cookie returned by TDmaChannel::PslId() at request |
|
711 fragmentation time. |
|
712 |
|
713 The value PslId() is often (but not necessarily) identical with the |
|
714 client's TDmaChannel::SCreateInfo::iCookie, which gets passed by the |
|
715 PIL into DmaChannelMgr::Open() as 'aOpenId'. |
|
716 */ |
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717 TUint32 iChannelCookie; |
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718 /** Structure contents delta vector. |
|
719 |
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720 (usage tbd) |
|
721 |
|
722 @prototype |
|
723 */ |
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724 TUint32 iDelta; |
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725 /** Reserved for future use */ |
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726 TUint32 iReserved1; |
|
727 |
|
728 private: |
|
729 /** Private constructor. |
|
730 |
|
731 Initializes fields with the values passed in by the legacy version of |
|
732 the DDmaRequest::Fragment() call. |
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733 */ |
|
734 TDmaTransferArgs(TUint32 aSrcAddr, TUint32 aDstAddr, TInt aCount, |
|
735 TUint aFlags, TUint32 aPslInfo); |
|
736 /** Reserved for future use */ |
|
737 TUint32 iReserved2; |
|
738 }; |
|
739 |
|
740 |
|
741 /** DMAC capabilities info structure. |
|
742 |
|
743 Instances are to be filled in by the PSL and then linked to via TDmaChannel |
|
744 objects after they have been opened. |
|
745 |
|
746 The contents may vary even between channels on the same DMAC (but should |
|
747 remain constant for a given channel for the duration that it is open), |
|
748 depending on static or dynamic factors which only the PSL knows about. |
|
749 |
|
750 @see TDmaChannel::Open |
|
751 @see TDmaChannel::DmacCaps |
|
752 |
|
753 @released |
|
754 */ |
|
755 struct SDmacCaps |
|
756 { |
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757 /** DMAC supports n + 1 different channel priorities. |
|
758 */ |
|
759 TUint iChannelPriorities; |
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760 /** DMAC supports the pausing and resuming of channels. |
|
761 */ |
|
762 TBool iChannelPauseAndResume; |
|
763 /** DMA addresses must be aligned on an element size boundary. |
|
764 */ |
|
765 TBool iAddrAlignedToElementSize; |
|
766 /** DMAC supports 1D (element) index addressing in hardware. |
|
767 */ |
|
768 TBool i1DIndexAddressing; |
|
769 /** DMAC supports 2D (frame) index addressing in hardware. |
|
770 */ |
|
771 TBool i2DIndexAddressing; |
|
772 /** DMAC supports these transfer synchronization types (bitmap of values). |
|
773 |
|
774 @see TDmaTransferSyncFlags |
|
775 */ |
|
776 TUint iSynchronizationTypes; |
|
777 /** DMAC supports burst transactions with these sizes (bitmap of values). |
|
778 |
|
779 @see TDmaBurstSize |
|
780 */ |
|
781 TUint iBurstTransactions; |
|
782 /** DMAC supports a 'h/w descriptor complete' interrupt. |
|
783 */ |
|
784 TBool iDescriptorInterrupt; |
|
785 /** DMAC supports a 'frame transfer complete' interrupt. |
|
786 */ |
|
787 TBool iFrameInterrupt; |
|
788 /** DMAC supports a 'linked-list pause event' interrupt. |
|
789 */ |
|
790 TBool iLinkedListPausedInterrupt; |
|
791 /** DMAC supports endianness conversion. |
|
792 */ |
|
793 TBool iEndiannessConversion; |
|
794 /** DMAC supports these graphics operations (bitmap of values). |
|
795 |
|
796 @see TDmaGraphicsOps |
|
797 */ |
|
798 TUint iGraphicsOps; |
|
799 /** DMAC supports repeated transfers (loops). |
|
800 */ |
|
801 TBool iRepeatingTransfers; |
|
802 /** DMAC supports logical channel linking (chaining). |
|
803 */ |
|
804 TBool iChannelLinking; |
|
805 /** DMAC supports scatter/gather mode (linked list items). |
|
806 */ |
|
807 TBool iHwDescriptors; |
|
808 /** DMAC supports asymmetric source and destination transfer |
|
809 parameters (such as element size). |
|
810 */ |
|
811 TBool iSrcDstAsymmetry; |
|
812 /** DMAC supports asymmetric h/w descriptor lists. |
|
813 |
|
814 ETrue here requires ETrue for iHwDescriptors and iSrcDstAsymmetry as |
|
815 well. |
|
816 */ |
|
817 TBool iAsymHwDescriptors; |
|
818 /** DMAC with asymmetric descriptor support has the limitation that the |
|
819 number of bytes transferred in source and destination must be equal in |
|
820 every link segment (i.e. in each src/dst descriptor pair). |
|
821 |
|
822 ETrue here requires ETrue for iAsymHwDescriptors as well. |
|
823 */ |
|
824 TBool iBalancedAsymSegments; |
|
825 /** DMAC supports separate transfer completion notifications for source and |
|
826 destination side subtransfers. |
|
827 |
|
828 This capability is required for the asymmetric transfer completion |
|
829 callback API feature. |
|
830 |
|
831 @see TDmaPILFlags::KDmaAsymCompletionCallback |
|
832 */ |
|
833 TBool iAsymCompletionInterrupt; |
|
834 /** DMAC supports separate descriptor completion notifications for source and |
|
835 destination side. |
|
836 |
|
837 This capability is required for the asymmetric descriptor completion |
|
838 callback API feature. |
|
839 |
|
840 ETrue here requires ETrue for both iDescriptorInterrupt and |
|
841 iAsymHwDescriptors as well. |
|
842 |
|
843 @see TDmaPILFlags::KDmaAsymDescriptorCallback |
|
844 */ |
|
845 TBool iAsymDescriptorInterrupt; |
|
846 /** DMAC supports separate frame completion notifications for source and |
|
847 destination side. |
|
848 |
|
849 This capability is required for the asymmetric frame completion |
|
850 callback API feature. |
|
851 |
|
852 ETrue here requires ETrue for iFrameInterrupt as well. |
|
853 |
|
854 @see TDmaPILFlags::KDmaAsymFrameCallback |
|
855 */ |
|
856 TBool iAsymFrameInterrupt; |
|
857 |
|
858 /** Reserved for future use */ |
|
859 TUint32 iReserved[5]; |
|
860 }; |
|
861 |
|
862 |
|
863 ////////////////////////////////////////////////////////////////////////////// |
|
864 // INTERFACE WITH TEST HARNESS |
|
865 ////////////////////////////////////////////////////////////////////////////// |
|
866 |
|
867 /** Set of information used by test harness. |
|
868 |
|
869 @deprecated |
|
870 */ |
|
871 #ifdef DMA_APIV2 |
|
872 struct TDmaTestInfo |
|
873 { |
|
874 /** Maximum transfer size in bytes for all channels (ie. the minimum of all |
|
875 channels' maximum size) |
|
876 */ |
|
877 TUint iMaxTransferSize; |
|
878 /** 3->Memory buffers must be 4-byte aligned, 7->8-byte aligned, ... */ |
|
879 TUint iMemAlignMask; |
|
880 /** Cookie to pass to DDmaRequest::Fragment for memory-memory transfer */ |
|
881 TUint32 iMemMemPslInfo; |
|
882 /** Number of test single-buffer channels */ |
|
883 TInt iMaxSbChannels; |
|
884 /** Pointer to array containing single-buffer test channel ids */ |
|
885 TUint32* iSbChannels; |
|
886 /** Number of test double-buffer channels */ |
|
887 TInt iMaxDbChannels; |
|
888 /** Pointer to array containing double-buffer test channel ids */ |
|
889 TUint32* iDbChannels; |
|
890 /** Number of test scatter-gather channels */ |
|
891 TInt iMaxSgChannels; |
|
892 /** Pointer to array containing scatter-gather test channel ids */ |
|
893 TUint32* iSgChannels; |
|
894 }; |
|
895 #endif |
|
896 |
|
897 |
|
898 /** Set of information used by test harness. |
|
899 |
|
900 @released |
|
901 */ |
|
902 struct TDmaV2TestInfo |
|
903 { |
|
904 enum {KMaxChannels=32}; |
|
905 /** Maximum transfer size in bytes for all channels (ie. the minimum of all |
|
906 channels' maximum size) |
|
907 */ |
|
908 TUint iMaxTransferSize; |
|
909 /** 3->Memory buffers must be 4-byte aligned, 7->8-byte aligned, ... */ |
|
910 TUint iMemAlignMask; |
|
911 /** Cookie to pass to DDmaRequest::Fragment for memory-memory transfer */ |
|
912 TUint32 iMemMemPslInfo; |
|
913 /** Number of test single-buffer channels */ |
|
914 TInt iMaxSbChannels; |
|
915 /** Pointer to array containing single-buffer test channel ids */ |
|
916 TUint32 iSbChannels[KMaxChannels]; |
|
917 /** Number of test double-buffer channels */ |
|
918 TInt iMaxDbChannels; |
|
919 /** Pointer to array containing double-buffer test channel ids */ |
|
920 TUint32 iDbChannels[KMaxChannels]; |
|
921 /** Number of test scatter-gather channels */ |
|
922 TInt iMaxSgChannels; |
|
923 /** Pointer to array containing scatter-gather test channel ids */ |
|
924 TUint32 iSgChannels[KMaxChannels]; |
|
925 }; |
|
926 |
|
927 |
|
928 #endif // #ifndef __DMADEFS_H__ |