--- a/kernel/eka/drivers/power/smppower/idlehelper.cia	Wed May 05 05:11:16 2010 +0100
+++ b/kernel/eka/drivers/power/smppower/idlehelper.cia	Mon May 10 11:40:53 2010 +0100
@@ -85,12 +85,12 @@
 	LDREX(3,1);                                                       // r3 = iIdlingCpus
     asm("orr    r3,r0,r3");                                           // orr in mask for this CPU
     asm("cmp    r3,r2");                                              // compare to iAllEngagedCpusMask
-    asm("orreq  r3,r3,#%a0" : : "i" (TIdleSupport::KGlobalIdleFlag)); // if equal orr in KGlobalIdleFlag
+    asm("orreq  r3,r3,#%a0" : : "i" ((TUint32)TIdleSupport::KGlobalIdleFlag)); // if equal orr in KGlobalIdleFlag
     STREX(12,3,1);
     asm("cmp    r12, #0 ");                                              // 
 	asm("bne    1b ");                                                   // write didn't succeed try again
     __DATA_MEMORY_BARRIER__(r12);
-    asm("and    r0,r3,#%a0" : : "i" (TIdleSupport::KGlobalIdleFlag));
+    asm("and    r0,r3,#%a0" : : "i" ((TUint32)TIdleSupport::KGlobalIdleFlag));
 	__JUMP(,lr);
     asm("__iAllEngagedCpusMask:");
     asm(".word %a0" : : "i" ((TInt)&TIdleSupport::iAllEngagedCpusMask));//
@@ -125,7 +125,7 @@
     asm("stmfd sp!, {r4-r5,lr} ");	
     asm("add r0,r0,#%a0" : : "i"  _FOFF(TSyncPointBase, iStageAndCPUWaitingMask)); // skip vt
     asm("ldr r4,[r0,#4]"); 
-    asm("ldr r4,[r4]")
+    asm("ldr r4,[r4]");
    __DATA_MEMORY_BARRIER_Z__(r12);          // 
     asm("1: ");
 	LDREX(2,0);                             // r2 =  iStageAndCPUWaitingMask, r4 = iAllEnagedCpusMask
@@ -149,7 +149,7 @@
 #endif		
     asm("2: ");
     asm("cmp r3,r5");                       // all (old stage does not equal new stage)
-    asm("ldmfdne sp!, {r4-r5,pc}");         // yup return
+    asm("bne 3f");                            // yup return
 #ifdef SYNCPOINT_WFE		
 	__DATA_MEMORY_BARRIER__(r12);        
 	ARM_WFE;
@@ -158,6 +158,8 @@
     __DATA_MEMORY_BARRIER__(r12);           // ensure read is observed
     asm("mov r3,r2,lsr #16");               // re-read new stage
     asm("b 2b");                            // loop back
+    asm("3: ");
+    asm("ldmfd sp!, {r4-r5,pc}");         // return
     }
 
 /** 
@@ -188,7 +190,7 @@
     asm("stmfd sp!, {r4,lr} ");	
     asm("add r0,r0,#%a0" : : "i"  _FOFF(TSyncPointBase, iStageAndCPUWaitingMask)); // skip vt
     asm("ldr r4,[r0,#4]");
-    asm("ldr r4,[r4]")
+    asm("ldr r4,[r4]");
     __DATA_MEMORY_BARRIER_Z__(r12);          // 
     asm("1: ");
 	LDREX(2,0);                             // r2 =  iStageAndCPUWaitingMask, r4 = iAllEnagedCpusMask
@@ -208,7 +210,7 @@
 #endif		
     asm("2: ");
     asm("ands r3,r2,#0x80000000");          // MSB set?	
-    asm("ldmfdne sp!, {r4,pc}");            // yup return
+    asm("bne 4f");                          // yup return
 #ifdef SYNCPOINT_WFE		
 	__DATA_MEMORY_BARRIER__(r12);
 	ARM_WFE;
@@ -222,7 +224,8 @@
     __DATA_MEMORY_BARRIER__(r12);           // ensure that's written
 	ARM_SEV;
 #endif	
-    asm("ldmfd sp!, {r4,pc}");            // yup return
+    asm("4:");
+    asm("ldmfd sp!, {r4,pc}");            // return
     }
 	
 	
@@ -292,7 +295,7 @@
     }
 #endif
 
-__NAKED__  TInt TIdleSupport::IntPending()  
+__NAKED__  TUint32 TIdleSupport::IntPending()  
     {
 	asm("ldr    r1,__KCPUIFAddr");//r1 = address of iBaseIntIfAddress
 	asm("ldr	r1, [r1]");//r1 = address of Hw GIC CPU interrupt interface base address