1 // Copyright (c) 2004-2009 Nokia Corporation and/or its subsidiary(-ies).

     2 // All rights reserved.

     3 // This component and the accompanying materials are made available

     4 // under the terms of the License "Eclipse Public License v1.0"

     5 // which accompanies this distribution, and is available

     6 // at the URL "http://www.eclipse.org/legal/epl-v10.html".

     7 //

     8 // Initial Contributors:

     9 // Nokia Corporation - initial contribution.

    10 //

    11 // Contributors:

    12 //

    13 // Description:

    14 // This file contains stepping code refactored from rm_debug_kerneldriver.cpp/rm_debug_kerneldriver.h

    15 //

    16 

    17 #include <e32def.h>

    18 #include <e32def_private.h>

    19 #include <e32cmn.h>

    20 #include <e32cmn_private.h>

    21 #include <kernel/kernel.h> 

    22 #include <kernel/kern_priv.h>

    23 #include <nk_trace.h>

    24 #include <arm.h>

    25 #include <rm_debug_api.h>

    26 

    27 #include "d_rmd_stepping.h"

    28 #include "d_rmd_breakpoints.h"

    29 #include "rm_debug_kerneldriver.h"	// needed to access DRM_DebugChannel

    30 #include "rm_debug_driver.h"

    31 #include "debug_logging.h"

    32 

    33 using namespace Debug;

    34 

    35 //

    36 // DRMDStepping::DRMDStepping

    37 //

    38 DRMDStepping::DRMDStepping(DRM_DebugChannel* aChannel)

    39 :

    40 	iChannel(aChannel)

    41 	{

    42 	// to do

    43 	}

    44 

    45 //

    46 // DRMDStepping::~DRM_DebugChannel

    47 //

    48 DRMDStepping::~DRMDStepping()

    49 	{

    50 	// to do

    51 	}

    52 

    53 //

    54 // DRMDStepping::IsExecuted

    55 //

    56 TBool DRMDStepping::IsExecuted(TUint8 aCondition ,TUint32 aStatusRegister)

    57 	{

    58 	LOG_MSG("DRMDStepping::IsExecuted()");

    59 

    60 	TBool N = ((aStatusRegister >> 28) & 0x0000000F) & 0x00000008;

    61 	TBool Z = ((aStatusRegister >> 28) & 0x0000000F) & 0x00000004;

    62 	TBool C = ((aStatusRegister >> 28) & 0x0000000F) & 0x00000002;

    63 	TBool V = ((aStatusRegister >> 28) & 0x0000000F) & 0x00000001;

    64 

    65 	switch(aCondition)

    66 		{

    67 		case 0:

    68 			return Z;

    69 		case 1:

    70 			return !Z;

    71 		case 2:

    72 			return C;

    73 		case 3:

    74 			return !C;

    75 		case 4:

    76 			return N;

    77 		case 5:

    78 			return !N;

    79 		case 6:

    80 			return V;

    81 		case 7:

    82 			return !V;

    83 		case 8:

    84 			return (C && !Z);

    85 		case 9:

    86 			return (!C || Z);

    87 		case 10:

    88 			return (N == V);

    89 		case 11:

    90 			return (N != V);

    91 		case 12:

    92 			return ((N == V) && !Z);

    93 		case 13:

    94 			return (Z || (N != V));

    95 		case 14:

    96 		case 15:

    97 			return ETrue;

    98 		}

    99 	

   100 	return EFalse;

   101 	}

   102 

   103 //

   104 // DRMDStepping::IsPreviousInstructionMovePCToLR

   105 //

   106 TBool DRMDStepping::IsPreviousInstructionMovePCToLR(DThread *aThread)

   107 	{

   108 	LOG_MSG("DRMDStepping::IsPreviousInstructionMovePCToLR()");

   109 

   110 	TInt err = KErrNone;

   111 	

   112 	// there are several types of instructions that modify the PC that aren't

   113 	// designated as linked or non linked branches.  the way gcc generates the

   114 	// code can tell us whether or not these instructions are to be treated as

   115 	// linked branches.  the main cases are bx and any type of mov or load or

   116 	// arithmatic operation that changes the PC.  if these are really just

   117 	// function calls that will return, gcc will generate a mov	lr, pc

   118 	// instruction as the previous instruction.  note that this is just for arm

   119 	// and armi

   120 	

   121 	// get the address of the previous instruction

   122 	TUint32 address = 0;

   123 	err = iChannel->ReadKernelRegisterValue(aThread, PC_REGISTER, address);

   124 	if(err != KErrNone)

   125 		{

   126 		LOG_MSG2("Non-zero error code discarded: %d", err);

   127 		}

   128 	address -= 4;

   129 

   130 	TBuf8<4> previousInstruction;

   131 	err = iChannel->DoReadMemory(aThread, address, 4, previousInstruction);

   132 	if (KErrNone != err)

   133 		{

   134 		LOG_MSG2("Error %d reading memory at address %x", address);

   135 		return EFalse;

   136 		}

   137 

   138 	const TUint32 movePCToLRIgnoringCondition = 0x01A0E00F;

   139 

   140 	TUint32 inst = *(TUint32 *)previousInstruction.Ptr();

   141 	

   142 	if ((inst & 0x0FFFFFFF) == movePCToLRIgnoringCondition)

   143 		{

   144 		return ETrue;

   145 		}

   146 		

   147 	return EFalse;

   148 	}

   149 

   150 //

   151 // DRMDStepping::DecodeDataProcessingInstruction

   152 //

   153 void DRMDStepping::DecodeDataProcessingInstruction(TUint8 aOpcode, TUint32 aOp1, TUint32 aOp2, TUint32 aStatusRegister, TUint32 &aBreakAddress)

   154 	{

   155 	LOG_MSG("DRMDStepping::DecodeDataProcessingInstruction()");

   156 

   157 	switch(aOpcode)

   158 		{

   159 		case 0:

   160 			{

   161 			// AND

   162 			aBreakAddress = aOp1 & aOp2;

   163 			break;

   164 			}

   165 		case 1:

   166 			{

   167 			// EOR

   168 			aBreakAddress = aOp1 ^ aOp2;

   169 			break;

   170 			}

   171 		case 2:

   172 			{

   173 			// SUB

   174 			aBreakAddress = aOp1 - aOp2;

   175 			break;

   176 			}

   177 		case 3:

   178 			{

   179 			// RSB

   180 			aBreakAddress = aOp2 - aOp1;

   181 			break;

   182 			}

   183 		case 4:

   184 			{

   185 			// ADD

   186 			aBreakAddress = aOp1 + aOp2;

   187 			break;

   188 			}

   189 		case 5:

   190 			{

   191 			// ADC

   192 			aBreakAddress = aOp1 + aOp2 + (aStatusRegister & arm_carry_bit()) ? 1 : 0;

   193 			break;

   194 			}

   195 		case 6:

   196 			{

   197 			// SBC

   198 			aBreakAddress = aOp1 - aOp2 - (aStatusRegister & arm_carry_bit()) ? 0 : 1;

   199 			break;

   200 			}

   201 		case 7:

   202 			{

   203 			// RSC

   204 			aBreakAddress = aOp2 - aOp1 - (aStatusRegister & arm_carry_bit()) ? 0 : 1;

   205 			break;

   206 			}

   207 		case 12:

   208 			{

   209 			// ORR

   210 			aBreakAddress = aOp1 | aOp2;

   211 			break;

   212 			}

   213 		case 13:

   214 			{

   215 			// MOV

   216 			aBreakAddress = aOp2;

   217 			break;

   218 			}

   219 		case 14:

   220 			{

   221 			// BIC

   222 			aBreakAddress = aOp1 & ~aOp2;

   223 			break;

   224 			}

   225 		case 15:

   226 			{

   227 			// MVN

   228 			aBreakAddress = ~aOp2;

   229 			break;

   230 			}

   231 		}

   232 	}

   233 

   234 //

   235 // DRMDStepping::CurrentInstruction

   236 //

   237 // Returns the current instruction bitpattern (either 32-bits or 16-bits) if possible

   238 TInt DRMDStepping::CurrentInstruction(DThread* aThread, TUint32& aInstruction)

   239 	{

   240 	LOG_MSG("DRMDStepping::CurrentInstruction");

   241 

   242 	// What is the current PC?

   243 	TUint32 pc;	

   244 	ReturnIfError(CurrentPC(aThread,pc));

   245 

   246 	// Read it one byte at a time to ensure alignment doesn't matter

   247 	TUint32 inst = 0;

   248 	for(TInt i=3;i>=0;i--)

   249 		{

   250 

   251 		TBuf8<1> instruction;

   252 		TInt err = iChannel->DoReadMemory(aThread, (pc+i), 1, instruction); 

   253 		if (KErrNone != err)

   254 			{

   255 			LOG_MSG2("DRMDStepping::CurrentInstruction : Failed to read memory at current PC: return 0x%08x",pc);

   256 			return err;

   257 			}

   258 

   259 		inst = (inst << 8) | (*(TUint8 *)instruction.Ptr());

   260 		}

   261 

   262 	aInstruction = inst;

   263 

   264 	LOG_MSG2("DRMDStepping::CurrentInstruction 0x%08x", aInstruction);

   265 

   266 	return KErrNone;

   267 	}

   268 

   269 //

   270 // DRMDStepping::CurrentArchMode

   271 //

   272 // Determines architecture mode from the supplied cpsr

   273 TInt DRMDStepping::CurrentArchMode(const TUint32 aCpsr, Debug::TArchitectureMode& aMode)

   274 	{

   275 // Thumb2 work will depend on having a suitable cpu architecture to compile for...

   276 #ifdef ECpuJf

   277 	// State table as per ARM ARM DDI0406A, section A.2.5.1

   278 	if(aCpsr & ECpuJf)

   279 		{

   280 		if (aCpsr & ECpuThumb)

   281 			{

   282 			// ThumbEE (Thumb2)

   283 			aMode = Debug::EThumb2EEMode;

   284 			}

   285 		else

   286 			{

   287 			// Jazelle mode - not supported

   288 			return KErrNotSupported;

   289 			}

   290 		}

   291 	else

   292 #endif

   293 		{

   294 		if (aCpsr & ECpuThumb)

   295 			{

   296 			// Thumb mode

   297 			aMode = Debug::EThumbMode;

   298 			}

   299 		else

   300 			{

   301 			// ARM mode

   302 			aMode = Debug::EArmMode;

   303 			}

   304 		}

   305 

   306 	return KErrNone;

   307 	}

   308 

   309 //

   310 // DRMDStepping::PCAfterInstructionExecutes

   311 //

   312 // Note, this function pretty much ignores all the arguments except for aThread.

   313 // The arguments continue to exist so that the function has the same prototype as

   314 // the original from Nokia. In the long term this function will be re-factored

   315 // to remove obsolete parameters.

   316 //

   317 TUint32 DRMDStepping::PCAfterInstructionExecutes(DThread *aThread, TUint32 aCurrentPC, TUint32 aStatusRegister, TInt aInstSize, /*TBool aStepInto,*/ TUint32 &aNewRangeEnd, TBool &aChangingModes)

   318 	{

   319 	LOG_MSG("DRMDStepping::PCAfterInstructionExecutes()");

   320 

   321 	// by default we will set the breakpoint at the next instruction

   322 	TUint32 breakAddress = aCurrentPC + aInstSize;

   323 

   324 	TInt err = KErrNone;

   325 

   326 	// determine the architecture

   327 	TUint32 cpuid;

   328 	asm("mrc p15, 0, cpuid, c0, c0, 0 ");

   329 	LOG_MSG2("DRMDStepping::PCAfterInstructionExecutes() - cpuid = 0x%08x\n",cpuid);

   330 

   331 	cpuid >>= 8;

   332 	cpuid &= 0xFF;

   333 

   334 	// determine the architecture mode for the current instruction

   335 	TArchitectureMode mode = EArmMode;	// Default assumption is ARM 

   336 

   337 	// Now we must examine the CPSR to read the T and J bits. See ARM ARM DDI0406A, section B1.3.3

   338 	TUint32 cpsr;

   339 

   340 	ReturnIfError(CurrentCPSR(aThread,cpsr));

   341 	LOG_MSG2("DRMDStepping::PCAfterInstructionExecutes() - cpsr = 0x%08x\n",cpsr);

   342 

   343 	// Determine the mode

   344 	ReturnIfError(CurrentArchMode(cpsr,mode));

   345 

   346 	// Decode instruction based on current CPU mode

   347 	switch(mode)

   348 		{

   349 		case Debug::EArmMode:

   350 			{

   351 			// Obtain the current instruction bit pattern

   352 			TUint32 inst;

   353 			ReturnIfError(CurrentInstruction(aThread,inst));

   354 			

   355 			LOG_MSG2("Current instruction: %x", inst);

   356 

   357 			// check the conditions to see if this will actually get executed

   358 			if (IsExecuted(((inst>>28) & 0x0000000F), aStatusRegister)) 

   359 				{

   360 				switch(arm_opcode(inst)) // bits 27-25

   361 					{

   362 					case 0:

   363 						{

   364 						switch((inst & 0x00000010) >> 4) // bit 4

   365 							{

   366 							case 0:

   367 								{

   368 								switch((inst & 0x01800000) >> 23) // bits 24-23

   369 									{

   370 									case 2:

   371 										{

   372 										// move to/from status register.  pc updates not allowed

   373 										// or TST, TEQ, CMP, CMN which don't modify the PC

   374 										break;

   375 										}

   376 									default:

   377 										{

   378 										// Data processing immediate shift

   379 										if (arm_rd(inst) == PC_REGISTER)

   380 											{

   381 											TUint32 rn = aCurrentPC + 8;

   382 											if (arm_rn(inst) != PC_REGISTER) // bits 19-16

   383 												{

   384 												err = iChannel->ReadKernelRegisterValue(aThread, arm_rn(inst), rn);

   385 												if(err != KErrNone)

   386 													{

   387 													LOG_MSG2("Non-zero error code discarded: %d", err);

   388 													}

   389 												}

   390 

   391 											TUint32 shifter = ShiftedRegValue(aThread, inst, aCurrentPC, aStatusRegister);

   392 

   393 											DecodeDataProcessingInstruction(((inst & 0x01E00000) >> 21), rn, shifter, aStatusRegister, breakAddress);

   394 											}

   395 										break;

   396 										}

   397 									}

   398 								break;

   399 								}

   400 							case 1:

   401 								{

   402 								switch((inst & 0x00000080) >> 7) // bit 7

   403 									{

   404 									case 0:

   405 										{

   406 										switch((inst & 0x01900000) >> 20) // bits 24-23 and bit 20

   407 											{

   408 											case 0x10:

   409 												{

   410 												// from figure 3-3

   411 												switch((inst & 0x000000F0) >> 4) // bits 7-4

   412 													{

   413 													case 1:

   414 														{

   415 														if (((inst & 0x00400000) >> 22) == 0) // bit 22

   416 															{

   417 															// BX

   418 															// this is a strange case.  normally this is used in the epilogue to branch the the link

   419 															// register.  sometimes it is used to call a function, and the LR is stored in the previous

   420 															// instruction.  since what we want to do is different for the two cases when stepping over,

   421 															// we need to read the previous instruction to see what we should do

   422 															err = iChannel->ReadKernelRegisterValue(aThread, (inst & 0x0000000F), breakAddress);

   423 															if(err != KErrNone)

   424 																{

   425 																LOG_MSG2("Non-zero error code discarded: %d", err);

   426 																}

   427 

   428 															if ((breakAddress & 0x00000001) == 1)

   429 																{

   430 																aChangingModes = ETrue;

   431 																}

   432 

   433 															breakAddress &= 0xFFFFFFFE;

   434 															}

   435 														break;

   436 														}

   437 													case 3:

   438 														{

   439 														// BLX

   440 															{

   441 															err = iChannel->ReadKernelRegisterValue(aThread, (inst & 0x0000000F), breakAddress);

   442 															if(err != KErrNone)

   443 																{

   444 																LOG_MSG2("Non-zero error code discarded: %d", err);

   445 																}

   446 

   447 															if ((breakAddress & 0x00000001) == 1)

   448 																{

   449 																aChangingModes = ETrue;

   450 																}

   451 															

   452 															breakAddress &= 0xFFFFFFFE;

   453 															}

   454 														break;

   455 														}

   456 													default:

   457 														{

   458 														// either doesn't modify the PC or it is illegal to

   459 														break;

   460 														}

   461 													}

   462 												break;

   463 												}

   464 											default:

   465 												{

   466 												// Data processing register shift

   467 												if (((inst & 0x01800000) >> 23) == 2) // bits 24-23

   468 													{

   469 													// TST, TEQ, CMP, CMN don't modify the PC

   470 													}

   471 												else if (arm_rd(inst) == PC_REGISTER)

   472 													{

   473 													// destination register is the PC

   474 													TUint32 rn = aCurrentPC + 8;

   475 													if (arm_rn(inst) != PC_REGISTER) // bits 19-16

   476 														{

   477 														err = iChannel->ReadKernelRegisterValue(aThread, arm_rn(inst), rn);

   478 														if(err != KErrNone)

   479 															{

   480 															LOG_MSG2("Non-zero error code discarded: %d", err);

   481 															}

   482 														}

   483 													

   484 													TUint32 shifter = ShiftedRegValue(aThread, inst, aCurrentPC, aStatusRegister);

   485 													

   486 													DecodeDataProcessingInstruction(((inst & 0x01E00000) >> 21), rn, shifter, aStatusRegister, breakAddress);

   487 													}

   488 												break;

   489 												}

   490 											}

   491 										break;

   492 										}

   493 									default:

   494 										{

   495 										// from figure 3-2, updates to the PC illegal

   496 										break;

   497 										}

   498 									}

   499 								break;

   500 								}

   501 							}

   502 						break;

   503 						}

   504 					case 1:

   505 						{

   506 						if (((inst & 0x01800000) >> 23) == 2) // bits 24-23

   507 							{

   508 							// cannot modify the PC

   509 							break;

   510 							}

   511 						else if (arm_rd(inst) == PC_REGISTER)

   512 							{

   513 							// destination register is the PC

   514 							TUint32 rn;

   515 							err = iChannel->ReadKernelRegisterValue(aThread, arm_rn(inst), rn); // bits 19-16

   516 							if(err != KErrNone)

   517 								{

   518 								LOG_MSG2("Non-zero error code discarded: %d", err);

   519 								}

   520 							TUint32 shifter = ((arm_data_imm(inst) >> arm_data_rot(inst)) | (arm_data_imm(inst) << (32 - arm_data_rot(inst)))) & 0xffffffff;

   521 

   522 							DecodeDataProcessingInstruction(((inst & 0x01E00000) >> 21), rn, shifter, aStatusRegister, breakAddress);

   523 							}

   524 						break;

   525 						}

   526 					case 2:

   527 						{

   528 						// load/store immediate offset

   529 						if (arm_load(inst)) // bit 20

   530 							{

   531 							// loading a register from memory

   532 							if (arm_rd(inst) == PC_REGISTER)

   533 								{

   534 								// loading the PC register

   535 								TUint32 base;

   536 								err = iChannel->ReadKernelRegisterValue(aThread, arm_rn(inst), base);

   537 								if(err != KErrNone)

   538 									{

   539 									LOG_MSG2("Non-zero error code discarded: %d", err);

   540 									}

   541 

   542 								/* Note: At runtime the PC would be 8 further on

   543 								 */

   544 								if (arm_rn(inst) == PC_REGISTER)

   545 									{

   546 									base = aCurrentPC + 8;

   547 									}

   548 

   549 								TUint32 offset = 0;

   550 

   551 								if (arm_single_pre(inst))

   552 									{

   553 									// Pre-indexing

   554 									offset = arm_single_imm(inst);

   555 

   556 									if (arm_single_u(inst))

   557 										{

   558 										base += offset;

   559 										}

   560 									else

   561 										{

   562 										base -= offset;

   563 										}

   564 									}

   565 

   566 								TBuf8<4> destination;

   567 								err = iChannel->DoReadMemory(aThread, base, 4, destination);

   568 								

   569 								if (KErrNone == err)

   570 									{

   571 									breakAddress = *(TUint32 *)destination.Ptr();

   572 

   573 									if ((breakAddress & 0x00000001) == 1)

   574 										{

   575 										aChangingModes = ETrue;

   576 										}

   577 									breakAddress &= 0xFFFFFFFE;

   578 									}

   579 								else

   580 									{

   581 									LOG_MSG("Error reading memory in decoding step instruction");

   582 									}

   583 								}

   584 							}

   585 						break;

   586 						}

   587 					case 3:

   588 						{

   589 						if (((inst & 0xF0000000) != 0xF0000000) && ((inst & 0x00000010) == 0))

   590 							{

   591 							// load/store register offset

   592 							if (arm_load(inst)) // bit 20

   593 								{

   594 								// loading a register from memory

   595 								if (arm_rd(inst) == PC_REGISTER)

   596 									{

   597 									// loading the PC register

   598 									TUint32 base = 0;

   599 									if(arm_rn(inst) == PC_REGISTER)

   600 										{

   601 										base = aCurrentPC + 8;

   602 										}

   603 									else

   604 										{

   605 										err = iChannel->ReadKernelRegisterValue(aThread, arm_rn(inst), base);

   606 										if(err != KErrNone)

   607 											{

   608 											LOG_MSG2("Non-zero error code discarded: %d", err);

   609 											}

   610 										}

   611 

   612 									TUint32 offset = 0;

   613 

   614 									if (arm_single_pre(inst))

   615 										{

   616 										offset = ShiftedRegValue(aThread, inst, aCurrentPC, aStatusRegister);

   617 

   618 										if (arm_single_u(inst))

   619 											{

   620 											base += offset;

   621 											}

   622 										else

   623 											{

   624 											base -= offset;

   625 											}

   626 										}

   627 

   628 									TBuf8<4> destination;

   629 									err = iChannel->DoReadMemory(aThread, base, 4, destination);

   630 

   631 									if (KErrNone == err)

   632 										{

   633 										breakAddress = *(TUint32 *)destination.Ptr();

   634 

   635 										if ((breakAddress & 0x00000001) == 1)

   636 											{

   637 											aChangingModes = ETrue;

   638 											}

   639 										breakAddress &= 0xFFFFFFFE;

   640 										}

   641 									else

   642 										{

   643 										LOG_MSG("Error reading memory in decoding step instruction");

   644 										}

   645 									}

   646 								}

   647 							}

   648 						break;

   649 						}

   650 					case 4:

   651 						{

   652 						if ((inst & 0xF0000000) != 0xF0000000)

   653 							{

   654 							// load/store multiple

   655 							if (arm_load(inst)) // bit 20

   656 								{

   657 								// loading a register from memory

   658 								if (((inst & 0x00008000) >> 15))

   659 									{

   660 									// loading the PC register

   661 									TInt offset = 0;	

   662 									if (arm_block_u(inst))

   663 										{

   664 										TUint32 reglist = arm_block_reglist(inst);

   665 										offset = iChannel->Bitcount(reglist) * 4 - 4;

   666 										if (arm_block_pre(inst))

   667 											offset += 4;

   668 										}

   669 									else if (arm_block_pre(inst))

   670 										{

   671 										offset = -4;

   672 										}

   673 

   674 									TUint32 temp = 0;

   675 									err = iChannel->ReadKernelRegisterValue(aThread, arm_rn(inst), temp);

   676 									if(err != KErrNone)

   677 										{

   678 										LOG_MSG2("Non-zero error code discarded: %d", err);

   679 										}

   680 

   681 									temp += offset;

   682 

   683 									TBuf8<4> destination;

   684 									err = iChannel->DoReadMemory(aThread, temp, 4, destination);

   685 

   686 									if (KErrNone == err)

   687 										{

   688 										breakAddress = *(TUint32 *)destination.Ptr();

   689 										if ((breakAddress & 0x00000001) == 1)

   690 											{

   691 											aChangingModes = ETrue;

   692 											}

   693 										breakAddress &= 0xFFFFFFFE;

   694 										}

   695 									else

   696 										{

   697 										LOG_MSG("Error reading memory in decoding step instruction");

   698 										}

   699 									}

   700 								}

   701 							}

   702 						break;

   703 						}

   704 					case 5:

   705 						{

   706 						if ((inst & 0xF0000000) == 0xF0000000)

   707 							{

   708 							// BLX

   709 							breakAddress = (TUint32)arm_instr_b_dest(inst, aCurrentPC);

   710 

   711 							// Unconditionally change into Thumb mode

   712 							aChangingModes = ETrue;

   713 							breakAddress &= 0xFFFFFFFE;

   714 							}

   715 						else

   716 							{

   717 							if ((inst & 0x01000000)) // bit 24

   718 								{

   719 								// BL

   720 									breakAddress = (TUint32)arm_instr_b_dest(inst, aCurrentPC);

   721 								}

   722 							else

   723 								{

   724 								// B

   725 								breakAddress = (TUint32)arm_instr_b_dest(inst, aCurrentPC);

   726 								}

   727 							}

   728 						break;

   729 						} // case 5

   730 					} //switch(arm_opcode(inst)) // bits 27-25

   731 				} // if (IsExecuted(((inst>>28) & 0x0000000F), aStatusRegister)) 

   732 			} // case Debug::EArmMode:

   733 		break;

   734 

   735 		case Debug::EThumbMode:

   736 			{

   737 			// Thumb Mode

   738 			//

   739 			// Notes: This now includes the extra code

   740 			// required to decode V6T2 instructions

   741 			

   742 			LOG_MSG("DRMDStepping::PCAfterInstructionExecutes: Thumb Instruction");

   743 

   744 			TUint16 inst;

   745 

   746 			// Obtain the current instruction bit pattern

   747 			TUint32 inst32;

   748 			ReturnIfError(CurrentInstruction(aThread,inst32));

   749 

   750 			inst = static_cast<TUint16>(inst32 & 0xFFFF);

   751 

   752 			LOG_MSG2("Current Thumb instruction: 0x%x", inst);

   753 

   754 			// v6T2 instructions

   755 

   756 			// Note: v6T2 decoding is only enabled for DEBUG builds or if using an

   757 			// an ARM_V6T2 supporting build system. At the time of writing, no

   758 			// ARM_V6T2 supporting build system exists, so the stepping code cannot

   759 			// be said to be known to work. Hence it is not run for release builds

   760 

   761 			TBool use_v6t2_decodings = EFalse;

   762 

   763 #if defined(DEBUG) || defined(__ARMV6T2__)

   764 			use_v6t2_decodings = ETrue;

   765 #endif

   766 			// coverity[dead_error_line]

   767 			if (use_v6t2_decodings)

   768 				{

   769 				// 16-bit encodings

   770 

   771 				// A6.2.5 Misc 16-bit instructions

   772 				// DONE Compare and branch on zero (page A8-66)

   773 				// If then hints

   774 

   775 				// ARM ARM DDI0406A - section A8.6.27 CBNZ, CBZ

   776 				//

   777 				// Compare and branch on Nonzero and Compare and Branch on Zero.

   778 				if ((inst & 0xF500) == 0xB100)

   779 					{

   780 					LOG_MSG("ARM ARM DDI0406A - section A8.6.27 CBNZ, CBZ");

   781 

   782 					// Decoding as per ARM ARM description

   783 					TUint32 op = (inst & 0x0800) >> 11;

   784 					TUint32 i = (inst & 0x0200) >> 9;

   785 					TUint32 imm5 = (inst & 0x00F8) >> 3;

   786 					TUint32 Rn = inst & 0x0007;

   787 

   788 					TUint32 imm32 = (i << 6) | (imm5 << 1);

   789 

   790 					// Obtain value for register Rn

   791 					TUint32 RnVal = 0;

   792 					ReturnIfError(RegisterValue(aThread,Rn,RnVal));

   793 

   794 					if (op)

   795 						{

   796 						// nonzero

   797 						if (RnVal != 0x0)

   798 							{

   799 							// Branch

   800 							breakAddress = aCurrentPC + imm32;

   801 							}

   802 						}

   803 					else

   804 						{

   805 						// zero

   806 						if (RnVal == 0x0)

   807 							{

   808 							// Branch

   809 							breakAddress = aCurrentPC + imm32;

   810 							}

   811 						}

   812 				}

   813 

   814 				// ARM ARM DDI0406A - section A8.6.50 IT

   815 				//

   816 				// If Then instruction

   817 				if ((inst & 0xFF00) == 0xBF00)

   818 					{

   819 					LOG_MSG("ARM ARM DDI0406A - section A8.6.50 IT");

   820 

   821 					// Decoding as per ARM ARM description

   822 					TUint32 firstcond = inst & 0x00F0 >> 4;

   823 					TUint32 mask = inst & 0x000F;

   824 

   825 					if (firstcond == 0xF)

   826 						{

   827 						// unpredictable

   828 						LOG_MSG("ARM ARM DDI0406A - section A8.6.50 IT - Unpredictable");

   829 						break;

   830 						}

   831 

   832 					if ((firstcond == 0xE) && (BitCount(mask) != 1))

   833 						{

   834 						// unpredictable

   835 						LOG_MSG("ARM ARM DDI0406A - section A8.6.50 IT - Unpredictable");

   836 						break;

   837 						}

   838 

   839 					// should check if 'in-it-block'

   840 					LOG_MSG("Cannot step IT instructions.");

   841 

   842 					// all the conds are as per Table A8-1 (i.e. the usual 16 cases)

   843 					// no idea how to decode the it block 'after-the-fact'

   844 					// so probably need to treat instructions in the it block

   845 					// as 'may' be executed. So breakpoints at both possible locations

   846 					// depending on whether the instruction is executed or not.

   847 

   848 					// also, how do we know if we have hit a breakpoint whilst 'in' an it block?

   849 					// can we check the status registers to find out?

   850 					//

   851 					// see arm arm page 390.

   852 					//

   853 					// seems to depend on the itstate field. this also says what the condition code

   854 					// actually is, and how many instructions are left in the itblock.

   855 					// perhaps we can just totally ignore this state, and always do the two-instruction

   856 					// breakpoint thing? Not if there is any possibility that the address target

   857 					// would be invalid for the non-taken branch address...

   858 					}

   859 

   860 

   861 				// 32-bit encodings.

   862 				//

   863 

   864 				// Load word A6-23

   865 				// Data processing instructions a6-28

   866 				// 

   867 

   868 				// ARM ARM DDI0406A - section A8.6.26

   869 				if (inst32 & 0xFFF0FFFF == 0xE3C08F00)

   870 					{

   871 					LOG_MSG("ARM ARM DDI0406A - section A8.6.26 - BXJ is not supported");

   872 

   873 					// Decoding as per ARM ARM description

   874 					// TUint32 Rm = inst32 & 0x000F0000;	// not needed yet

   875 					}

   876 

   877 				// return from exception... SUBS PC,LR. page b6-25

   878 				//

   879 				// ARM ARM DDi046A - section B6.1.13 - SUBS PC,LR

   880 				//

   881 				// Encoding T1

   882 				if (inst32 & 0xFFFFFF00 == 0xF3DE8F00)

   883 					{

   884 					LOG_MSG("ARM ARM DDI0406A - section B6.1.13 - SUBS PC,LR Encoding T1");

   885 

   886 					// Decoding as per ARM ARM description

   887 					TUint32 imm8 = inst32 & 0x000000FF;

   888 					TUint32 imm32 = imm8;

   889 

   890 					// TUint32 register_form = EFalse;	// not needed for this decoding

   891 					// TUint32 opcode = 0x2;	// SUB	// not needed for this decoding

   892 					TUint32 n = 14;

   893 

   894 					// Obtain LR

   895 					TUint32 lrVal;

   896 					ReturnIfError(RegisterValue(aThread,n,lrVal));

   897 

   898 					TUint32 operand2 = imm32;	// always for Encoding T1

   899 					

   900 					TUint32 result = lrVal - operand2;

   901 					

   902 					breakAddress = result;

   903 					}

   904 

   905 				// ARM ARM DDI0406A - section A8.6.16 - B

   906 				//

   907 				// Branch Encoding T3

   908 				if (inst32 & 0xF800D000 == 0xF0008000)

   909 					{

   910 					LOG_MSG("ARM ARM DDI0406A - section A8.6.16 - B Encoding T3");

   911 

   912 					// Decoding as per ARM ARM description

   913 					TUint32 S = inst32 & 0x04000000 >> 26;

   914 					// TUint32 cond = inst32 & 0x03C00000 >> 22;	// not needed for this decoding

   915 					TUint32 imm6 = inst32 & 0x003F0000 >> 16;

   916 					TUint32 J1 = inst32 & 0x00002000 >> 13;

   917 					TUint32 J2 = inst32 & 0x00000800 >> 11;

   918 					TUint32 imm11 = inst32 & 0x000007FF;

   919 

   920 					TUint32 imm32 = S ? 0xFFFFFFFF : 0 ;

   921 					imm32 = (imm32 << 1) | J2;

   922 					imm32 = (imm32 << 1) | J1;

   923 					imm32 = (imm32 << 6) | imm6;

   924 					imm32 = (imm32 << 11) | imm11;

   925 					imm32 = (imm32 << 1) | 0;

   926 

   927 					breakAddress = aCurrentPC + imm32;

   928 					}

   929 

   930 				// ARM ARM DDI0406A - section A8.6.16 - B

   931 				//

   932 				// Branch Encoding T4

   933 				if (inst32 & 0xF800D000 == 0xF0009000)

   934 					{

   935 					LOG_MSG("ARM ARM DDI0406A - section A8.6.16 - B");

   936 

   937 					// Decoding as per ARM ARM description

   938 					TUint32 S = inst32 & 0x04000000 >> 26;

   939 					TUint32 imm10 = inst32 & 0x03FF0000 >> 16;

   940 					TUint32 J1 = inst32 & 0x00002000 >> 12;

   941 					TUint32 J2 = inst32 & 0x00000800 >> 11;

   942 					TUint32 imm11 = inst32 & 0x000003FF;

   943 

   944 					TUint32 I1 = !(J1 ^ S);

   945 					TUint32 I2 = !(J2 ^ S);

   946 

   947 					TUint32 imm32 = S ? 0xFFFFFFFF : 0;

   948 					imm32 = (imm32 << 1) | S;

   949 					imm32 = (imm32 << 1) | I1;

   950 					imm32 = (imm32 << 1) | I2;

   951 					imm32 = (imm32 << 10) | imm10;

   952 					imm32 = (imm32 << 11) | imm11;

   953 					imm32 = (imm32 << 1) | 0;

   954 

   955 					breakAddress = aCurrentPC + imm32;

   956 					}

   957 

   958 

   959 				// ARM ARM DDI0406A - section A8.6.225 - TBB, TBH

   960 				//

   961 				// Table Branch Byte, Table Branch Halfword

   962 				if (inst32 & 0xFFF0FFE0 == 0xE8D0F000)

   963 						{

   964 					LOG_MSG("ARM ARM DDI0406A - section A8.6.225 TBB,TBH Encoding T1");

   965 

   966 					// Decoding as per ARM ARM description

   967 					TUint32 Rn = inst32 & 0x000F0000 >> 16;

   968 					TUint32 H = inst32 & 0x00000010 >> 4;

   969 					TUint32 Rm = inst32 & 0x0000000F;

   970 

   971 					// Unpredictable?

   972 					if (Rm == 13 || Rm == 15)

   973 						{

   974 						LOG_MSG("ARM ARM DDI0406A - section A8.6.225 TBB,TBH Encoding T1 - Unpredictable");

   975 						break;

   976 						}

   977 

   978 					TUint32 halfwords;

   979 					TUint32 address;

   980 					ReturnIfError(RegisterValue(aThread,Rn,address));

   981 

   982 					TUint32 offset;

   983 					ReturnIfError(RegisterValue(aThread,Rm,offset));

   984 

   985 					if (H)

   986 						{

   987 						address += offset << 1;

   988 						}

   989 					else

   990 						{

   991 						address += offset;

   992 						}

   993 

   994 					ReturnIfError(ReadMem32(aThread,address,halfwords));

   995 

   996 					breakAddress = aCurrentPC + 2*halfwords;

   997 					break;

   998 					}

   999 

  1000 				// ARM ARM DDI0406A - section A8.6.55 - LDMDB, LDMEA

  1001 				//

  1002 				// LDMDB Encoding T1

  1003 				if (inst32 & 0xFFD02000 == 0xE9100000)

  1004 					{

  1005 					LOG_MSG("ARM ARM DDI0406 - section A8.6.55 LDMDB Encoding T1");

  1006 

  1007 					// Decoding as per ARM ARM description

  1008 					// TUint32 W = inst32 & 0x00200000 >> 21;	// Not needed for this encoding

  1009 					TUint32 Rn = inst32 & 0x000F0000 >> 16;

  1010 					TUint32 P = inst32 & 0x00008000 >> 15;

  1011 					TUint32 M = inst32 & 0x00004000 >> 14;

  1012 					TUint32 registers = inst32 & 0x00001FFF;

  1013 

  1014 					//TBool wback = (W == 1);	// not needed for this encoding

  1015 

  1016 					// Unpredictable?

  1017 					if (Rn == 15 || BitCount(registers) < 2 || ((P == 1) && (M==1)))

  1018 						{

  1019 						LOG_MSG("ARM ARM DDI0406 - section A8.6.55 LDMDB Encoding T1 - Unpredictable");

  1020 						break;

  1021 						}

  1022 

  1023 					TUint32 address;

  1024 					ReturnIfError(RegisterValue(aThread,Rn,address));

  1025 

  1026 					address -= 4*BitCount(registers);

  1027 

  1028 					for(TInt i=0; i<15; i++)

  1029 						{

  1030 						if (IsBitSet(registers,i))

  1031 							{

  1032 							address +=4;

  1033 							}

  1034 						}

  1035 

  1036 					if (IsBitSet(registers,15))

  1037 						{

  1038 						TUint32 RnVal = 0;

  1039 						ReturnIfError(ReadMem32(aThread,address,RnVal));

  1040 

  1041 						breakAddress = RnVal;

  1042 						}

  1043 					break;

  1044 					}

  1045 

  1046 				// ARM ARM DDI0406A - section A8.6.121 POP

  1047 				//

  1048 				// POP.W Encoding T2

  1049 				if (inst32 & 0xFFFF2000 == 0xE8BD0000)

  1050 					{

  1051 					LOG_MSG("ARM ARM DDI0406A - section A8.6.121 POP Encoding T2");

  1052 

  1053 					// Decoding as per ARM ARM description

  1054 					TUint32 registers = inst32 & 0x00001FFF;

  1055 					TUint32 P = inst32 & 0x00008000;

  1056 					TUint32 M = inst32 & 0x00004000;

  1057 

  1058 					// Unpredictable?

  1059 					if ( (BitCount(registers)<2) || ((P == 1)&&(M == 1)) )

  1060 						{

  1061 						LOG_MSG("ARM ARM DDI0406A - section A8.6.121 POP Encoding T2 - Unpredictable");

  1062 						break;

  1063 						}

  1064 

  1065 					TUint32 address;

  1066 					ReturnIfError(RegisterValue(aThread,13,address));

  1067 					

  1068 					for(TInt i=0; i< 15; i++)

  1069 						{

  1070 						if (IsBitSet(registers,i))

  1071 							{

  1072 							address += 4;

  1073 							}

  1074 						}

  1075 

  1076 					// Is the PC written?

  1077 					if (IsBitSet(registers,15))

  1078 						{

  1079 						// Yes

  1080 						ReturnIfError(ReadMem32(aThread,address,breakAddress));

  1081 						}

  1082 					}

  1083 

  1084 				// POP Encoding T3

  1085 				if (inst32 & 0xFFFF0FFFF == 0xF85D0B04)

  1086 					{

  1087 					LOG_MSG("ARM ARM DDI0406A - section A8.6.121 POP Encoding T3");

  1088 

  1089 					// Decoding as per ARM ARM description

  1090 					TUint32 Rt = inst32 & 0x0000F000 >> 12;

  1091 					TUint32 registers = 1 << Rt;

  1092 

  1093 					// Unpredictable?

  1094 					if (Rt == 13 || Rt == 15)

  1095 						{

  1096 						LOG_MSG("ARM ARM DDI0406A - section A8.6.121 POP Encoding T3 - Unpredictable");

  1097 						break;

  1098 						}

  1099 					

  1100 					TUint32 address;

  1101 					ReturnIfError(RegisterValue(aThread,13,address));

  1102 					

  1103 					for(TInt i=0; i< 15; i++)

  1104 						{

  1105 						if (IsBitSet(registers,i))

  1106 							{

  1107 							address += 4;

  1108 							}

  1109 						}

  1110 

  1111 					// Is the PC written?

  1112 					if (IsBitSet(registers,15))

  1113 						{

  1114 						// Yes

  1115 						ReturnIfError(ReadMem32(aThread,address,breakAddress));

  1116 						}

  1117 

  1118 					break;

  1119 					}

  1120 

  1121 				// ARM ARM DDI0406A - section A8.6.53 LDM

  1122 				//

  1123 				// Load Multiple Encoding T2 

  1124 				if ((inst32 & 0xFFD02000) == 0xE8900000)

  1125 					{

  1126 					LOG_MSG("ARM ARM DDI0406A - section A8.6.53 LDM Encoding T2");

  1127 

  1128 					// Decoding as per ARM ARM description

  1129 					TUint32 W = inst32 & 0x0020000 >> 21;

  1130 					TUint32 Rn = inst32 & 0x000F0000 >> 16;

  1131 					TUint32 P = inst32 & 0x00008000 >> 15;

  1132 					TUint32 M = inst32 & 0x00004000 >> 14;

  1133 					TUint32 registers = inst32 & 0x0000FFFF;

  1134 					TUint32 register_list = inst32 & 0x00001FFF;