debugsrv/runmodedebug/rmdriver/src/d_rmd_stepping.cpp
changeset 45 185201be11b0
child 56 aa2539c91954
equal deleted inserted replaced
38:169364e7e4b4 45:185201be11b0
       
     1 // Copyright (c) 2004-2009 Nokia Corporation and/or its subsidiary(-ies).
       
     2 // All rights reserved.
       
     3 // This component and the accompanying materials are made available
       
     4 // under the terms of the License "Eclipse Public License v1.0"
       
     5 // which accompanies this distribution, and is available
       
     6 // at the URL "http://www.eclipse.org/legal/epl-v10.html".
       
     7 //
       
     8 // Initial Contributors:
       
     9 // Nokia Corporation - initial contribution.
       
    10 //
       
    11 // Contributors:
       
    12 //
       
    13 // Description:
       
    14 // This file contains stepping code refactored from rm_debug_kerneldriver.cpp/rm_debug_kerneldriver.h
       
    15 //
       
    16 
       
    17 #include <e32def.h>
       
    18 #include <e32def_private.h>
       
    19 #include <e32cmn.h>
       
    20 #include <e32cmn_private.h>
       
    21 #include <kernel/kernel.h> 
       
    22 #include <kernel/kern_priv.h>
       
    23 #include <nk_trace.h>
       
    24 #include <arm.h>
       
    25 #include <rm_debug_api.h>
       
    26 
       
    27 #include "d_rmd_stepping.h"
       
    28 #include "d_rmd_breakpoints.h"
       
    29 #include "rm_debug_kerneldriver.h"	// needed to access DRM_DebugChannel
       
    30 #include "rm_debug_driver.h"
       
    31 #include "debug_logging.h"
       
    32 
       
    33 using namespace Debug;
       
    34 
       
    35 //
       
    36 // DRMDStepping::DRMDStepping
       
    37 //
       
    38 DRMDStepping::DRMDStepping(DRM_DebugChannel* aChannel)
       
    39 :
       
    40 	iChannel(aChannel)
       
    41 	{
       
    42 	// to do
       
    43 	}
       
    44 
       
    45 //
       
    46 // DRMDStepping::~DRM_DebugChannel
       
    47 //
       
    48 DRMDStepping::~DRMDStepping()
       
    49 	{
       
    50 	// to do
       
    51 	}
       
    52 
       
    53 //
       
    54 // DRMDStepping::IsExecuted
       
    55 //
       
    56 TBool DRMDStepping::IsExecuted(TUint8 aCondition ,TUint32 aStatusRegister)
       
    57 	{
       
    58 	LOG_MSG("DRMDStepping::IsExecuted()");
       
    59 
       
    60 	TBool N = ((aStatusRegister >> 28) & 0x0000000F) & 0x00000008;
       
    61 	TBool Z = ((aStatusRegister >> 28) & 0x0000000F) & 0x00000004;
       
    62 	TBool C = ((aStatusRegister >> 28) & 0x0000000F) & 0x00000002;
       
    63 	TBool V = ((aStatusRegister >> 28) & 0x0000000F) & 0x00000001;
       
    64 
       
    65 	switch(aCondition)
       
    66 		{
       
    67 		case 0:
       
    68 			return Z;
       
    69 		case 1:
       
    70 			return !Z;
       
    71 		case 2:
       
    72 			return C;
       
    73 		case 3:
       
    74 			return !C;
       
    75 		case 4:
       
    76 			return N;
       
    77 		case 5:
       
    78 			return !N;
       
    79 		case 6:
       
    80 			return V;
       
    81 		case 7:
       
    82 			return !V;
       
    83 		case 8:
       
    84 			return (C && !Z);
       
    85 		case 9:
       
    86 			return (!C || Z);
       
    87 		case 10:
       
    88 			return (N == V);
       
    89 		case 11:
       
    90 			return (N != V);
       
    91 		case 12:
       
    92 			return ((N == V) && !Z);
       
    93 		case 13:
       
    94 			return (Z || (N != V));
       
    95 		case 14:
       
    96 		case 15:
       
    97 			return ETrue;
       
    98 		}
       
    99 	
       
   100 	return EFalse;
       
   101 	}
       
   102 
       
   103 //
       
   104 // DRMDStepping::IsPreviousInstructionMovePCToLR
       
   105 //
       
   106 TBool DRMDStepping::IsPreviousInstructionMovePCToLR(DThread *aThread)
       
   107 	{
       
   108 	LOG_MSG("DRMDStepping::IsPreviousInstructionMovePCToLR()");
       
   109 
       
   110 	TInt err = KErrNone;
       
   111 	
       
   112 	// there are several types of instructions that modify the PC that aren't
       
   113 	// designated as linked or non linked branches.  the way gcc generates the
       
   114 	// code can tell us whether or not these instructions are to be treated as
       
   115 	// linked branches.  the main cases are bx and any type of mov or load or
       
   116 	// arithmatic operation that changes the PC.  if these are really just
       
   117 	// function calls that will return, gcc will generate a mov	lr, pc
       
   118 	// instruction as the previous instruction.  note that this is just for arm
       
   119 	// and armi
       
   120 	
       
   121 	// get the address of the previous instruction
       
   122 	TUint32 address = 0;
       
   123 	err = iChannel->ReadKernelRegisterValue(aThread, PC_REGISTER, address);
       
   124 	if(err != KErrNone)
       
   125 		{
       
   126 		LOG_MSG2("Non-zero error code discarded: %d", err);
       
   127 		}
       
   128 	address -= 4;
       
   129 
       
   130 	TBuf8<4> previousInstruction;
       
   131 	err = iChannel->DoReadMemory(aThread, address, 4, previousInstruction);
       
   132 	if (KErrNone != err)
       
   133 		{
       
   134 		LOG_MSG2("Error %d reading memory at address %x", address);
       
   135 		return EFalse;
       
   136 		}
       
   137 
       
   138 	const TUint32 movePCToLRIgnoringCondition = 0x01A0E00F;
       
   139 
       
   140 	TUint32 inst = *(TUint32 *)previousInstruction.Ptr();
       
   141 	
       
   142 	if ((inst & 0x0FFFFFFF) == movePCToLRIgnoringCondition)
       
   143 		{
       
   144 		return ETrue;
       
   145 		}
       
   146 		
       
   147 	return EFalse;
       
   148 	}
       
   149 
       
   150 //
       
   151 // DRMDStepping::DecodeDataProcessingInstruction
       
   152 //
       
   153 void DRMDStepping::DecodeDataProcessingInstruction(TUint8 aOpcode, TUint32 aOp1, TUint32 aOp2, TUint32 aStatusRegister, TUint32 &aBreakAddress)
       
   154 	{
       
   155 	LOG_MSG("DRMDStepping::DecodeDataProcessingInstruction()");
       
   156 
       
   157 	switch(aOpcode)
       
   158 		{
       
   159 		case 0:
       
   160 			{
       
   161 			// AND
       
   162 			aBreakAddress = aOp1 & aOp2;
       
   163 			break;
       
   164 			}
       
   165 		case 1:
       
   166 			{
       
   167 			// EOR
       
   168 			aBreakAddress = aOp1 ^ aOp2;
       
   169 			break;
       
   170 			}
       
   171 		case 2:
       
   172 			{
       
   173 			// SUB
       
   174 			aBreakAddress = aOp1 - aOp2;
       
   175 			break;
       
   176 			}
       
   177 		case 3:
       
   178 			{
       
   179 			// RSB
       
   180 			aBreakAddress = aOp2 - aOp1;
       
   181 			break;
       
   182 			}
       
   183 		case 4:
       
   184 			{
       
   185 			// ADD
       
   186 			aBreakAddress = aOp1 + aOp2;
       
   187 			break;
       
   188 			}
       
   189 		case 5:
       
   190 			{
       
   191 			// ADC
       
   192 			aBreakAddress = aOp1 + aOp2 + (aStatusRegister & arm_carry_bit()) ? 1 : 0;
       
   193 			break;
       
   194 			}
       
   195 		case 6:
       
   196 			{
       
   197 			// SBC
       
   198 			aBreakAddress = aOp1 - aOp2 - (aStatusRegister & arm_carry_bit()) ? 0 : 1;
       
   199 			break;
       
   200 			}
       
   201 		case 7:
       
   202 			{
       
   203 			// RSC
       
   204 			aBreakAddress = aOp2 - aOp1 - (aStatusRegister & arm_carry_bit()) ? 0 : 1;
       
   205 			break;
       
   206 			}
       
   207 		case 12:
       
   208 			{
       
   209 			// ORR
       
   210 			aBreakAddress = aOp1 | aOp2;
       
   211 			break;
       
   212 			}
       
   213 		case 13:
       
   214 			{
       
   215 			// MOV
       
   216 			aBreakAddress = aOp2;
       
   217 			break;
       
   218 			}
       
   219 		case 14:
       
   220 			{
       
   221 			// BIC
       
   222 			aBreakAddress = aOp1 & ~aOp2;
       
   223 			break;
       
   224 			}
       
   225 		case 15:
       
   226 			{
       
   227 			// MVN
       
   228 			aBreakAddress = ~aOp2;
       
   229 			break;
       
   230 			}
       
   231 		}
       
   232 	}
       
   233 
       
   234 //
       
   235 // DRMDStepping::CurrentInstruction
       
   236 //
       
   237 // Returns the current instruction bitpattern (either 32-bits or 16-bits) if possible
       
   238 TInt DRMDStepping::CurrentInstruction(DThread* aThread, TUint32& aInstruction)
       
   239 	{
       
   240 	LOG_MSG("DRMDStepping::CurrentInstruction");
       
   241 
       
   242 	// What is the current PC?
       
   243 	TUint32 pc;	
       
   244 	ReturnIfError(CurrentPC(aThread,pc));
       
   245 
       
   246 	// Read it one byte at a time to ensure alignment doesn't matter
       
   247 	TUint32 inst = 0;
       
   248 	for(TInt i=3;i>=0;i--)
       
   249 		{
       
   250 
       
   251 		TBuf8<1> instruction;
       
   252 		TInt err = iChannel->DoReadMemory(aThread, (pc+i), 1, instruction); 
       
   253 		if (KErrNone != err)
       
   254 			{
       
   255 			LOG_MSG2("DRMDStepping::CurrentInstruction : Failed to read memory at current PC: return 0x%08x",pc);
       
   256 			return err;
       
   257 			}
       
   258 
       
   259 		inst = (inst << 8) | (*(TUint8 *)instruction.Ptr());
       
   260 		}
       
   261 
       
   262 	aInstruction = inst;
       
   263 
       
   264 	LOG_MSG2("DRMDStepping::CurrentInstruction 0x%08x", aInstruction);
       
   265 
       
   266 	return KErrNone;
       
   267 	}
       
   268 
       
   269 //
       
   270 // DRMDStepping::CurrentArchMode
       
   271 //
       
   272 // Determines architecture mode from the supplied cpsr
       
   273 TInt DRMDStepping::CurrentArchMode(const TUint32 aCpsr, Debug::TArchitectureMode& aMode)
       
   274 	{
       
   275 // Thumb2 work will depend on having a suitable cpu architecture to compile for...
       
   276 #ifdef ECpuJf
       
   277 	// State table as per ARM ARM DDI0406A, section A.2.5.1
       
   278 	if(aCpsr & ECpuJf)
       
   279 		{
       
   280 		if (aCpsr & ECpuThumb)
       
   281 			{
       
   282 			// ThumbEE (Thumb2)
       
   283 			aMode = Debug::EThumb2EEMode;
       
   284 			}
       
   285 		else
       
   286 			{
       
   287 			// Jazelle mode - not supported
       
   288 			return KErrNotSupported;
       
   289 			}
       
   290 		}
       
   291 	else
       
   292 #endif
       
   293 		{
       
   294 		if (aCpsr & ECpuThumb)
       
   295 			{
       
   296 			// Thumb mode
       
   297 			aMode = Debug::EThumbMode;
       
   298 			}
       
   299 		else
       
   300 			{
       
   301 			// ARM mode
       
   302 			aMode = Debug::EArmMode;
       
   303 			}
       
   304 		}
       
   305 
       
   306 	return KErrNone;
       
   307 	}
       
   308 
       
   309 //
       
   310 // DRMDStepping::PCAfterInstructionExecutes
       
   311 //
       
   312 // Note, this function pretty much ignores all the arguments except for aThread.
       
   313 // The arguments continue to exist so that the function has the same prototype as
       
   314 // the original from Nokia. In the long term this function will be re-factored
       
   315 // to remove obsolete parameters.
       
   316 //
       
   317 TUint32 DRMDStepping::PCAfterInstructionExecutes(DThread *aThread, TUint32 aCurrentPC, TUint32 aStatusRegister, TInt aInstSize, /*TBool aStepInto,*/ TUint32 &aNewRangeEnd, TBool &aChangingModes)
       
   318 	{
       
   319 	LOG_MSG("DRMDStepping::PCAfterInstructionExecutes()");
       
   320 
       
   321 	// by default we will set the breakpoint at the next instruction
       
   322 	TUint32 breakAddress = aCurrentPC + aInstSize;
       
   323 
       
   324 	TInt err = KErrNone;
       
   325 
       
   326 	// determine the architecture
       
   327 	TUint32 cpuid;
       
   328 	asm("mrc p15, 0, cpuid, c0, c0, 0 ");
       
   329 	LOG_MSG2("DRMDStepping::PCAfterInstructionExecutes() - cpuid = 0x%08x\n",cpuid);
       
   330 
       
   331 	cpuid >>= 8;
       
   332 	cpuid &= 0xFF;
       
   333 
       
   334 	// determine the architecture mode for the current instruction
       
   335 	TArchitectureMode mode = EArmMode;	// Default assumption is ARM 
       
   336 
       
   337 	// Now we must examine the CPSR to read the T and J bits. See ARM ARM DDI0406A, section B1.3.3
       
   338 	TUint32 cpsr;
       
   339 
       
   340 	ReturnIfError(CurrentCPSR(aThread,cpsr));
       
   341 	LOG_MSG2("DRMDStepping::PCAfterInstructionExecutes() - cpsr = 0x%08x\n",cpsr);
       
   342 
       
   343 	// Determine the mode
       
   344 	ReturnIfError(CurrentArchMode(cpsr,mode));
       
   345 
       
   346 	// Decode instruction based on current CPU mode
       
   347 	switch(mode)
       
   348 		{
       
   349 		case Debug::EArmMode:
       
   350 			{
       
   351 			// Obtain the current instruction bit pattern
       
   352 			TUint32 inst;
       
   353 			ReturnIfError(CurrentInstruction(aThread,inst));
       
   354 			
       
   355 			LOG_MSG2("Current instruction: %x", inst);
       
   356 
       
   357 			// check the conditions to see if this will actually get executed
       
   358 			if (IsExecuted(((inst>>28) & 0x0000000F), aStatusRegister)) 
       
   359 				{
       
   360 				switch(arm_opcode(inst)) // bits 27-25
       
   361 					{
       
   362 					case 0:
       
   363 						{
       
   364 						switch((inst & 0x00000010) >> 4) // bit 4
       
   365 							{
       
   366 							case 0:
       
   367 								{
       
   368 								switch((inst & 0x01800000) >> 23) // bits 24-23
       
   369 									{
       
   370 									case 2:
       
   371 										{
       
   372 										// move to/from status register.  pc updates not allowed
       
   373 										// or TST, TEQ, CMP, CMN which don't modify the PC
       
   374 										break;
       
   375 										}
       
   376 									default:
       
   377 										{
       
   378 										// Data processing immediate shift
       
   379 										if (arm_rd(inst) == PC_REGISTER)
       
   380 											{
       
   381 											TUint32 rn = aCurrentPC + 8;
       
   382 											if (arm_rn(inst) != PC_REGISTER) // bits 19-16
       
   383 												{
       
   384 												err = iChannel->ReadKernelRegisterValue(aThread, arm_rn(inst), rn);
       
   385 												if(err != KErrNone)
       
   386 													{
       
   387 													LOG_MSG2("Non-zero error code discarded: %d", err);
       
   388 													}
       
   389 												}
       
   390 
       
   391 											TUint32 shifter = ShiftedRegValue(aThread, inst, aCurrentPC, aStatusRegister);
       
   392 
       
   393 											DecodeDataProcessingInstruction(((inst & 0x01E00000) >> 21), rn, shifter, aStatusRegister, breakAddress);
       
   394 											}
       
   395 										break;
       
   396 										}
       
   397 									}
       
   398 								break;
       
   399 								}
       
   400 							case 1:
       
   401 								{
       
   402 								switch((inst & 0x00000080) >> 7) // bit 7
       
   403 									{
       
   404 									case 0:
       
   405 										{
       
   406 										switch((inst & 0x01900000) >> 20) // bits 24-23 and bit 20
       
   407 											{
       
   408 											case 0x10:
       
   409 												{
       
   410 												// from figure 3-3
       
   411 												switch((inst & 0x000000F0) >> 4) // bits 7-4
       
   412 													{
       
   413 													case 1:
       
   414 														{
       
   415 														if (((inst & 0x00400000) >> 22) == 0) // bit 22
       
   416 															{
       
   417 															// BX
       
   418 															// this is a strange case.  normally this is used in the epilogue to branch the the link
       
   419 															// register.  sometimes it is used to call a function, and the LR is stored in the previous
       
   420 															// instruction.  since what we want to do is different for the two cases when stepping over,
       
   421 															// we need to read the previous instruction to see what we should do
       
   422 															err = iChannel->ReadKernelRegisterValue(aThread, (inst & 0x0000000F), breakAddress);
       
   423 															if(err != KErrNone)
       
   424 																{
       
   425 																LOG_MSG2("Non-zero error code discarded: %d", err);
       
   426 																}
       
   427 
       
   428 															if ((breakAddress & 0x00000001) == 1)
       
   429 																{
       
   430 																aChangingModes = ETrue;
       
   431 																}
       
   432 
       
   433 															breakAddress &= 0xFFFFFFFE;
       
   434 															}
       
   435 														break;
       
   436 														}
       
   437 													case 3:
       
   438 														{
       
   439 														// BLX
       
   440 															{
       
   441 															err = iChannel->ReadKernelRegisterValue(aThread, (inst & 0x0000000F), breakAddress);
       
   442 															if(err != KErrNone)
       
   443 																{
       
   444 																LOG_MSG2("Non-zero error code discarded: %d", err);
       
   445 																}
       
   446 
       
   447 															if ((breakAddress & 0x00000001) == 1)
       
   448 																{
       
   449 																aChangingModes = ETrue;
       
   450 																}
       
   451 															
       
   452 															breakAddress &= 0xFFFFFFFE;
       
   453 															}
       
   454 														break;
       
   455 														}
       
   456 													default:
       
   457 														{
       
   458 														// either doesn't modify the PC or it is illegal to
       
   459 														break;
       
   460 														}
       
   461 													}
       
   462 												break;
       
   463 												}
       
   464 											default:
       
   465 												{
       
   466 												// Data processing register shift
       
   467 												if (((inst & 0x01800000) >> 23) == 2) // bits 24-23
       
   468 													{
       
   469 													// TST, TEQ, CMP, CMN don't modify the PC
       
   470 													}
       
   471 												else if (arm_rd(inst) == PC_REGISTER)
       
   472 													{
       
   473 													// destination register is the PC
       
   474 													TUint32 rn = aCurrentPC + 8;
       
   475 													if (arm_rn(inst) != PC_REGISTER) // bits 19-16
       
   476 														{
       
   477 														err = iChannel->ReadKernelRegisterValue(aThread, arm_rn(inst), rn);
       
   478 														if(err != KErrNone)
       
   479 															{
       
   480 															LOG_MSG2("Non-zero error code discarded: %d", err);
       
   481 															}
       
   482 														}
       
   483 													
       
   484 													TUint32 shifter = ShiftedRegValue(aThread, inst, aCurrentPC, aStatusRegister);
       
   485 													
       
   486 													DecodeDataProcessingInstruction(((inst & 0x01E00000) >> 21), rn, shifter, aStatusRegister, breakAddress);
       
   487 													}
       
   488 												break;
       
   489 												}
       
   490 											}
       
   491 										break;
       
   492 										}
       
   493 									default:
       
   494 										{
       
   495 										// from figure 3-2, updates to the PC illegal
       
   496 										break;
       
   497 										}
       
   498 									}
       
   499 								break;
       
   500 								}
       
   501 							}
       
   502 						break;
       
   503 						}
       
   504 					case 1:
       
   505 						{
       
   506 						if (((inst & 0x01800000) >> 23) == 2) // bits 24-23
       
   507 							{
       
   508 							// cannot modify the PC
       
   509 							break;
       
   510 							}
       
   511 						else if (arm_rd(inst) == PC_REGISTER)
       
   512 							{
       
   513 							// destination register is the PC
       
   514 							TUint32 rn;
       
   515 							err = iChannel->ReadKernelRegisterValue(aThread, arm_rn(inst), rn); // bits 19-16
       
   516 							if(err != KErrNone)
       
   517 								{
       
   518 								LOG_MSG2("Non-zero error code discarded: %d", err);
       
   519 								}
       
   520 							TUint32 shifter = ((arm_data_imm(inst) >> arm_data_rot(inst)) | (arm_data_imm(inst) << (32 - arm_data_rot(inst)))) & 0xffffffff;
       
   521 
       
   522 							DecodeDataProcessingInstruction(((inst & 0x01E00000) >> 21), rn, shifter, aStatusRegister, breakAddress);
       
   523 							}
       
   524 						break;
       
   525 						}
       
   526 					case 2:
       
   527 						{
       
   528 						// load/store immediate offset
       
   529 						if (arm_load(inst)) // bit 20
       
   530 							{
       
   531 							// loading a register from memory
       
   532 							if (arm_rd(inst) == PC_REGISTER)
       
   533 								{
       
   534 								// loading the PC register
       
   535 								TUint32 base;
       
   536 								err = iChannel->ReadKernelRegisterValue(aThread, arm_rn(inst), base);
       
   537 								if(err != KErrNone)
       
   538 									{
       
   539 									LOG_MSG2("Non-zero error code discarded: %d", err);
       
   540 									}
       
   541 
       
   542 								/* Note: At runtime the PC would be 8 further on
       
   543 								 */
       
   544 								if (arm_rn(inst) == PC_REGISTER)
       
   545 									{
       
   546 									base = aCurrentPC + 8;
       
   547 									}
       
   548 
       
   549 								TUint32 offset = 0;
       
   550 
       
   551 								if (arm_single_pre(inst))
       
   552 									{
       
   553 									// Pre-indexing
       
   554 									offset = arm_single_imm(inst);
       
   555 
       
   556 									if (arm_single_u(inst))
       
   557 										{
       
   558 										base += offset;
       
   559 										}
       
   560 									else
       
   561 										{
       
   562 										base -= offset;
       
   563 										}
       
   564 									}
       
   565 
       
   566 								TBuf8<4> destination;
       
   567 								err = iChannel->DoReadMemory(aThread, base, 4, destination);
       
   568 								
       
   569 								if (KErrNone == err)
       
   570 									{
       
   571 									breakAddress = *(TUint32 *)destination.Ptr();
       
   572 
       
   573 									if ((breakAddress & 0x00000001) == 1)
       
   574 										{
       
   575 										aChangingModes = ETrue;
       
   576 										}
       
   577 									breakAddress &= 0xFFFFFFFE;
       
   578 									}
       
   579 								else
       
   580 									{
       
   581 									LOG_MSG("Error reading memory in decoding step instruction");
       
   582 									}
       
   583 								}
       
   584 							}
       
   585 						break;
       
   586 						}
       
   587 					case 3:
       
   588 						{
       
   589 						if (((inst & 0xF0000000) != 0xF0000000) && ((inst & 0x00000010) == 0))
       
   590 							{
       
   591 							// load/store register offset
       
   592 							if (arm_load(inst)) // bit 20
       
   593 								{
       
   594 								// loading a register from memory
       
   595 								if (arm_rd(inst) == PC_REGISTER)
       
   596 									{
       
   597 									// loading the PC register
       
   598 									TUint32 base = 0;
       
   599 									if(arm_rn(inst) == PC_REGISTER)
       
   600 										{
       
   601 										base = aCurrentPC + 8;
       
   602 										}
       
   603 									else
       
   604 										{
       
   605 										err = iChannel->ReadKernelRegisterValue(aThread, arm_rn(inst), base);
       
   606 										if(err != KErrNone)
       
   607 											{
       
   608 											LOG_MSG2("Non-zero error code discarded: %d", err);
       
   609 											}
       
   610 										}
       
   611 
       
   612 									TUint32 offset = 0;
       
   613 
       
   614 									if (arm_single_pre(inst))
       
   615 										{
       
   616 										offset = ShiftedRegValue(aThread, inst, aCurrentPC, aStatusRegister);
       
   617 
       
   618 										if (arm_single_u(inst))
       
   619 											{
       
   620 											base += offset;
       
   621 											}
       
   622 										else
       
   623 											{
       
   624 											base -= offset;
       
   625 											}
       
   626 										}
       
   627 
       
   628 									TBuf8<4> destination;
       
   629 									err = iChannel->DoReadMemory(aThread, base, 4, destination);
       
   630 
       
   631 									if (KErrNone == err)
       
   632 										{
       
   633 										breakAddress = *(TUint32 *)destination.Ptr();
       
   634 
       
   635 										if ((breakAddress & 0x00000001) == 1)
       
   636 											{
       
   637 											aChangingModes = ETrue;
       
   638 											}
       
   639 										breakAddress &= 0xFFFFFFFE;
       
   640 										}
       
   641 									else
       
   642 										{
       
   643 										LOG_MSG("Error reading memory in decoding step instruction");
       
   644 										}
       
   645 									}
       
   646 								}
       
   647 							}
       
   648 						break;
       
   649 						}
       
   650 					case 4:
       
   651 						{
       
   652 						if ((inst & 0xF0000000) != 0xF0000000)
       
   653 							{
       
   654 							// load/store multiple
       
   655 							if (arm_load(inst)) // bit 20
       
   656 								{
       
   657 								// loading a register from memory
       
   658 								if (((inst & 0x00008000) >> 15))
       
   659 									{
       
   660 									// loading the PC register
       
   661 									TInt offset = 0;	
       
   662 									if (arm_block_u(inst))
       
   663 										{
       
   664 										TUint32 reglist = arm_block_reglist(inst);
       
   665 										offset = iChannel->Bitcount(reglist) * 4 - 4;
       
   666 										if (arm_block_pre(inst))
       
   667 											offset += 4;
       
   668 										}
       
   669 									else if (arm_block_pre(inst))
       
   670 										{
       
   671 										offset = -4;
       
   672 										}
       
   673 
       
   674 									TUint32 temp = 0;
       
   675 									err = iChannel->ReadKernelRegisterValue(aThread, arm_rn(inst), temp);
       
   676 									if(err != KErrNone)
       
   677 										{
       
   678 										LOG_MSG2("Non-zero error code discarded: %d", err);
       
   679 										}
       
   680 
       
   681 									temp += offset;
       
   682 
       
   683 									TBuf8<4> destination;
       
   684 									err = iChannel->DoReadMemory(aThread, temp, 4, destination);
       
   685 
       
   686 									if (KErrNone == err)
       
   687 										{
       
   688 										breakAddress = *(TUint32 *)destination.Ptr();
       
   689 										if ((breakAddress & 0x00000001) == 1)
       
   690 											{
       
   691 											aChangingModes = ETrue;
       
   692 											}
       
   693 										breakAddress &= 0xFFFFFFFE;
       
   694 										}
       
   695 									else
       
   696 										{
       
   697 										LOG_MSG("Error reading memory in decoding step instruction");
       
   698 										}
       
   699 									}
       
   700 								}
       
   701 							}
       
   702 						break;
       
   703 						}
       
   704 					case 5:
       
   705 						{
       
   706 						if ((inst & 0xF0000000) == 0xF0000000)
       
   707 							{
       
   708 							// BLX
       
   709 							breakAddress = (TUint32)arm_instr_b_dest(inst, aCurrentPC);
       
   710 
       
   711 							// Unconditionally change into Thumb mode
       
   712 							aChangingModes = ETrue;
       
   713 							breakAddress &= 0xFFFFFFFE;
       
   714 							}
       
   715 						else
       
   716 							{
       
   717 							if ((inst & 0x01000000)) // bit 24
       
   718 								{
       
   719 								// BL
       
   720 									breakAddress = (TUint32)arm_instr_b_dest(inst, aCurrentPC);
       
   721 								}
       
   722 							else
       
   723 								{
       
   724 								// B
       
   725 								breakAddress = (TUint32)arm_instr_b_dest(inst, aCurrentPC);
       
   726 								}
       
   727 							}
       
   728 						break;
       
   729 						} // case 5
       
   730 					} //switch(arm_opcode(inst)) // bits 27-25
       
   731 				} // if (IsExecuted(((inst>>28) & 0x0000000F), aStatusRegister)) 
       
   732 			} // case Debug::EArmMode:
       
   733 		break;
       
   734 
       
   735 		case Debug::EThumbMode:
       
   736 			{
       
   737 			// Thumb Mode
       
   738 			//
       
   739 			// Notes: This now includes the extra code
       
   740 			// required to decode V6T2 instructions
       
   741 			
       
   742 			LOG_MSG("DRMDStepping::PCAfterInstructionExecutes: Thumb Instruction");
       
   743 
       
   744 			TUint16 inst;
       
   745 
       
   746 			// Obtain the current instruction bit pattern
       
   747 			TUint32 inst32;
       
   748 			ReturnIfError(CurrentInstruction(aThread,inst32));
       
   749 
       
   750 			inst = static_cast<TUint16>(inst32 & 0xFFFF);
       
   751 
       
   752 			LOG_MSG2("Current Thumb instruction: 0x%x", inst);
       
   753 
       
   754 			// v6T2 instructions
       
   755 
       
   756 			// Note: v6T2 decoding is only enabled for DEBUG builds or if using an
       
   757 			// an ARM_V6T2 supporting build system. At the time of writing, no
       
   758 			// ARM_V6T2 supporting build system exists, so the stepping code cannot
       
   759 			// be said to be known to work. Hence it is not run for release builds
       
   760 
       
   761 			TBool use_v6t2_decodings = EFalse;
       
   762 
       
   763 #if defined(DEBUG) || defined(__ARMV6T2__)
       
   764 			use_v6t2_decodings = ETrue;
       
   765 #endif
       
   766 			// coverity[dead_error_line]
       
   767 			if (use_v6t2_decodings)
       
   768 				{
       
   769 				// 16-bit encodings
       
   770 
       
   771 				// A6.2.5 Misc 16-bit instructions
       
   772 				// DONE Compare and branch on zero (page A8-66)
       
   773 				// If then hints
       
   774 
       
   775 				// ARM ARM DDI0406A - section A8.6.27 CBNZ, CBZ
       
   776 				//
       
   777 				// Compare and branch on Nonzero and Compare and Branch on Zero.
       
   778 				if ((inst & 0xF500) == 0xB100)
       
   779 					{
       
   780 					LOG_MSG("ARM ARM DDI0406A - section A8.6.27 CBNZ, CBZ");
       
   781 
       
   782 					// Decoding as per ARM ARM description
       
   783 					TUint32 op = (inst & 0x0800) >> 11;
       
   784 					TUint32 i = (inst & 0x0200) >> 9;
       
   785 					TUint32 imm5 = (inst & 0x00F8) >> 3;
       
   786 					TUint32 Rn = inst & 0x0007;
       
   787 
       
   788 					TUint32 imm32 = (i << 6) | (imm5 << 1);
       
   789 
       
   790 					// Obtain value for register Rn
       
   791 					TUint32 RnVal = 0;
       
   792 					ReturnIfError(RegisterValue(aThread,Rn,RnVal));
       
   793 
       
   794 					if (op)
       
   795 						{
       
   796 						// nonzero
       
   797 						if (RnVal != 0x0)
       
   798 							{
       
   799 							// Branch
       
   800 							breakAddress = aCurrentPC + imm32;
       
   801 							}
       
   802 						}
       
   803 					else
       
   804 						{
       
   805 						// zero
       
   806 						if (RnVal == 0x0)
       
   807 							{
       
   808 							// Branch
       
   809 							breakAddress = aCurrentPC + imm32;
       
   810 							}
       
   811 						}
       
   812 				}
       
   813 
       
   814 				// ARM ARM DDI0406A - section A8.6.50 IT
       
   815 				//
       
   816 				// If Then instruction
       
   817 				if ((inst & 0xFF00) == 0xBF00)
       
   818 					{
       
   819 					LOG_MSG("ARM ARM DDI0406A - section A8.6.50 IT");
       
   820 
       
   821 					// Decoding as per ARM ARM description
       
   822 					TUint32 firstcond = inst & 0x00F0 >> 4;
       
   823 					TUint32 mask = inst & 0x000F;
       
   824 
       
   825 					if (firstcond == 0xF)
       
   826 						{
       
   827 						// unpredictable
       
   828 						LOG_MSG("ARM ARM DDI0406A - section A8.6.50 IT - Unpredictable");
       
   829 						break;
       
   830 						}
       
   831 
       
   832 					if ((firstcond == 0xE) && (BitCount(mask) != 1))
       
   833 						{
       
   834 						// unpredictable
       
   835 						LOG_MSG("ARM ARM DDI0406A - section A8.6.50 IT - Unpredictable");
       
   836 						break;
       
   837 						}
       
   838 
       
   839 					// should check if 'in-it-block'
       
   840 					LOG_MSG("Cannot step IT instructions.");
       
   841 
       
   842 					// all the conds are as per Table A8-1 (i.e. the usual 16 cases)
       
   843 					// no idea how to decode the it block 'after-the-fact'
       
   844 					// so probably need to treat instructions in the it block
       
   845 					// as 'may' be executed. So breakpoints at both possible locations
       
   846 					// depending on whether the instruction is executed or not.
       
   847 
       
   848 					// also, how do we know if we have hit a breakpoint whilst 'in' an it block?
       
   849 					// can we check the status registers to find out?
       
   850 					//
       
   851 					// see arm arm page 390.
       
   852 					//
       
   853 					// seems to depend on the itstate field. this also says what the condition code
       
   854 					// actually is, and how many instructions are left in the itblock.
       
   855 					// perhaps we can just totally ignore this state, and always do the two-instruction
       
   856 					// breakpoint thing? Not if there is any possibility that the address target
       
   857 					// would be invalid for the non-taken branch address...
       
   858 					}
       
   859 
       
   860 
       
   861 				// 32-bit encodings.
       
   862 				//
       
   863 
       
   864 				// Load word A6-23
       
   865 				// Data processing instructions a6-28
       
   866 				// 
       
   867 
       
   868 				// ARM ARM DDI0406A - section A8.6.26
       
   869 				if (inst32 & 0xFFF0FFFF == 0xE3C08F00)
       
   870 					{
       
   871 					LOG_MSG("ARM ARM DDI0406A - section A8.6.26 - BXJ is not supported");
       
   872 
       
   873 					// Decoding as per ARM ARM description
       
   874 					// TUint32 Rm = inst32 & 0x000F0000;	// not needed yet
       
   875 					}
       
   876 
       
   877 				// return from exception... SUBS PC,LR. page b6-25
       
   878 				//
       
   879 				// ARM ARM DDi046A - section B6.1.13 - SUBS PC,LR
       
   880 				//
       
   881 				// Encoding T1
       
   882 				if (inst32 & 0xFFFFFF00 == 0xF3DE8F00)
       
   883 					{
       
   884 					LOG_MSG("ARM ARM DDI0406A - section B6.1.13 - SUBS PC,LR Encoding T1");
       
   885 
       
   886 					// Decoding as per ARM ARM description
       
   887 					TUint32 imm8 = inst32 & 0x000000FF;
       
   888 					TUint32 imm32 = imm8;
       
   889 
       
   890 					// TUint32 register_form = EFalse;	// not needed for this decoding
       
   891 					// TUint32 opcode = 0x2;	// SUB	// not needed for this decoding
       
   892 					TUint32 n = 14;
       
   893 
       
   894 					// Obtain LR
       
   895 					TUint32 lrVal;
       
   896 					ReturnIfError(RegisterValue(aThread,n,lrVal));
       
   897 
       
   898 					TUint32 operand2 = imm32;	// always for Encoding T1
       
   899 					
       
   900 					TUint32 result = lrVal - operand2;
       
   901 					
       
   902 					breakAddress = result;
       
   903 					}
       
   904 
       
   905 				// ARM ARM DDI0406A - section A8.6.16 - B
       
   906 				//
       
   907 				// Branch Encoding T3
       
   908 				if (inst32 & 0xF800D000 == 0xF0008000)
       
   909 					{
       
   910 					LOG_MSG("ARM ARM DDI0406A - section A8.6.16 - B Encoding T3");
       
   911 
       
   912 					// Decoding as per ARM ARM description
       
   913 					TUint32 S = inst32 & 0x04000000 >> 26;
       
   914 					// TUint32 cond = inst32 & 0x03C00000 >> 22;	// not needed for this decoding
       
   915 					TUint32 imm6 = inst32 & 0x003F0000 >> 16;
       
   916 					TUint32 J1 = inst32 & 0x00002000 >> 13;
       
   917 					TUint32 J2 = inst32 & 0x00000800 >> 11;
       
   918 					TUint32 imm11 = inst32 & 0x000007FF;
       
   919 
       
   920 					TUint32 imm32 = S ? 0xFFFFFFFF : 0 ;
       
   921 					imm32 = (imm32 << 1) | J2;
       
   922 					imm32 = (imm32 << 1) | J1;
       
   923 					imm32 = (imm32 << 6) | imm6;
       
   924 					imm32 = (imm32 << 11) | imm11;
       
   925 					imm32 = (imm32 << 1) | 0;
       
   926 
       
   927 					breakAddress = aCurrentPC + imm32;
       
   928 					}
       
   929 
       
   930 				// ARM ARM DDI0406A - section A8.6.16 - B
       
   931 				//
       
   932 				// Branch Encoding T4
       
   933 				if (inst32 & 0xF800D000 == 0xF0009000)
       
   934 					{
       
   935 					LOG_MSG("ARM ARM DDI0406A - section A8.6.16 - B");
       
   936 
       
   937 					// Decoding as per ARM ARM description
       
   938 					TUint32 S = inst32 & 0x04000000 >> 26;
       
   939 					TUint32 imm10 = inst32 & 0x03FF0000 >> 16;
       
   940 					TUint32 J1 = inst32 & 0x00002000 >> 12;
       
   941 					TUint32 J2 = inst32 & 0x00000800 >> 11;
       
   942 					TUint32 imm11 = inst32 & 0x000003FF;
       
   943 
       
   944 					TUint32 I1 = !(J1 ^ S);
       
   945 					TUint32 I2 = !(J2 ^ S);
       
   946 
       
   947 					TUint32 imm32 = S ? 0xFFFFFFFF : 0;
       
   948 					imm32 = (imm32 << 1) | S;
       
   949 					imm32 = (imm32 << 1) | I1;
       
   950 					imm32 = (imm32 << 1) | I2;
       
   951 					imm32 = (imm32 << 10) | imm10;
       
   952 					imm32 = (imm32 << 11) | imm11;
       
   953 					imm32 = (imm32 << 1) | 0;
       
   954 
       
   955 					breakAddress = aCurrentPC + imm32;
       
   956 					}
       
   957 
       
   958 
       
   959 				// ARM ARM DDI0406A - section A8.6.225 - TBB, TBH
       
   960 				//
       
   961 				// Table Branch Byte, Table Branch Halfword
       
   962 				if (inst32 & 0xFFF0FFE0 == 0xE8D0F000)
       
   963 						{
       
   964 					LOG_MSG("ARM ARM DDI0406A - section A8.6.225 TBB,TBH Encoding T1");
       
   965 
       
   966 					// Decoding as per ARM ARM description
       
   967 					TUint32 Rn = inst32 & 0x000F0000 >> 16;
       
   968 					TUint32 H = inst32 & 0x00000010 >> 4;
       
   969 					TUint32 Rm = inst32 & 0x0000000F;
       
   970 
       
   971 					// Unpredictable?
       
   972 					if (Rm == 13 || Rm == 15)
       
   973 						{
       
   974 						LOG_MSG("ARM ARM DDI0406A - section A8.6.225 TBB,TBH Encoding T1 - Unpredictable");
       
   975 						break;
       
   976 						}
       
   977 
       
   978 					TUint32 halfwords;
       
   979 					TUint32 address;
       
   980 					ReturnIfError(RegisterValue(aThread,Rn,address));
       
   981 
       
   982 					TUint32 offset;
       
   983 					ReturnIfError(RegisterValue(aThread,Rm,offset));
       
   984 
       
   985 					if (H)
       
   986 						{
       
   987 						address += offset << 1;
       
   988 						}
       
   989 					else
       
   990 						{
       
   991 						address += offset;
       
   992 						}
       
   993 
       
   994 					ReturnIfError(ReadMem32(aThread,address,halfwords));
       
   995 
       
   996 					breakAddress = aCurrentPC + 2*halfwords;
       
   997 					break;
       
   998 					}
       
   999 
       
  1000 				// ARM ARM DDI0406A - section A8.6.55 - LDMDB, LDMEA
       
  1001 				//
       
  1002 				// LDMDB Encoding T1
       
  1003 				if (inst32 & 0xFFD02000 == 0xE9100000)
       
  1004 					{
       
  1005 					LOG_MSG("ARM ARM DDI0406 - section A8.6.55 LDMDB Encoding T1");
       
  1006 
       
  1007 					// Decoding as per ARM ARM description
       
  1008 					// TUint32 W = inst32 & 0x00200000 >> 21;	// Not needed for this encoding
       
  1009 					TUint32 Rn = inst32 & 0x000F0000 >> 16;
       
  1010 					TUint32 P = inst32 & 0x00008000 >> 15;
       
  1011 					TUint32 M = inst32 & 0x00004000 >> 14;
       
  1012 					TUint32 registers = inst32 & 0x00001FFF;
       
  1013 
       
  1014 					//TBool wback = (W == 1);	// not needed for this encoding
       
  1015 
       
  1016 					// Unpredictable?
       
  1017 					if (Rn == 15 || BitCount(registers) < 2 || ((P == 1) && (M==1)))
       
  1018 						{
       
  1019 						LOG_MSG("ARM ARM DDI0406 - section A8.6.55 LDMDB Encoding T1 - Unpredictable");
       
  1020 						break;
       
  1021 						}
       
  1022 
       
  1023 					TUint32 address;
       
  1024 					ReturnIfError(RegisterValue(aThread,Rn,address));
       
  1025 
       
  1026 					address -= 4*BitCount(registers);
       
  1027 
       
  1028 					for(TInt i=0; i<15; i++)
       
  1029 						{
       
  1030 						if (IsBitSet(registers,i))
       
  1031 							{
       
  1032 							address +=4;
       
  1033 							}
       
  1034 						}
       
  1035 
       
  1036 					if (IsBitSet(registers,15))
       
  1037 						{
       
  1038 						TUint32 RnVal = 0;
       
  1039 						ReturnIfError(ReadMem32(aThread,address,RnVal));
       
  1040 
       
  1041 						breakAddress = RnVal;
       
  1042 						}
       
  1043 					break;
       
  1044 					}
       
  1045 
       
  1046 				// ARM ARM DDI0406A - section A8.6.121 POP
       
  1047 				//
       
  1048 				// POP.W Encoding T2
       
  1049 				if (inst32 & 0xFFFF2000 == 0xE8BD0000)
       
  1050 					{
       
  1051 					LOG_MSG("ARM ARM DDI0406A - section A8.6.121 POP Encoding T2");
       
  1052 
       
  1053 					// Decoding as per ARM ARM description
       
  1054 					TUint32 registers = inst32 & 0x00001FFF;
       
  1055 					TUint32 P = inst32 & 0x00008000;
       
  1056 					TUint32 M = inst32 & 0x00004000;
       
  1057 
       
  1058 					// Unpredictable?
       
  1059 					if ( (BitCount(registers)<2) || ((P == 1)&&(M == 1)) )
       
  1060 						{
       
  1061 						LOG_MSG("ARM ARM DDI0406A - section A8.6.121 POP Encoding T2 - Unpredictable");
       
  1062 						break;
       
  1063 						}
       
  1064 
       
  1065 					TUint32 address;
       
  1066 					ReturnIfError(RegisterValue(aThread,13,address));
       
  1067 					
       
  1068 					for(TInt i=0; i< 15; i++)
       
  1069 						{
       
  1070 						if (IsBitSet(registers,i))
       
  1071 							{
       
  1072 							address += 4;
       
  1073 							}
       
  1074 						}
       
  1075 
       
  1076 					// Is the PC written?
       
  1077 					if (IsBitSet(registers,15))
       
  1078 						{
       
  1079 						// Yes
       
  1080 						ReturnIfError(ReadMem32(aThread,address,breakAddress));
       
  1081 						}
       
  1082 					}
       
  1083 
       
  1084 				// POP Encoding T3
       
  1085 				if (inst32 & 0xFFFF0FFFF == 0xF85D0B04)
       
  1086 					{
       
  1087 					LOG_MSG("ARM ARM DDI0406A - section A8.6.121 POP Encoding T3");
       
  1088 
       
  1089 					// Decoding as per ARM ARM description
       
  1090 					TUint32 Rt = inst32 & 0x0000F000 >> 12;
       
  1091 					TUint32 registers = 1 << Rt;
       
  1092 
       
  1093 					// Unpredictable?
       
  1094 					if (Rt == 13 || Rt == 15)
       
  1095 						{
       
  1096 						LOG_MSG("ARM ARM DDI0406A - section A8.6.121 POP Encoding T3 - Unpredictable");
       
  1097 						break;
       
  1098 						}
       
  1099 					
       
  1100 					TUint32 address;
       
  1101 					ReturnIfError(RegisterValue(aThread,13,address));
       
  1102 					
       
  1103 					for(TInt i=0; i< 15; i++)
       
  1104 						{
       
  1105 						if (IsBitSet(registers,i))
       
  1106 							{
       
  1107 							address += 4;
       
  1108 							}
       
  1109 						}
       
  1110 
       
  1111 					// Is the PC written?
       
  1112 					if (IsBitSet(registers,15))
       
  1113 						{
       
  1114 						// Yes
       
  1115 						ReturnIfError(ReadMem32(aThread,address,breakAddress));
       
  1116 						}
       
  1117 
       
  1118 					break;
       
  1119 					}
       
  1120 
       
  1121 				// ARM ARM DDI0406A - section A8.6.53 LDM
       
  1122 				//
       
  1123 				// Load Multiple Encoding T2 
       
  1124 				if ((inst32 & 0xFFD02000) == 0xE8900000)
       
  1125 					{
       
  1126 					LOG_MSG("ARM ARM DDI0406A - section A8.6.53 LDM Encoding T2");
       
  1127 
       
  1128 					// Decoding as per ARM ARM description
       
  1129 					TUint32 W = inst32 & 0x0020000 >> 21;
       
  1130 					TUint32 Rn = inst32 & 0x000F0000 >> 16;
       
  1131 					TUint32 P = inst32 & 0x00008000 >> 15;
       
  1132 					TUint32 M = inst32 & 0x00004000 >> 14;
       
  1133 					TUint32 registers = inst32 & 0x0000FFFF;
       
  1134 					TUint32 register_list = inst32 & 0x00001FFF;
       
  1135 				
       
  1136 					// POP?
       
  1137 					if ( (W == 1) && (Rn == 13) )
       
  1138 						{
       
  1139 						// POP instruction
       
  1140 						LOG_MSG("ARM ARM DDI0406A - section A8.6.53 LDM Encoding T2 - POP");
       
  1141 						}
       
  1142 
       
  1143 					// Unpredictable?
       
  1144 					if (Rn == 15 || BitCount(register_list) < 2 || ((P == 1) && (M == 1)) )
       
  1145 						{
       
  1146 						LOG_MSG("ARM ARM DDI0406A - section A8.6.53 LDM Encoding T2 - Unpredictable");
       
  1147 						break;
       
  1148 						}
       
  1149 					
       
  1150 					TUint32 RnVal;
       
  1151 					ReturnIfError(RegisterValue(aThread,Rn,RnVal));
       
  1152 
       
  1153 					TUint32 address = RnVal;
       
  1154 
       
  1155 					// Calculate offset of address
       
  1156 					for(TInt i = 0; i < 15; i++)
       
  1157 						{
       
  1158 						if (IsBitSet(registers,i))
       
  1159 						{
       
  1160 							address += 4;
       
  1161 						}
       
  1162 						}
       
  1163 
       
  1164 					// Does it load the PC?
       
  1165 					if (IsBitSet(registers,15))
       
  1166 						{
       
  1167 						// Obtain the value loaded into the PC
       
  1168 						ReturnIfError(ReadMem32(aThread,address,breakAddress));
       
  1169 						}
       
  1170 					break;
       
  1171 
       
  1172 					}
       
  1173 
       
  1174 				// ARM ARM DDI0406A - section B6.1.8 RFE
       
  1175 				//
       
  1176 				// Return From Exception Encoding T1 RFEDB
       
  1177 				if ((inst32 & 0xFFD0FFFF) == 0xE810C000)
       
  1178 					{
       
  1179 					LOG_MSG("ARM ARM DDI0406A - section B6.1.8 RFE Encoding T1");
       
  1180 
       
  1181 					// Decoding as per ARM ARM description
       
  1182 					// TUint32 W = (inst32 & 0x00200000) >> 21;	// not needed for this encoding
       
  1183 					TUint32 Rn = (inst32 & 0x000F0000) >> 16;
       
  1184 					
       
  1185 					// TBool wback = (W == 1);	// not needed for this encoding
       
  1186 					TBool increment = EFalse;
       
  1187 					TBool wordhigher = EFalse;
       
  1188 
       
  1189 					// Do calculation
       
  1190 					if (Rn == 15)
       
  1191 						{
       
  1192 						// Unpredictable 
       
  1193 						LOG_MSG("ARM ARM DDI0406A - section B6.1.8 RFE Encoding T1 - Unpredictable");
       
  1194 						break;
       
  1195 						}
       
  1196 
       
  1197 					TUint32 RnVal = 0;
       
  1198 					ReturnIfError(RegisterValue(aThread,Rn,RnVal));
       
  1199 
       
  1200 					TUint32 address = 0;
       
  1201 					ReturnIfError(ReadMem32(aThread,RnVal,address));
       
  1202 
       
  1203 					if (increment)
       
  1204 						{
       
  1205 						address -= 8;
       
  1206 						}
       
  1207 
       
  1208 					if (wordhigher)
       
  1209 						{
       
  1210 						address += 4;
       
  1211 						}
       
  1212 
       
  1213 					breakAddress = address;
       
  1214 					break;
       
  1215 					}
       
  1216 
       
  1217 				// Return From Exception Encoding T2 RFEIA
       
  1218 				if ((inst32 & 0xFFD0FFFF) == 0xE990C000)
       
  1219 					{
       
  1220 					LOG_MSG("ARM ARM DDI0406A - section B6.1.8 RFE Encoding T2");
       
  1221 
       
  1222 					// Decoding as per ARM ARM description
       
  1223 					// TUint32 W = (inst32 & 0x00200000) >> 21;	// not needed for this encoding
       
  1224 					TUint32 Rn = (inst32 & 0x000F0000) >> 16;
       
  1225 					
       
  1226 					// TBool wback = (W == 1);	// not needed for this encoding
       
  1227 					TBool increment = ETrue;
       
  1228 					TBool wordhigher = EFalse;
       
  1229 
       
  1230 					// Do calculation
       
  1231 					if (Rn == 15)
       
  1232 						{
       
  1233 						// Unpredictable 
       
  1234 						LOG_MSG("ARM ARM DDI0406A - section B6.1.8 RFE Encoding T2 - Unpredictable");
       
  1235 						break;
       
  1236 						}
       
  1237 
       
  1238 					TUint32 RnVal = 0;
       
  1239 					ReturnIfError(RegisterValue(aThread,Rn,RnVal));
       
  1240 
       
  1241 					TUint32 address = 0;
       
  1242 					ReturnIfError(ReadMem32(aThread,RnVal,address));
       
  1243 
       
  1244 					if (increment)
       
  1245 						{
       
  1246 						address -= 8;
       
  1247 						}
       
  1248 
       
  1249 					if (wordhigher)
       
  1250 						{
       
  1251 						address += 4;
       
  1252 						}
       
  1253 
       
  1254 					breakAddress = RnVal;
       
  1255 					break;
       
  1256 					}
       
  1257 
       
  1258 				// Return From Exception Encoding A1 RFE<amode>
       
  1259 				if ((inst32 & 0xFE50FFFF) == 0xF8100A00)
       
  1260 					{
       
  1261 					LOG_MSG("ARM ARM DDI0406A - section B6.1.8 RFE Encoding A1");
       
  1262 
       
  1263 					// Decoding as per ARM ARM description
       
  1264 					TUint32 P = (inst32 & 0x01000000) >> 24;
       
  1265 					TUint32 U = (inst32 & 0x00800000) >> 23;
       
  1266 					// TUint32 W = (inst32 & 0x00200000) >> 21; // not needed for this encoding
       
  1267 					TUint32 Rn = (inst32 & 0x000F0000) >> 16;	
       
  1268 					
       
  1269 					// TBool wback = (W == 1);	// not needed for this encoding
       
  1270 					TBool increment = (U == 1);
       
  1271 					TBool wordhigher = (P == U);
       
  1272 
       
  1273 					// Do calculation
       
  1274 					if (Rn == 15)
       
  1275 						{
       
  1276 						// Unpredictable 
       
  1277 						LOG_MSG("ARM ARM DDI0406A - section B6.1.8 RFE Encoding A1 - Unpredictable");
       
  1278 						break;
       
  1279 						}
       
  1280 
       
  1281 					TUint32 RnVal = 0;
       
  1282 					ReturnIfError(RegisterValue(aThread,Rn,RnVal));
       
  1283 
       
  1284 					TUint32 address = 0;
       
  1285 					ReturnIfError(ReadMem32(aThread,RnVal,address));
       
  1286 
       
  1287 					if (increment)
       
  1288 						{
       
  1289 						address -= 8;
       
  1290 						}
       
  1291 
       
  1292 					if (wordhigher)
       
  1293 						{
       
  1294 						address += 4;
       
  1295 						}
       
  1296 
       
  1297 					breakAddress = address;
       
  1298 					break;
       
  1299 					}
       
  1300 				}
       
  1301 
       
  1302 			// v4T/v5T/v6T instructions
       
  1303 			switch(thumb_opcode(inst))
       
  1304 				{
       
  1305 				case 0x08:
       
  1306 					{
       
  1307 					// Data-processing. See ARM ARM DDI0406A, section A6-8, A6.2.2.
       
  1308 
       
  1309 					if ((thumb_inst_7_15(inst) == 0x08F))
       
  1310 						{
       
  1311 						// BLX(2)
       
  1312 						err = iChannel->ReadKernelRegisterValue(aThread, ((inst & 0x0078) >> 3), breakAddress);
       
  1313 						if(err != KErrNone)
       
  1314 							{
       
  1315 							LOG_MSG2("Non-zero error code discarded: %d", err);
       
  1316 							}
       
  1317 
       
  1318 						if ((breakAddress & 0x00000001) == 0)
       
  1319 							{
       
  1320 							aChangingModes = ETrue;
       
  1321 							}
       
  1322 
       
  1323 						breakAddress &= 0xFFFFFFFE;
       
  1324 
       
  1325 						// Report how we decoded this instruction
       
  1326 						LOG_MSG("DRMDStepping::PCAfterInstructionExecutes: Decoded as BLX (2)");
       
  1327 						}
       
  1328 					else if (thumb_inst_7_15(inst) == 0x08E)
       
  1329 						{
       
  1330 						// BX
       
  1331 						err = iChannel->ReadKernelRegisterValue(aThread, ((inst & 0x0078) >> 3), breakAddress);
       
  1332 						if(err != KErrNone)
       
  1333 							{
       
  1334 							LOG_MSG2("Non-zero error code discarded: %d", err);
       
  1335 							}
       
  1336 
       
  1337 						if ((breakAddress & 0x00000001) == 0)
       
  1338 							{
       
  1339 							aChangingModes = ETrue;
       
  1340 							}
       
  1341 						
       
  1342 						breakAddress &= 0xFFFFFFFE;
       
  1343 
       
  1344 						// Report how we decoded this instruction
       
  1345 						LOG_MSG("DRMDStepping::PCAfterInstructionExecutes: Decoded as BX");
       
  1346 						}
       
  1347 					else if ((thumb_inst_8_15(inst) == 0x46) && ((inst & 0x87) == 0x87))
       
  1348 						{
       
  1349 						// MOV with PC as the destination
       
  1350 						err = iChannel->ReadKernelRegisterValue(aThread, ((inst & 0x0078) >> 3), breakAddress);
       
  1351 						if(err != KErrNone)
       
  1352 							{
       
  1353 							LOG_MSG2("Non-zero error code discarded: %d", err);
       
  1354 							}
       
  1355 
       
  1356 						// Report how we decoded this instruction
       
  1357 						LOG_MSG("DRMDStepping::PCAfterInstructionExecutes: Decoded as MOV with PC as the destination");
       
  1358 						}
       
  1359 					else if ((thumb_inst_8_15(inst) == 0x44) && ((inst & 0x87) == 0x87))
       
  1360 						{
       
  1361 						// ADD with PC as the destination
       
  1362 						err = iChannel->ReadKernelRegisterValue(aThread, ((inst & 0x0078) >> 3), breakAddress);
       
  1363 						if(err != KErrNone)
       
  1364 							{
       
  1365 							LOG_MSG2("Non-zero error code discarded: %d", err);
       
  1366 							}
       
  1367 						breakAddress += aCurrentPC + 4; // +4 because we need to use the PC+4 according to ARM ARM DDI0406A, section A6.1.2.
       
  1368 
       
  1369 						// Report how we decoded this instruction
       
  1370 						LOG_MSG("DRMDStepping::PCAfterInstructionExecutes: Decoded as ADD with PC as the destination");
       
  1371 						}
       
  1372 					break;
       
  1373 					}
       
  1374 				case 0x13:
       
  1375 					{
       
  1376 					// Load/Store single data item. See ARM ARM DDI0406A, section A6-10
       
  1377 
       
  1378 					//This instruction doesn't modify the PC.
       
  1379 
       
  1380 					//if (thumb_inst_8_15(inst) == 0x9F)
       
  1381 					//{
       
  1382 						// LDR(4) with the PC as the destination
       
  1383 					//	breakAddress = ReadRegister(aThread, SP_REGISTER) + (4 * (inst & 0x00FF));
       
  1384 					//}
       
  1385 
       
  1386 					// Report how we decoded this instruction
       
  1387 					LOG_MSG("DRMDStepping::PCAfterInstructionExecutes: Decoded as This instruction doesn't modify the PC.");
       
  1388 					break;
       
  1389 					}
       
  1390 				case 0x17:
       
  1391 					{
       
  1392 					// Misc 16-bit instruction. See ARM ARM DDI0406A, section A6-11
       
  1393 
       
  1394 					if (thumb_inst_8_15(inst) == 0xBD)
       
  1395 						{
       
  1396 						// POP with the PC in the list
       
  1397 						TUint32 regList = (inst & 0x00FF);
       
  1398 						TInt offset = 0;
       
  1399 						err = iChannel->ReadKernelRegisterValue(aThread,  SP_REGISTER, (T4ByteRegisterValue&)offset);
       
  1400 						if(err != KErrNone)
       
  1401 							{
       
  1402 							LOG_MSG2("Non-zero error code discarded: %d", err);
       
  1403 							}
       
  1404 						offset += (iChannel->Bitcount(regList) * 4);
       
  1405 
       
  1406 						TBuf8<4> destination;
       
  1407 						err = iChannel->DoReadMemory(aThread, offset, 4, destination);
       
  1408 						
       
  1409 						if (KErrNone == err)
       
  1410 							{
       
  1411 							breakAddress = *(TUint32 *)destination.Ptr();
       
  1412 
       
  1413 							if ((breakAddress & 0x00000001) == 0)
       
  1414 								{
       
  1415 								aChangingModes = ETrue;
       
  1416 								}
       
  1417 
       
  1418 							breakAddress &= 0xFFFFFFFE;
       
  1419 							}
       
  1420 						else
       
  1421 							{
       
  1422 							LOG_MSG("Error reading memory in decoding step instruction");
       
  1423 							}
       
  1424 
       
  1425 						// Report how we decoded this instruction
       
  1426 						LOG_MSG("DRMDStepping::PCAfterInstructionExecutes: Decoded as POP with the PC in the list");
       
  1427 						}
       
  1428 					break;
       
  1429 					}
       
  1430 				case 0x1A:
       
  1431 				case 0x1B:
       
  1432 					{
       
  1433 					// Conditional branch, and supervisor call. See ARM ARM DDI0406A, section A6-13
       
  1434 
       
  1435 					if (thumb_inst_8_15(inst) < 0xDE)
       
  1436 						{
       
  1437 						// B(1) conditional branch
       
  1438 						if (IsExecuted(((inst & 0x0F00) >> 8), aStatusRegister))
       
  1439 							{
       
  1440 							TUint32 offset = ((inst & 0x000000FF) << 1);
       
  1441 							if (offset & 0x00000100)
       
  1442 								{
       
  1443 								offset |= 0xFFFFFF00;
       
  1444 								}
       
  1445 							
       
  1446 							breakAddress = aCurrentPC + 4 + offset;
       
  1447 
       
  1448 							// Report how we decoded this instruction
       
  1449 							LOG_MSG("DRMDStepping::PCAfterInstructionExecutes: Decoded as B(1) conditional branch");
       
  1450 							}
       
  1451 						}
       
  1452 					break;
       
  1453 					}
       
  1454 				case 0x1C:
       
  1455 					{
       
  1456 					// Unconditional branch, See ARM ARM DDI0406A, section A8-44.
       
  1457 
       
  1458 					// B(2) unconditional branch
       
  1459 					TUint32 offset = (inst & 0x000007FF) << 1;
       
  1460 					if (offset & 0x00000800)
       
  1461 						{
       
  1462 						offset |= 0xFFFFF800;
       
  1463 						}
       
  1464 					
       
  1465 					breakAddress = aCurrentPC + 4 + offset;
       
  1466 
       
  1467 					// Report how we decoded this instruction
       
  1468 					LOG_MSG("DRMDStepping::PCAfterInstructionExecutes: Decoded as B(2) unconditional branch");
       
  1469 
       
  1470 					break;
       
  1471 					}
       
  1472 				case 0x1D:
       
  1473 					{
       
  1474 					if (!(inst & 0x0001))
       
  1475 						{
       
  1476 						// BLX(1)
       
  1477 						err = iChannel->ReadKernelRegisterValue(aThread, LINK_REGISTER, breakAddress);
       
  1478 						if(err != KErrNone)
       
  1479 							{
       
  1480 							LOG_MSG2("Non-zero error code discarded: %d", err);
       
  1481 							}
       
  1482 						breakAddress +=  ((inst & 0x07FF) << 1);
       
  1483 						if ((breakAddress & 0x00000001) == 0)
       
  1484 							{
       
  1485 							aChangingModes = ETrue;
       
  1486 							}
       
  1487 
       
  1488 						breakAddress &= 0xFFFFFFFC;
       
  1489 
       
  1490 						// Report how we decoded this instruction
       
  1491 						LOG_MSG("DRMDStepping::PCAfterInstructionExecutes: Decoded as BLX(1)");
       
  1492 
       
  1493 						}
       
  1494 					break;
       
  1495 					}
       
  1496 				case 0x1E:
       
  1497 					{
       
  1498 					// Check for ARMv7 CPU
       
  1499 					if(cpuid == 0xC0)
       
  1500 						{
       
  1501 						// BL/BLX 32-bit instruction
       
  1502 						aNewRangeEnd += 4;
       
  1503 
       
  1504 						breakAddress = (TUint32)thumb_instr_b_dest(inst32, aCurrentPC);
       
  1505 
       
  1506 						if((inst32 >> 27) == 0x1D)
       
  1507 							{
       
  1508 							// BLX(1)
       
  1509 							if ((breakAddress & 0x00000001) == 0)
       
  1510 								{
       
  1511 								aChangingModes = ETrue;
       
  1512 								}
       
  1513 
       
  1514 							breakAddress &= 0xFFFFFFFC;
       
  1515 
       
  1516 							// Report how we decoded this instruction
       
  1517 							LOG_MSG("DRMDStepping::PCAfterInstructionExecutes: Decoded as 32-bit BLX(1)");
       
  1518 							}
       
  1519 						else
       
  1520 							{
       
  1521 							// Report how we decoded this instruction
       
  1522 							LOG_MSG("DRMDStepping::PCAfterInstructionExecutes: 32-bit BL instruction");
       
  1523 							}
       
  1524 						LOG_MSG2(" 32-bit BL/BLX instruction: breakAddress = 0x%X", breakAddress);
       
  1525 						} // if(cpuid == 0xC0)
       
  1526 					else
       
  1527 						{
       
  1528 						// BL/BLX prefix - destination is encoded in this and the next instruction
       
  1529 						aNewRangeEnd += 2;
       
  1530 
       
  1531 						// Report how we decoded this instruction
       
  1532 						LOG_MSG("DRMDStepping::PCAfterInstructionExecutes: BL/BLX prefix - destination is encoded in this and the next instruction");
       
  1533 						}
       
  1534 
       
  1535 					break;
       
  1536 					}
       
  1537 				case 0x1F:
       
  1538 					{
       
  1539 					// BL
       
  1540 					err = iChannel->ReadKernelRegisterValue(aThread, LINK_REGISTER, breakAddress);
       
  1541 					if(err != KErrNone)
       
  1542 						{
       
  1543 						LOG_MSG2("Non-zero error code discarded: %d", err);
       
  1544 						}
       
  1545 					breakAddress += ((inst & 0x07FF) << 1);
       
  1546 
       
  1547 					// Report how we decoded this instruction
       
  1548 					LOG_MSG("DRMDStepping::PCAfterInstructionExecutes: Decoded as BL");
       
  1549 					break;
       
  1550 					}
       
  1551 				default:
       
  1552 					{
       
  1553 					// Don't know any better at this point!
       
  1554 					LOG_MSG("DRMDStepping::PCAfterInstructionExecutes:- default to next instruction");
       
  1555 					}
       
  1556 					break;
       
  1557 				} // switch(thumb_opcode(inst))
       
  1558 			} // case Debug::EThumbMode:
       
  1559 		break;
       
  1560 
       
  1561 		case Debug::EThumb2EEMode:
       
  1562 			{
       
  1563 			// Not yet supported
       
  1564 			LOG_MSG("DRMDStepping::PCAfterInstructionExecutes - Debug::EThumb2Mode is not supported");
       
  1565 
       
  1566 			}
       
  1567 			break;
       
  1568 
       
  1569 		default:
       
  1570 			LOG_MSG("DRMDStepping::PCAfterInstructionExecutes - Cannot determine CPU mode architecture");
       
  1571 		} // switch(mode)
       
  1572 
       
  1573 	LOG_MSG2("DRMDStepping::PCAfterInstructionExecutes : return 0x%08x",breakAddress);
       
  1574 	return breakAddress;
       
  1575 	}
       
  1576 
       
  1577 // Obtain a 32-bit memory value with minimum fuss
       
  1578 TInt DRMDStepping::ReadMem32(DThread* aThread, const TUint32 aAddress, TUint32& aValue)
       
  1579 	{
       
  1580 	TBuf8<4> valBuf;
       
  1581 	TInt err = iChannel->DoReadMemory(aThread, aAddress, 4, valBuf);
       
  1582 	if (err != KErrNone)
       
  1583 		{
       
  1584 		LOG_MSG2("DRMDStepping::ReadMem32 failed to read memory at 0x%08x", aAddress);
       
  1585 		return err;
       
  1586 		}
       
  1587 
       
  1588 	aValue = *(TUint32 *)valBuf.Ptr();
       
  1589 
       
  1590 	return KErrNone;
       
  1591 	}
       
  1592 
       
  1593 // Obtain a 16-bit memory value with minimum fuss
       
  1594 TInt DRMDStepping::ReadMem16(DThread* aThread, const TUint32 aAddress, TUint16& aValue)
       
  1595 	{
       
  1596 	TBuf8<2> valBuf;
       
  1597 	TInt err = iChannel->DoReadMemory(aThread, aAddress, 2, valBuf);
       
  1598 	if (err != KErrNone)
       
  1599 		{
       
  1600 		LOG_MSG2("DRMDStepping::ReadMem16 failed to read memory at 0x%08x", aAddress);
       
  1601 		return err;
       
  1602 		}
       
  1603 
       
  1604 	aValue = *(TUint16 *)valBuf.Ptr();
       
  1605 
       
  1606 	return KErrNone;
       
  1607 	}
       
  1608 
       
  1609 // Obtain a 16-bit memory value with minimum fuss
       
  1610 TInt DRMDStepping::ReadMem8(DThread* aThread, const TUint32 aAddress, TUint8& aValue)
       
  1611 	{
       
  1612 	TBuf8<1> valBuf;
       
  1613 	TInt err = iChannel->DoReadMemory(aThread, aAddress, 1, valBuf);
       
  1614 	if (err != KErrNone)
       
  1615 		{
       
  1616 		LOG_MSG2("DRMDStepping::ReadMem8 failed to read memory at 0x%08x", aAddress);
       
  1617 		return err;
       
  1618 		}
       
  1619 
       
  1620 	aValue = *(TUint8 *)valBuf.Ptr();
       
  1621 
       
  1622 	return KErrNone;
       
  1623 	}
       
  1624 
       
  1625 // Obtain a core register value with minimum fuss
       
  1626 TInt DRMDStepping::RegisterValue(DThread *aThread, const TUint32 aKernelRegisterId, TUint32 &aValue)
       
  1627 	{
       
  1628 	TInt err = iChannel->ReadKernelRegisterValue(aThread, aKernelRegisterId, aValue);
       
  1629 	if(err != KErrNone)
       
  1630 		{
       
  1631 		LOG_MSG3("DRMDStepping::RegisterValue failed to read register %d err = %d", aKernelRegisterId, err);
       
  1632 		}
       
  1633 		return err;
       
  1634 	}
       
  1635 
       
  1636 
       
  1637 // Encodings from ARM ARM DDI0406A, section 9.2.1
       
  1638 enum TThumb2EEOpcode
       
  1639 	{
       
  1640 	EThumb2HDP,		// Handler Branch with Parameter
       
  1641 	EThumb2UNDEF,	// UNDEFINED
       
  1642 	EThumb2HB,		// Handler Branch, Handler Branch with Link
       
  1643 	EThumb2HBLP,	// Handle Branch with Link and Parameter
       
  1644 	EThumb2LDRF,	// Load Register from a frame
       
  1645 	EThumb2CHKA,	// Check Array
       
  1646 	EThumb2LDRL,	// Load Register from a literal pool
       
  1647 	EThumb2LDRA,	// Load Register (array operations)
       
  1648 	EThumb2STR		// Store Register to a frame
       
  1649 	};
       
  1650 
       
  1651 //
       
  1652 // DRMDStepping::ShiftedRegValue
       
  1653 //
       
  1654 TUint32 DRMDStepping::ShiftedRegValue(DThread *aThread, TUint32 aInstruction, TUint32 aCurrentPC, TUint32 aStatusRegister)
       
  1655 	{
       
  1656 	LOG_MSG("DRMDStepping::ShiftedRegValue()");
       
  1657 
       
  1658 	TUint32 shift = 0;
       
  1659 	if (aInstruction & 0x10)	// bit 4
       
  1660 		{
       
  1661 		shift = (arm_rs(aInstruction) == PC_REGISTER ? aCurrentPC + 8 : aStatusRegister) & 0xFF;
       
  1662 		}
       
  1663 	else
       
  1664 		{
       
  1665 		shift = arm_data_c(aInstruction);
       
  1666 		}
       
  1667 	
       
  1668 	TInt rm = arm_rm(aInstruction);
       
  1669 	
       
  1670 	TUint32 res = 0;
       
  1671 	if(rm == PC_REGISTER)
       
  1672 		{
       
  1673 		res = aCurrentPC + ((aInstruction & 0x10) ? 12 : 8);
       
  1674 		}
       
  1675 	else
       
  1676 		{
       
  1677 		TInt err = iChannel->ReadKernelRegisterValue(aThread, rm, res);
       
  1678 		if(err != KErrNone)
       
  1679 			{
       
  1680 			LOG_MSG2("DRMDStepping::ShiftedRegValue - Non-zero error code discarded: %d", err);
       
  1681 			}
       
  1682 		}
       
  1683 
       
  1684 	switch(arm_data_shift(aInstruction))
       
  1685 		{
       
  1686 		case 0:			// LSL
       
  1687 			{
       
  1688 			res = shift >= 32 ? 0 : res << shift;
       
  1689 			break;
       
  1690 			}
       
  1691 		case 1:			// LSR
       
  1692 			{
       
  1693 			res = shift >= 32 ? 0 : res >> shift;
       
  1694 			break;
       
  1695 			}
       
  1696 		case 2:			// ASR
       
  1697 			{
       
  1698 			if (shift >= 32)
       
  1699 			shift = 31;
       
  1700 			res = ((res & 0x80000000L) ? ~((~res) >> shift) : res >> shift);
       
  1701 			break;
       
  1702 			}
       
  1703 		case 3:			// ROR/RRX
       
  1704 			{
       
  1705 			shift &= 31;
       
  1706 			if (shift == 0)
       
  1707 				{
       
  1708 				res = (res >> 1) | ((aStatusRegister & arm_carry_bit()) ? 0x80000000L : 0);
       
  1709 				}
       
  1710 			else
       
  1711 				{
       
  1712 				res = (res >> shift) | (res << (32 - shift));
       
  1713 				}
       
  1714 			break;
       
  1715 			}
       
  1716 		}
       
  1717 
       
  1718 	return res & 0xFFFFFFFF;
       
  1719 }
       
  1720 
       
  1721 //
       
  1722 // DRMDStepping::CurrentPC
       
  1723 //
       
  1724 // 
       
  1725 //
       
  1726 TInt DRMDStepping::CurrentPC(DThread* aThread, TUint32& aPC)
       
  1727 	{
       
  1728 	LOG_MSG("DRMDStepping::CurrentPC");
       
  1729 
       
  1730 	TInt err = iChannel->ReadKernelRegisterValue(aThread, PC_REGISTER, aPC);
       
  1731 	if(err != KErrNone)
       
  1732 		{
       
  1733 		// We don't know the current PC for this thread!
       
  1734 		LOG_MSG("DRMDStepping::CurrentPC - Failed to read the current PC");
       
  1735 		
       
  1736 		return KErrGeneral;
       
  1737 		}
       
  1738 
       
  1739 	LOG_MSG2("DRMDStepping::CurrentPC 0x%08x", aPC);
       
  1740 
       
  1741 	return KErrNone;
       
  1742 	}
       
  1743 
       
  1744 //
       
  1745 // DRMDStepping::CurrentCPSR
       
  1746 //
       
  1747 // 
       
  1748 //
       
  1749 TInt DRMDStepping::CurrentCPSR(DThread* aThread, TUint32& aCPSR)
       
  1750 	{
       
  1751 	LOG_MSG("DRMDStepping::CurrentCPSR");
       
  1752 
       
  1753 	TInt err = iChannel->ReadKernelRegisterValue(aThread, STATUS_REGISTER, aCPSR);
       
  1754 	if(err != KErrNone)
       
  1755 		{
       
  1756 		// We don't know the current PC for this thread!
       
  1757 		LOG_MSG("DRMDStepping::CurrentPC - Failed to read the current CPSR");
       
  1758 		
       
  1759 		return KErrGeneral;
       
  1760 		}
       
  1761 
       
  1762 	LOG_MSG2("DRMDStepping::CurrentCPSR 0x%08x", aCPSR);
       
  1763 	
       
  1764 	return KErrNone;
       
  1765 	}
       
  1766 
       
  1767 //
       
  1768 // DRMDStepping::ModifyBreaksForStep
       
  1769 //
       
  1770 // Set a temporary breakpoint at the next instruction to be executed after the one at the current PC
       
  1771 // Disable the breakpoint at the current PC if one exists
       
  1772 //
       
  1773 TInt DRMDStepping::ModifyBreaksForStep(DThread *aThread, TUint32 aRangeStart, TUint32 aRangeEnd, /*TBool aStepInto,*/ TBool aResumeOnceOutOfRange, TBool aCheckForStubs, const TUint32 aNumSteps)
       
  1774 	{
       
  1775 	LOG_MSG2("DRMDStepping::ModifyBreaksForStep() Numsteps 0x%d",aNumSteps);
       
  1776 
       
  1777 	// Validate arguments
       
  1778 	if (!aThread)
       
  1779 		{
       
  1780 		LOG_MSG("DRMDStepping::ModifyBreaksForStep() - No aThread specified to step");
       
  1781 		return KErrArgument;
       
  1782 		}
       
  1783 
       
  1784 	// Current PC
       
  1785 	TUint32 currentPC;
       
  1786 
       
  1787 	ReturnIfError(CurrentPC(aThread,currentPC));
       
  1788 	LOG_MSG2("Current PC: 0x%x", currentPC);
       
  1789 
       
  1790 	// disable breakpoint at the current PC if necessary
       
  1791 	ReturnIfError(iChannel->iBreakManager->DisableBreakAtAddress(currentPC));
       
  1792 
       
  1793 	// Current CPSR
       
  1794 	TUint32 statusRegister;
       
  1795 
       
  1796 	ReturnIfError(CurrentCPSR(aThread,statusRegister));
       
  1797 	LOG_MSG2("Current CPSR: %x", statusRegister);
       
  1798 
       
  1799 	TBool thumbMode = (statusRegister & ECpuThumb);
       
  1800 	if (thumbMode)
       
  1801 		LOG_MSG("Thumb Mode");
       
  1802 
       
  1803 	TInt instSize = thumbMode ? 2 : 4;
       
  1804 
       
  1805 	TBool changingModes = EFalse;
       
  1806 
       
  1807 	TUint32 breakAddress = 0;
       
  1808 
       
  1809 	TUint32 newRangeEnd = aRangeEnd;
       
  1810 
       
  1811 	breakAddress = PCAfterInstructionExecutes(aThread, currentPC, statusRegister, instSize, /* aStepInto, */ newRangeEnd, changingModes);
       
  1812 
       
  1813 	/*
       
  1814 	If there is already a user breakpoint at this address, we do not need to set a temp breakpoint. The program
       
  1815 	should simply stop at that address.	
       
  1816 	*/
       
  1817 	TBreakEntry* breakEntry = NULL;
       
  1818 	do
       
  1819 		{
       
  1820 		breakEntry = iChannel->iBreakManager->GetNextBreak(breakEntry);
       
  1821 		if(breakEntry && !iChannel->iBreakManager->IsTemporaryBreak(*breakEntry))
       
  1822 			{
       
  1823 			if ((breakEntry->iAddress == breakAddress) && ((breakEntry->iThreadSpecific && breakEntry->iId == aThread->iId) || (!breakEntry->iThreadSpecific && breakEntry->iId == aThread->iOwningProcess->iId)))
       
  1824 				{
       
  1825 				LOG_MSG("DRMDStepping::ModifyBreaksForStep - Breakpoint already exists at the step target address\n");
       
  1826 
       
  1827 				// note also that if this is the case, we will not keep stepping if we hit a real breakpoint, so may as well set
       
  1828 				// the step count = 0.
       
  1829 				breakEntry->iNumSteps = 0;
       
  1830 
       
  1831 				return KErrNone;
       
  1832 				}
       
  1833 			}
       
  1834 		} while(breakEntry);
       
  1835 
       
  1836 	breakEntry = NULL;
       
  1837 	do
       
  1838 		{
       
  1839 		breakEntry = iChannel->iBreakManager->GetNextBreak(breakEntry);
       
  1840 		if(breakEntry && iChannel->iBreakManager->IsTemporaryBreak(*breakEntry))
       
  1841 			{
       
  1842 			if (breakEntry->iAddress == 0)
       
  1843 				{
       
  1844 				breakEntry->iId = aThread->iId;
       
  1845 				breakEntry->iAddress = breakAddress;
       
  1846 				breakEntry->iThreadSpecific = ETrue;
       
  1847 
       
  1848 				TBool realThumbMode = (thumbMode && !changingModes) || (!thumbMode && changingModes);
       
  1849 
       
  1850 				// Need to set the correct type of breakpoint for the mode we are in
       
  1851 				// and the the one we are changing into
       
  1852 				if(realThumbMode)
       
  1853 					{
       
  1854 					// We are remaining in Thumb mode
       
  1855 					breakEntry->iMode = EThumbMode;
       
  1856 					}
       
  1857 				else
       
  1858 					{
       
  1859 					// We are switching to ARM mode
       
  1860 					breakEntry->iMode = EArmMode;
       
  1861 					}
       
  1862 
       
  1863 				breakEntry->iResumeOnceOutOfRange = aResumeOnceOutOfRange;
       
  1864 				breakEntry->iSteppingInto = ETrue /* aStepInto */;
       
  1865 				breakEntry->iRangeStart = 0;	// no longer used
       
  1866 				breakEntry->iRangeEnd = 0;		// no longer used
       
  1867 
       
  1868 				LOG_MSG2("Adding temp breakpoint with id: %d", breakEntry->iBreakId);
       
  1869 				LOG_MSG2("Adding temp breakpoint with thread id: %d", aThread->iId);
       
  1870 
       
  1871 				// Record how many more steps to go after we hit this one
       
  1872 				breakEntry->iNumSteps = aNumSteps;
       
  1873 
       
  1874 				LOG_MSG3("Setting temp breakpoint id %d with %d steps to go\n", breakEntry->iBreakId, aNumSteps);
       
  1875 
       
  1876 				return iChannel->iBreakManager->DoEnableBreak(*breakEntry, ETrue);			
       
  1877 				}
       
  1878 			}
       
  1879 		} while(breakEntry);
       
  1880 	LOG_MSG("ModifyBreaksForStep : Failed to set suitable breakpoint for stepping");
       
  1881 	return KErrNoMemory;	// should never get here
       
  1882 }
       
  1883 
       
  1884 // End of file - d-rmd-stepping.cpp