stdcpp/tsrc/Stdcpp_test/stlport/auto/stlport_logic/src/logicor.cpp
author Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
Fri, 11 Jun 2010 15:26:22 +0300
changeset 34 5fae379060a7
parent 31 ce057bb09d0b
child 45 4b03adbd26ca
permissions -rw-r--r--
Revision: 201023 Kit: 2010123

 
// STLport regression testsuite component.
// To compile as a separate example, please #define MAIN.

#include <iostream>
#include <algorithm>
#include <functional>

#ifdef MAIN 
#define logicor_test main
#endif

#if !defined (STLPORT) || defined(__STL_USE_NAMESPACES)
using namespace std;
#endif
int logicor_test(int, char**)
{
  cout<<"Results of logicor_test:"<<endl;
int input1 [4] = { 1, 1, 0, 1 };
int input2 [4] = { 0, 1, 0, 0 };
int failures = 0;
  int output [4];
  transform((int*)input1, (int*)input1 + 4, (int*)input2, (int*)output, logical_or<bool>());
  for(int i = 0; i < 4; i++)
    cout << output[i] << endl;
    if(output[0] != 1)
    failures++;
    if(output[1] != 1)
    failures++;
    if(output[2] !=0 )
    failures++;
	if(output[3] != 1)
    failures++;
  return failures;
}